mb/google/nissa/var/craask: Modify GPIOs for NVMe
Modify NVMe clkreq pin to GPP_D7 from GPP_D6.The design change is for commonality of GPIO settings. To reserve craask GPIO table and add craaskneto/craaskino's NVMe GPIO setting. In the change, clkreq# will be 2 and clksrc is still 1. BUG=b:259211172 TEST=Verify on reworked craask DUT to boot up from NVMe. Change-Id: If45c1a87144d5370b1ca2525295fb7947639362f Signed-off-by: Ren Kuo <ren.kuo@quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/71170 Reviewed-by: Reka Norman <rekanorman@chromium.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu@compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@@ -50,39 +50,16 @@ static const struct pad_config stylus_disable_pads[] = {
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static const struct pad_config nvme_disable_pads[] = {
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/* B4 : SSD_PERST_L */
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PAD_NC_LOCK(GPP_B4, NONE, LOCK_CONFIG),
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/* D7 : SSD_CLKREQ_ODL */
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PAD_NC(GPP_D7, NONE),
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/* D11 : EN_PP3300_SSD */
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PAD_NC_LOCK(GPP_D11, NONE, LOCK_CONFIG),
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/* E17 : SSD_PLN_L */
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PAD_NC_LOCK(GPP_E17, NONE, LOCK_CONFIG),
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/*
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* Note: don't disable GPP_D6 = SSD_CLKREQ_ODL, since this is used as
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* WWAN_EN on LTE variants.
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*/
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};
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/*
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* GPP_D6 is used as WWAN_EN on LTE variants and SSD_CLKREQ_ODL on NVMe
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* variants (there is no craask variant supporting both LTE and NVMe).
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* In craask/gpio.c, it's set to WWAN_EN since this needs to be done in
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* bootblock. So we override it to SSD_CLKREQ_ODL here for NVMe variants.
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*/
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static const struct pad_config nvme_enable_pads[] = {
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/* D6 : SRCCLKREQ1# ==> SSD_CLKREQ_ODL */
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PAD_CFG_NF(GPP_D6, NONE, DEEP, NF1),
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};
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void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
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{
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/*
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* Since GPP_D6 is used as WWAN_EN on LTE variants and SSD_CLKREQ_ODL on
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* NVMe variants, we don't support both together. If there's a variant
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* using both in the future, this GPIO handling will need to be updated.
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*/
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if (fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE)) &&
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fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME))) {
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printk(BIOS_ERR, "LTE and NVMe together is not supported on craask\n");
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}
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if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) {
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printk(BIOS_INFO, "Disable LTE-related GPIO pins on craask.\n");
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gpio_padbased_override(padbased_table, lte_disable_pads,
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@@ -107,16 +84,7 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table)
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ARRAY_SIZE(stylus_disable_pads));
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}
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if (!fw_config_is_provisioned() ||
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fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME))) {
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/*
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* Note: this must be done after lte_disable_pads, otherwise
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* GPP_D6 will be disabled again.
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*/
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printk(BIOS_INFO, "Enable NVMe SSD GPIO pins.\n");
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gpio_padbased_override(padbased_table, nvme_enable_pads,
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ARRAY_SIZE(nvme_enable_pads));
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} else {
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if (fw_config_is_provisioned() && !fw_config_probe(FW_CONFIG(STORAGE, STORAGE_NVME))) {
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printk(BIOS_INFO, "Disable NVMe SSD GPIO pins.\n");
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gpio_padbased_override(padbased_table, nvme_disable_pads,
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ARRAY_SIZE(nvme_disable_pads));
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@@ -13,8 +13,8 @@ static const struct pad_config override_gpio_table[] = {
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PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG),
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/* D6 : WWAN_EN */
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PAD_CFG_GPO(GPP_D6, 1, DEEP),
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/* D7 : WLAN_CLKREQ_ODL */
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PAD_NC(GPP_D7, NONE),
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/* D7 : SRCCLKREQ1# ==> SSD_CLKREQ_ODL */
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PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
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/* D11 : EN_PP3300_SSD */
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PAD_CFG_GPO_LOCK(GPP_D11, 1, LOCK_CONFIG),
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/* E17 : SSD_PLN_L */
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@@ -447,10 +447,10 @@ chip soc/intel/alderlake
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probe SD_CARD SD_GL9750S
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end
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device ref pcie_rp9 on
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# Enable NVMe SSD PCIe 9-12 using clk 1
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# Enable NVMe SSD PCIe 9-12 using clk 2
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register "pch_pcie_rp[PCH_RP(9)]" = "{
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.clk_src = 1,
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.clk_req = 1,
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.clk_req = 2,
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.flags = PCIE_RP_LTR | PCIE_RP_AER,
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}"
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end
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