mb/google/auron: Prepare devicetree for PCH split
Tested with BUILD_TIMELESS=1, all variants remain identical. Change-Id: I2b088b36c8e9ff9cbd47d625b14fc45ebd96532a Signed-off-by: Angel Pons <th3fanbus@gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/46702 Reviewed-by: Nico Huber <nico.h@gmx.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
Patrick Georgi
parent
ce19f4f8ad
commit
99af210456
@ -15,27 +15,6 @@ chip soc/intel/broadwell
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# Set backlight PWM value for eDP
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register "gpu_pch_backlight_pwm_hz" = "200"
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# EC range is 0x800-0x9ff
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x00fc0901"
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# EC_SMI is GPIO34
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register "alt_gp_smi_en" = "0x0004"
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register "gpe0_en_1" = "0x00000000"
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# EC_SCI is GPIO36
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register "gpe0_en_2" = "0x00000010"
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register "gpe0_en_3" = "0x00000000"
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register "gpe0_en_4" = "0x00000000"
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register "sata_port_map" = "0x1"
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register "sio_acpi_mode" = "1"
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# Force enable ASPM for PCIe Port1
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register "pcie_port_force_aspm" = "0x01"
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# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
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register "icc_clock_disable" = "0x013c0000"
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register "s0ix_enable" = "1"
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device cpu_cluster 0 on
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@ -46,40 +25,64 @@ chip soc/intel/broadwell
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device pci 00.0 on end # host bridge
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device pci 02.0 on end # vga controller
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device pci 03.0 on end # mini-hd audio
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device pci 13.0 off end # Smart Sound Audio DSP
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device pci 14.0 on end # USB3 XHCI
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device pci 15.0 on end # Serial I/O DMA
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device pci 15.1 on end # I2C0
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device pci 15.2 on end # I2C1
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device pci 15.3 off end # GSPI0
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device pci 15.4 off end # GSPI1
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device pci 15.5 off end # UART0
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device pci 15.6 off end # UART1
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT
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device pci 17.0 off end # SDIO
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device pci 19.0 off end # GbE
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device pci 1b.0 on end # High Definition Audio
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device pci 1c.0 on end # PCIe Port #1
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device pci 1c.1 off end # PCIe Port #2
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device pci 1c.2 off end # PCIe Port #3
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device pci 1c.3 off end # PCIe Port #4
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device pci 1c.4 off end # PCIe Port #5
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device pci 1c.5 off end # PCIe Port #6
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device pci 1d.0 on end # USB2 EHCI
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end
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end
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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end
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end # LPC bridge
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device pci 1f.2 on end # SATA Controller
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device pci 1f.3 off end # SMBus
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device pci 1f.6 on end # Thermal
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# chip soc/intel/broadwell/pch
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# EC range is 0x800-0x9ff
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x00fc0901"
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# EC_SMI is GPIO34
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register "alt_gp_smi_en" = "0x0004"
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register "gpe0_en_1" = "0x00000000"
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# EC_SCI is GPIO36
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register "gpe0_en_2" = "0x00000010"
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register "gpe0_en_3" = "0x00000000"
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register "gpe0_en_4" = "0x00000000"
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register "sata_port_map" = "0x1"
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register "sio_acpi_mode" = "1"
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# Force enable ASPM for PCIe Port1
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register "pcie_port_force_aspm" = "0x01"
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# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
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register "icc_clock_disable" = "0x013c0000"
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device pci 13.0 off end # Smart Sound Audio DSP
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device pci 14.0 on end # USB3 XHCI
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device pci 15.0 on end # Serial I/O DMA
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device pci 15.1 on end # I2C0
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device pci 15.2 on end # I2C1
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device pci 15.3 off end # GSPI0
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device pci 15.4 off end # GSPI1
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device pci 15.5 off end # UART0
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device pci 15.6 off end # UART1
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device pci 16.0 on end # Management Engine Interface 1
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device pci 16.1 off end # Management Engine Interface 2
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device pci 16.2 off end # Management Engine IDE-R
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device pci 16.3 off end # Management Engine KT
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device pci 17.0 off end # SDIO
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device pci 19.0 off end # GbE
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device pci 1b.0 on end # High Definition Audio
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device pci 1c.0 on end # PCIe Port #1
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device pci 1c.1 off end # PCIe Port #2
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device pci 1c.2 off end # PCIe Port #3
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device pci 1c.3 off end # PCIe Port #4
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device pci 1c.4 off end # PCIe Port #5
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device pci 1c.5 off end # PCIe Port #6
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device pci 1d.0 on end # USB2 EHCI
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device pci 1e.0 off end # PCI bridge
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device pci 1f.0 on
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chip drivers/pc80/tpm
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device pnp 0c31.0 on end
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end
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chip ec/google/chromeec
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device pnp 0c09.0 on end
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end
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end # LPC bridge
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device pci 1f.2 on end # SATA Controller
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device pci 1f.3 off end # SMBus
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device pci 1f.6 on end # Thermal
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# end
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end
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end
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@ -7,9 +7,11 @@ chip soc/intel/broadwell
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register "gpu_panel_power_backlight_on_delay" = "70" # 7ms
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register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
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# DTLE DATA / EDGE values
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register "sata_port0_gen3_dtle" = "0x5"
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register "sata_port1_gen3_dtle" = "0x5"
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device domain 0 on end
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device domain 0 on
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# chip soc/intel/broadwell/pch
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# DTLE DATA / EDGE values
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register "sata_port0_gen3_dtle" = "0x5"
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register "sata_port1_gen3_dtle" = "0x5"
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# end
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end
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end
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@ -7,9 +7,11 @@ chip soc/intel/broadwell
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register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms
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register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
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# DTLE DATA / EDGE values
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register "sata_port0_gen3_dtle" = "0x7"
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register "sata_port1_gen3_dtle" = "0x5"
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device domain 0 on end
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device domain 0 on
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# chip soc/intel/broadwell/pch
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# DTLE DATA / EDGE values
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register "sata_port0_gen3_dtle" = "0x7"
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register "sata_port1_gen3_dtle" = "0x5"
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# end
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end
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end
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@ -7,32 +7,34 @@ chip soc/intel/broadwell
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register "gpu_panel_power_backlight_on_delay" = "70" # 7ms
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register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
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register "sata_devslp_disable" = "0x1"
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register "sio_i2c0_voltage" = "1" # 1.8V
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register "sio_i2c1_voltage" = "0" # 3.3V
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# DTLE DATA / EDGE values
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register "sata_port0_gen3_dtle" = "0x5"
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register "sata_port1_gen3_dtle" = "0x5"
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# Force enable ASPM for PCIe Port 5
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register "pcie_port_force_aspm" = "0x10"
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# Enable port coalescing
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register "pcie_port_coalesce" = "1"
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# Disable PCIe CLKOUT 1,5 and CLKOUT_XDP
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register "icc_clock_disable" = "0x01220000"
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register "s0ix_enable" = "0"
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device domain 0 on
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device pci 13.0 on end # Smart Sound Audio DSP
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device pci 1b.0 off end # High Definition Audio
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device pci 1c.0 off end # PCIe Port #1
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device pci 1c.2 on end # PCIe Port #3 - LAN (becomes RP1)
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device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2)
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device pci 1f.3 on end # SMBus
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# chip soc/intel/broadwell/pch
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register "sata_devslp_disable" = "0x1"
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register "sio_i2c0_voltage" = "1" # 1.8V
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register "sio_i2c1_voltage" = "0" # 3.3V
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# DTLE DATA / EDGE values
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register "sata_port0_gen3_dtle" = "0x5"
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register "sata_port1_gen3_dtle" = "0x5"
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# Force enable ASPM for PCIe Port 5
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register "pcie_port_force_aspm" = "0x10"
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# Enable port coalescing
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register "pcie_port_coalesce" = "1"
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# Disable PCIe CLKOUT 1,5 and CLKOUT_XDP
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register "icc_clock_disable" = "0x01220000"
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device pci 13.0 on end # Smart Sound Audio DSP
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device pci 1b.0 off end # High Definition Audio
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device pci 1c.0 off end # PCIe Port #1
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device pci 1c.2 on end # PCIe Port #3 - LAN (becomes RP1)
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device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2)
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device pci 1f.3 on end # SMBus
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# end
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end
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end
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@ -7,9 +7,11 @@ chip soc/intel/broadwell
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register "gpu_panel_power_backlight_on_delay" = "500" # 50ms
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register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
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# DTLE DATA / EDGE values
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register "sata_port0_gen3_dtle" = "0x5"
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register "sata_port1_gen3_dtle" = "0x5"
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device domain 0 on end
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device domain 0 on
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# chip soc/intel/broadwell/pch
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# DTLE DATA / EDGE values
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register "sata_port0_gen3_dtle" = "0x5"
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register "sata_port1_gen3_dtle" = "0x5"
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# end
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end
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end
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@ -7,9 +7,11 @@ chip soc/intel/broadwell
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register "gpu_panel_power_backlight_on_delay" = "70" # 7ms
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register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
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# DTLE DATA / EDGE values
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register "sata_port0_gen3_dtle" = "0x5"
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register "sata_port1_gen3_dtle" = "0x5"
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device domain 0 on end
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device domain 0 on
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# chip soc/intel/broadwell/pch
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# DTLE DATA / EDGE values
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register "sata_port0_gen3_dtle" = "0x5"
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register "sata_port1_gen3_dtle" = "0x5"
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# end
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end
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end
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@ -10,30 +10,32 @@ chip soc/intel/broadwell
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register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms
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register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms
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register "sata_port0_gen3_tx" = "0x72"
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# Set I2C0 to 1.8V
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register "sio_i2c0_voltage" = "1"
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# Force enable ASPM for PCIe Port 3
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register "pcie_port_force_aspm" = "0x04"
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register "pcie_port_coalesce" = "1"
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# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
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register "icc_clock_disable" = "0x013b0000"
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register "vr_slow_ramp_rate_set" = "3"
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register "vr_slow_ramp_rate_enable" = "1"
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# Disable S0ix for now
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register "s0ix_enable" = "0"
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register "vr_slow_ramp_rate_set" = "3"
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register "vr_slow_ramp_rate_enable" = "1"
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device domain 0 on
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device pci 13.0 on end # Smart Sound Audio DSP
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device pci 15.3 on end # GSPI0
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device pci 1b.0 off end # High Definition Audio
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device pci 1c.0 off end # PCIe Port #1
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device pci 1c.2 on end # PCIe Port #3
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device pci 1d.0 off end # USB2 EHCI
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# chip soc/intel/broadwell/pch
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register "sata_port0_gen3_tx" = "0x72"
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# Set I2C0 to 1.8V
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register "sio_i2c0_voltage" = "1"
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# Force enable ASPM for PCIe Port 3
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register "pcie_port_force_aspm" = "0x04"
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register "pcie_port_coalesce" = "1"
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# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
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register "icc_clock_disable" = "0x013b0000"
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device pci 13.0 on end # Smart Sound Audio DSP
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device pci 15.3 on end # GSPI0
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device pci 1b.0 off end # High Definition Audio
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device pci 1c.0 off end # PCIe Port #1
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device pci 1c.2 on end # PCIe Port #3
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device pci 1d.0 off end # USB2 EHCI
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# end
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end
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end
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