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mb/google/auron: Prepare devicetree for PCH split

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Tested with BUILD_TIMELESS=1, all variants remain identical.

Change-Id: I2b088b36c8e9ff9cbd47d625b14fc45ebd96532a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46702
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-10-23 20:39:17 +02:00 committed by Patrick Georgi
parent ce19f4f8ad
commit 99af210456
7 changed files with 135 additions and 120 deletions
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115
src/mainboard/google/auron/devicetree.cb
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@ -15,27 +15,6 @@ chip soc/intel/broadwell
# Set backlight PWM value for eDP # Set backlight PWM value for eDP
register "gpu_pch_backlight_pwm_hz" = "200" register "gpu_pch_backlight_pwm_hz" = "200"
# EC range is 0x800-0x9ff
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x00fc0901"
# EC_SMI is GPIO34
register "alt_gp_smi_en" = "0x0004"
register "gpe0_en_1" = "0x00000000"
# EC_SCI is GPIO36
register "gpe0_en_2" = "0x00000010"
register "gpe0_en_3" = "0x00000000"
register "gpe0_en_4" = "0x00000000"
register "sata_port_map" = "0x1"
register "sio_acpi_mode" = "1"
# Force enable ASPM for PCIe Port1
register "pcie_port_force_aspm" = "0x01"
# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
register "icc_clock_disable" = "0x013c0000"
register "s0ix_enable" = "1" register "s0ix_enable" = "1"
device cpu_cluster 0 on device cpu_cluster 0 on
@ -46,40 +25,64 @@ chip soc/intel/broadwell
device pci 00.0 on end # host bridge device pci 00.0 on end # host bridge
device pci 02.0 on end # vga controller device pci 02.0 on end # vga controller
device pci 03.0 on end # mini-hd audio device pci 03.0 on end # mini-hd audio
device pci 13.0 off end # Smart Sound Audio DSP
device pci 14.0 on end # USB3 XHCI # chip soc/intel/broadwell/pch
device pci 15.0 on end # Serial I/O DMA # EC range is 0x800-0x9ff
device pci 15.1 on end # I2C0 register "gen1_dec" = "0x00fc0801"
device pci 15.2 on end # I2C1 register "gen2_dec" = "0x00fc0901"
device pci 15.3 off end # GSPI0
device pci 15.4 off end # GSPI1 # EC_SMI is GPIO34
device pci 15.5 off end # UART0 register "alt_gp_smi_en" = "0x0004"
device pci 15.6 off end # UART1 register "gpe0_en_1" = "0x00000000"
device pci 16.0 on end # Management Engine Interface 1 # EC_SCI is GPIO36
device pci 16.1 off end # Management Engine Interface 2 register "gpe0_en_2" = "0x00000010"
device pci 16.2 off end # Management Engine IDE-R register "gpe0_en_3" = "0x00000000"
device pci 16.3 off end # Management Engine KT register "gpe0_en_4" = "0x00000000"
device pci 17.0 off end # SDIO
device pci 19.0 off end # GbE register "sata_port_map" = "0x1"
device pci 1b.0 on end # High Definition Audio register "sio_acpi_mode" = "1"
device pci 1c.0 on end # PCIe Port #1
device pci 1c.1 off end # PCIe Port #2 # Force enable ASPM for PCIe Port1
device pci 1c.2 off end # PCIe Port #3 register "pcie_port_force_aspm" = "0x01"
device pci 1c.3 off end # PCIe Port #4
device pci 1c.4 off end # PCIe Port #5 # Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
device pci 1c.5 off end # PCIe Port #6 register "icc_clock_disable" = "0x013c0000"
device pci 1d.0 on end # USB2 EHCI
device pci 1e.0 off end # PCI bridge device pci 13.0 off end # Smart Sound Audio DSP
device pci 1f.0 on device pci 14.0 on end # USB3 XHCI
chip drivers/pc80/tpm device pci 15.0 on end # Serial I/O DMA
device pnp 0c31.0 on end device pci 15.1 on end # I2C0
end device pci 15.2 on end # I2C1
chip ec/google/chromeec device pci 15.3 off end # GSPI0
device pnp 0c09.0 on end device pci 15.4 off end # GSPI1
end device pci 15.5 off end # UART0
end # LPC bridge device pci 15.6 off end # UART1
device pci 1f.2 on end # SATA Controller device pci 16.0 on end # Management Engine Interface 1
device pci 1f.3 off end # SMBus device pci 16.1 off end # Management Engine Interface 2
device pci 1f.6 on end # Thermal device pci 16.2 off end # Management Engine IDE-R
device pci 16.3 off end # Management Engine KT
device pci 17.0 off end # SDIO
device pci 19.0 off end # GbE
device pci 1b.0 on end # High Definition Audio
device pci 1c.0 on end # PCIe Port #1
device pci 1c.1 off end # PCIe Port #2
device pci 1c.2 off end # PCIe Port #3
device pci 1c.3 off end # PCIe Port #4
device pci 1c.4 off end # PCIe Port #5
device pci 1c.5 off end # PCIe Port #6
device pci 1d.0 on end # USB2 EHCI
device pci 1e.0 off end # PCI bridge
device pci 1f.0 on
chip drivers/pc80/tpm
device pnp 0c31.0 on end
end
chip ec/google/chromeec
device pnp 0c09.0 on end
end
end # LPC bridge
device pci 1f.2 on end # SATA Controller
device pci 1f.3 off end # SMBus
device pci 1f.6 on end # Thermal
# end
end end
end end

12
src/mainboard/google/auron/variants/auron_paine/overridetree.cb
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@ -7,9 +7,11 @@ chip soc/intel/broadwell
register "gpu_panel_power_backlight_on_delay" = "70" # 7ms register "gpu_panel_power_backlight_on_delay" = "70" # 7ms
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
# DTLE DATA / EDGE values device domain 0 on
register "sata_port0_gen3_dtle" = "0x5" # chip soc/intel/broadwell/pch
register "sata_port1_gen3_dtle" = "0x5" # DTLE DATA / EDGE values
register "sata_port0_gen3_dtle" = "0x5"
device domain 0 on end register "sata_port1_gen3_dtle" = "0x5"
# end
end
end end

12
src/mainboard/google/auron/variants/auron_yuna/overridetree.cb
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@ -7,9 +7,11 @@ chip soc/intel/broadwell
register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
# DTLE DATA / EDGE values device domain 0 on
register "sata_port0_gen3_dtle" = "0x7" # chip soc/intel/broadwell/pch
register "sata_port1_gen3_dtle" = "0x5" # DTLE DATA / EDGE values
register "sata_port0_gen3_dtle" = "0x7"
device domain 0 on end register "sata_port1_gen3_dtle" = "0x5"
# end
end
end end

50
src/mainboard/google/auron/variants/buddy/overridetree.cb
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@ -7,32 +7,34 @@ chip soc/intel/broadwell
register "gpu_panel_power_backlight_on_delay" = "70" # 7ms register "gpu_panel_power_backlight_on_delay" = "70" # 7ms
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
register "sata_devslp_disable" = "0x1"
register "sio_i2c0_voltage" = "1" # 1.8V
register "sio_i2c1_voltage" = "0" # 3.3V
# DTLE DATA / EDGE values
register "sata_port0_gen3_dtle" = "0x5"
register "sata_port1_gen3_dtle" = "0x5"
# Force enable ASPM for PCIe Port 5
register "pcie_port_force_aspm" = "0x10"
# Enable port coalescing
register "pcie_port_coalesce" = "1"
# Disable PCIe CLKOUT 1,5 and CLKOUT_XDP
register "icc_clock_disable" = "0x01220000"
register "s0ix_enable" = "0" register "s0ix_enable" = "0"
device domain 0 on device domain 0 on
device pci 13.0 on end # Smart Sound Audio DSP # chip soc/intel/broadwell/pch
device pci 1b.0 off end # High Definition Audio register "sata_devslp_disable" = "0x1"
device pci 1c.0 off end # PCIe Port #1
device pci 1c.2 on end # PCIe Port #3 - LAN (becomes RP1) register "sio_i2c0_voltage" = "1" # 1.8V
device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2) register "sio_i2c1_voltage" = "0" # 3.3V
device pci 1f.3 on end # SMBus
# DTLE DATA / EDGE values
register "sata_port0_gen3_dtle" = "0x5"
register "sata_port1_gen3_dtle" = "0x5"
# Force enable ASPM for PCIe Port 5
register "pcie_port_force_aspm" = "0x10"
# Enable port coalescing
register "pcie_port_coalesce" = "1"
# Disable PCIe CLKOUT 1,5 and CLKOUT_XDP
register "icc_clock_disable" = "0x01220000"
device pci 13.0 on end # Smart Sound Audio DSP
device pci 1b.0 off end # High Definition Audio
device pci 1c.0 off end # PCIe Port #1
device pci 1c.2 on end # PCIe Port #3 - LAN (becomes RP1)
device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2)
device pci 1f.3 on end # SMBus
# end
end end
end end

12
src/mainboard/google/auron/variants/gandof/overridetree.cb
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@ -7,9 +7,11 @@ chip soc/intel/broadwell
register "gpu_panel_power_backlight_on_delay" = "500" # 50ms register "gpu_panel_power_backlight_on_delay" = "500" # 50ms
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
# DTLE DATA / EDGE values device domain 0 on
register "sata_port0_gen3_dtle" = "0x5" # chip soc/intel/broadwell/pch
register "sata_port1_gen3_dtle" = "0x5" # DTLE DATA / EDGE values
register "sata_port0_gen3_dtle" = "0x5"
device domain 0 on end register "sata_port1_gen3_dtle" = "0x5"
# end
end
end end

12
src/mainboard/google/auron/variants/lulu/overridetree.cb
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@ -7,9 +7,11 @@ chip soc/intel/broadwell
register "gpu_panel_power_backlight_on_delay" = "70" # 7ms register "gpu_panel_power_backlight_on_delay" = "70" # 7ms
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
# DTLE DATA / EDGE values device domain 0 on
register "sata_port0_gen3_dtle" = "0x5" # chip soc/intel/broadwell/pch
register "sata_port1_gen3_dtle" = "0x5" # DTLE DATA / EDGE values
register "sata_port0_gen3_dtle" = "0x5"
device domain 0 on end register "sata_port1_gen3_dtle" = "0x5"
# end
end
end end

42
src/mainboard/google/auron/variants/samus/overridetree.cb
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@ -10,30 +10,32 @@ chip soc/intel/broadwell
register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms
register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms
register "sata_port0_gen3_tx" = "0x72" register "vr_slow_ramp_rate_set" = "3"
register "vr_slow_ramp_rate_enable" = "1"
# Set I2C0 to 1.8V
register "sio_i2c0_voltage" = "1"
# Force enable ASPM for PCIe Port 3
register "pcie_port_force_aspm" = "0x04"
register "pcie_port_coalesce" = "1"
# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
register "icc_clock_disable" = "0x013b0000"
# Disable S0ix for now # Disable S0ix for now
register "s0ix_enable" = "0" register "s0ix_enable" = "0"
register "vr_slow_ramp_rate_set" = "3"
register "vr_slow_ramp_rate_enable" = "1"
device domain 0 on device domain 0 on
device pci 13.0 on end # Smart Sound Audio DSP # chip soc/intel/broadwell/pch
device pci 15.3 on end # GSPI0 register "sata_port0_gen3_tx" = "0x72"
device pci 1b.0 off end # High Definition Audio
device pci 1c.0 off end # PCIe Port #1 # Set I2C0 to 1.8V
device pci 1c.2 on end # PCIe Port #3 register "sio_i2c0_voltage" = "1"
device pci 1d.0 off end # USB2 EHCI
# Force enable ASPM for PCIe Port 3
register "pcie_port_force_aspm" = "0x04"
register "pcie_port_coalesce" = "1"
# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
register "icc_clock_disable" = "0x013b0000"
device pci 13.0 on end # Smart Sound Audio DSP
device pci 15.3 on end # GSPI0
device pci 1b.0 off end # High Definition Audio
device pci 1c.0 off end # PCIe Port #1
device pci 1c.2 on end # PCIe Port #3
device pci 1d.0 off end # USB2 EHCI
# end
end end
end end