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mb/google/auron: Prepare devicetree for PCH split

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Tested with BUILD_TIMELESS=1, all variants remain identical.

Change-Id: I2b088b36c8e9ff9cbd47d625b14fc45ebd96532a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46702
Reviewed-by: Nico Huber <nico.h@gmx.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-10-23 20:39:17 +02:00 committed by Patrick Georgi
parent ce19f4f8ad
commit 99af210456
7 changed files with 135 additions and 120 deletions
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23
src/mainboard/google/auron/devicetree.cb
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@ -15,6 +15,18 @@ chip soc/intel/broadwell
# Set backlight PWM value for eDP
register "gpu_pch_backlight_pwm_hz" = "200"
register "s0ix_enable" = "1"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # host bridge
device pci 02.0 on end # vga controller
device pci 03.0 on end # mini-hd audio
# chip soc/intel/broadwell/pch
# EC range is 0x800-0x9ff
register "gen1_dec" = "0x00fc0801"
register "gen2_dec" = "0x00fc0901"
@ -36,16 +48,6 @@ chip soc/intel/broadwell
# Disable PCIe CLKOUT 2-5 and CLKOUT_XDP
register "icc_clock_disable" = "0x013c0000"
register "s0ix_enable" = "1"
device cpu_cluster 0 on
device lapic 0 on end
end
device domain 0 on
device pci 00.0 on end # host bridge
device pci 02.0 on end # vga controller
device pci 03.0 on end # mini-hd audio
device pci 13.0 off end # Smart Sound Audio DSP
device pci 14.0 on end # USB3 XHCI
device pci 15.0 on end # Serial I/O DMA
@ -81,5 +83,6 @@ chip soc/intel/broadwell
device pci 1f.2 on end # SATA Controller
device pci 1f.3 off end # SMBus
device pci 1f.6 on end # Thermal
# end
end
end

6
src/mainboard/google/auron/variants/auron_paine/overridetree.cb
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@ -7,9 +7,11 @@ chip soc/intel/broadwell
register "gpu_panel_power_backlight_on_delay" = "70" # 7ms
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
device domain 0 on
# chip soc/intel/broadwell/pch
# DTLE DATA / EDGE values
register "sata_port0_gen3_dtle" = "0x5"
register "sata_port1_gen3_dtle" = "0x5"
device domain 0 on end
# end
end
end

6
src/mainboard/google/auron/variants/auron_yuna/overridetree.cb
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@ -7,9 +7,11 @@ chip soc/intel/broadwell
register "gpu_panel_power_backlight_on_delay" = "2100" # 210ms
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
device domain 0 on
# chip soc/intel/broadwell/pch
# DTLE DATA / EDGE values
register "sata_port0_gen3_dtle" = "0x7"
register "sata_port1_gen3_dtle" = "0x5"
device domain 0 on end
# end
end
end

8
src/mainboard/google/auron/variants/buddy/overridetree.cb
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@ -7,6 +7,10 @@ chip soc/intel/broadwell
register "gpu_panel_power_backlight_on_delay" = "70" # 7ms
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
register "s0ix_enable" = "0"
device domain 0 on
# chip soc/intel/broadwell/pch
register "sata_devslp_disable" = "0x1"
register "sio_i2c0_voltage" = "1" # 1.8V
@ -25,14 +29,12 @@ chip soc/intel/broadwell
# Disable PCIe CLKOUT 1,5 and CLKOUT_XDP
register "icc_clock_disable" = "0x01220000"
register "s0ix_enable" = "0"
device domain 0 on
device pci 13.0 on end # Smart Sound Audio DSP
device pci 1b.0 off end # High Definition Audio
device pci 1c.0 off end # PCIe Port #1
device pci 1c.2 on end # PCIe Port #3 - LAN (becomes RP1)
device pci 1c.3 on end # PCIe Port #4 - WLAN (becomes RP2)
device pci 1f.3 on end # SMBus
# end
end
end

6
src/mainboard/google/auron/variants/gandof/overridetree.cb
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@ -7,9 +7,11 @@ chip soc/intel/broadwell
register "gpu_panel_power_backlight_on_delay" = "500" # 50ms
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
device domain 0 on
# chip soc/intel/broadwell/pch
# DTLE DATA / EDGE values
register "sata_port0_gen3_dtle" = "0x5"
register "sata_port1_gen3_dtle" = "0x5"
device domain 0 on end
# end
end
end

6
src/mainboard/google/auron/variants/lulu/overridetree.cb
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@ -7,9 +7,11 @@ chip soc/intel/broadwell
register "gpu_panel_power_backlight_on_delay" = "70" # 7ms
register "gpu_panel_power_backlight_off_delay" = "2100" # 210ms
device domain 0 on
# chip soc/intel/broadwell/pch
# DTLE DATA / EDGE values
register "sata_port0_gen3_dtle" = "0x5"
register "sata_port1_gen3_dtle" = "0x5"
device domain 0 on end
# end
end
end

16
src/mainboard/google/auron/variants/samus/overridetree.cb
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@ -10,6 +10,14 @@ chip soc/intel/broadwell
register "gpu_panel_power_backlight_on_delay" = "2000" # 200ms
register "gpu_panel_power_backlight_off_delay" = "2000" # 200ms
register "vr_slow_ramp_rate_set" = "3"
register "vr_slow_ramp_rate_enable" = "1"
# Disable S0ix for now
register "s0ix_enable" = "0"
device domain 0 on
# chip soc/intel/broadwell/pch
register "sata_port0_gen3_tx" = "0x72"
# Set I2C0 to 1.8V
@ -22,18 +30,12 @@ chip soc/intel/broadwell
# Disable PCIe CLKOUT 1-5 and CLKOUT_XDP
register "icc_clock_disable" = "0x013b0000"
# Disable S0ix for now
register "s0ix_enable" = "0"
register "vr_slow_ramp_rate_set" = "3"
register "vr_slow_ramp_rate_enable" = "1"
device domain 0 on
device pci 13.0 on end # Smart Sound Audio DSP
device pci 15.3 on end # GSPI0
device pci 1b.0 off end # High Definition Audio
device pci 1c.0 off end # PCIe Port #1
device pci 1c.2 on end # PCIe Port #3
device pci 1d.0 off end # USB2 EHCI
# end
end
end