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AMD GX2 boards & chips: Remove - using LATE_CBMEM_INIT

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All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.

If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.

chips:
cpu/amd/geode_gx2
northbridge/amd/gx2
southbridge/amd/cs5535

Mainboards:
mainboard/amd/rumba
mainboard/lippert/frontrunner
mainboard/wyse/s50

Change-Id: I81c130f53bbfa001edbfdb7a878ef115757f620c
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22025
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Martin Roth
2017-10-15 14:16:37 -06:00
committed by Martin Roth
parent b94b2c7306
commit 99c45dee0a
52 changed files with 0 additions and 4564 deletions
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1
src/cpu/amd/Kconfig
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@@ -14,7 +14,6 @@ source src/cpu/amd/socket_S1G1/Kconfig
source src/cpu/amd/model_fxx/Kconfig
source src/cpu/amd/family_10h-family_15h/Kconfig
source src/cpu/amd/geode_gx2/Kconfig
source src/cpu/amd/geode_lx/Kconfig
source src/cpu/amd/agesa/Kconfig

1
src/cpu/amd/Makefile.inc
View File

@@ -10,7 +10,6 @@ subdirs-$(CONFIG_CPU_AMD_SOCKET_ASB2) += socket_ASB2
subdirs-$(CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA) += socket_C32
subdirs-$(CONFIG_CPU_AMD_SOCKET_FM2_NON_AGESA) += socket_FM2
subdirs-$(CONFIG_CPU_AMD_SOCKET_G34_NON_AGESA) += socket_G34
subdirs-$(CONFIG_CPU_AMD_GEODE_GX2) += geode_gx2
subdirs-$(CONFIG_CPU_AMD_GEODE_LX) += geode_lx
subdirs-$(CONFIG_CPU_AMD_SOCKET_S1G1) += socket_S1G1

69
src/cpu/amd/geode_gx2/Kconfig
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@@ -1,69 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2010 coresystems GmbH
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config CPU_AMD_GEODE_GX2
bool
select ARCH_BOOTBLOCK_X86_32
select ARCH_VERSTAGE_X86_32
select ARCH_ROMSTAGE_X86_32
select ARCH_RAMSTAGE_X86_32
if CPU_AMD_GEODE_GX2
config CPU_SPECIFIC_OPTIONS
def_bool y
select NO_MMCONF_SUPPORT
config DCACHE_RAM_BASE
hex
default 0xc8000
config DCACHE_RAM_SIZE
hex
default 0x04000
config DCACHE_BSP_STACK_SIZE
hex
default 0x1000
config DCACHE_BSP_STACK_SLUSH
hex
default 0x1000
config DCACHE_AP_STACK_SIZE
hex
default 0x400
config GEODE_VSA
bool
default y
config GEODE_VSA_FILE
bool "Add a VSA image"
help
Select this option if you have an AMD Geode GX2 vsa that you would
like to add to your ROM.
You will be able to specify the location and file name of the
image later.
config VSA_FILENAME
string "AMD Geode GX2 VSA path and filename"
depends on GEODE_VSA_FILE
default "gpl_vsa_gx_102.bin"
help
The path and filename of the file to use as VSA.
endif # CPU_AMD_GEODE_GX2

14
src/cpu/amd/geode_gx2/Makefile.inc
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@@ -1,14 +0,0 @@
subdirs-y += ../../x86/tsc
subdirs-y += ../../x86/lapic
subdirs-y += ../../x86/cache
subdirs-y += ../../x86/smm
ramstage-y += geode_gx2_init.c
ramstage-y += cpubug.c
cpu_incs-y += $(src)/cpu/amd/geode_gx2/cache_as_ram.inc
cbfs-files-$(CONFIG_GEODE_VSA_FILE) += vsa
vsa-file = $(call strip_quotes,$(CONFIG_VSA_FILENAME)):vsa
vsa-type = stage
vsa-required = VSA binary (binary and MASM source code available in coreboot/3rdparty/blobs repository)

198
src/cpu/amd/geode_gx2/cache_as_ram.inc
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@@ -1,198 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
* Copyright (C) 2010 Nils Jacobs
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#define GX2_STACK_BASE CONFIG_DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as coreboot normal stack */
#define GX2_STACK_END GX2_STACK_BASE+(CONFIG_DCACHE_RAM_SIZE-1)
#define GX2_NUM_CACHELINES 0x080 /* there are 128lines per way */
#define GX2_CACHELINE_SIZE 0x020 /* there are 32bytes per line */
#define GX2_CACHEWAY_SIZE (GX2_NUM_CACHELINES * GX2_CACHELINE_SIZE)
#define CR0_CD 0x40000000 /* bit 30 = Cache Disable */
#define CR0_NW 0x20000000 /* bit 29 = Not Write Through */
#include <cpu/amd/gx2def.h>
#include <cpu/x86/post_code.h>
/*
* DCacheSetup
*
* Setup data cache for use as RAM for a stack.
*
* Max. size data cache =0x4000 (16KB)
*/
DCacheSetup:
/* Save the BIST result */
movl %eax, %ebx
invd
/* set cache properties */
movl $CPU_RCONF_DEFAULT, %ecx
rdmsr
movl $0x010010000, %eax /*1MB system memory in write back 1|00100|00 */
wrmsr
/* in GX2 DCDIS is set after POR which disables the cache..., clear this bit */
movl $CPU_DM_CONFIG0, %ecx
rdmsr
andl $(~(DM_CONFIG0_LOWER_DCDIS_SET)), %eax /* TODO: make consistent with i$ init, either whole reg = 0, or just this bit... */
wrmsr
/* Get cleaned up. */
xorl %edi, %edi
xorl %esi, %esi
xorl %ebp, %ebp
/* DCache Ways0 through Ways3 will be tagged for GX2_STACK_BASE + CONFIG_DCACHE_RAM_SIZE for holding stack */
/* remember, there is NO stack yet... */
/* Tell cache we want to fill WAY 0 starting at the top */
xorl %edx, %edx
xorl %eax, %eax
movl $CPU_DC_INDEX, %ecx
wrmsr
/* startaddress for tag of Way0: ebp will hold the incrementing address. dont destroy! */
movl $GX2_STACK_BASE, %ebp /* init to start address */
orl $1, %ebp /* set valid bit and tag for this Way (B[31:12] : Cache tag value for line/way curr. selected by CPU_DC_INDEX */
/* start tag Ways 0 with 128 lines with 32bytes each: edi will hold the line counter. dont destroy! */
movl $GX2_NUM_CACHELINES, %edi
DCacheSetupFillWay:
/* fill with dummy data: zero it so we can tell it from PCI memory space (returns FFs). */
/* We will now store a line (32 bytes = 4 x 8bytes = 4 quadWords) */
movw $0x04, %si
xorl %edx, %edx
xorl %eax, %eax
movl $CPU_DC_DATA, %ecx
DCacheSetup_quadWordLoop:
wrmsr
decw %si
jnz DCacheSetup_quadWordLoop
/* Set the tag for this line,need to do this for every new cache line to validate it! */
/* accessing CPU_DC_TAG_I makes the LINE field in CPU_DC_INDEX increment and thus cont. in the next cache line... */
xorl %edx, %edx
movl %ebp, %eax
movl $CPU_DC_TAG, %ecx
wrmsr
/* switch to next line */
/* lines are in Bits8:2 */
/* when index is crossing 0x7F -> 0x80 writing a RSVD bit as 0x80 is not a valid CL anymore! */
movl $CPU_DC_INDEX, %ecx
rdmsr
addl $0x04, %eax /* inc DC_LINE. TODO: prob. would be more elegant to calc. this from counter var edi... */
wrmsr
decl %edi
jnz DCacheSetupFillWay
/* 1 Way has been filled, forward start address for next Way, terminate if we have reached end of desired address range */
addl $GX2_CACHEWAY_SIZE, %ebp
cmpl $GX2_STACK_END, %ebp
jge leave_DCacheSetup
movl $GX2_NUM_CACHELINES, %edi
/* switch to next way */
movl $CPU_DC_INDEX, %ecx
rdmsr
addl $0x01, %eax
andl $0xFFFFFE03, %eax /* lets be sure: reset line index Bits8:2 */
wrmsr
jmp DCacheSetupFillWay
leave_DCacheSetup:
xorl %edi, %edi
xorl %esi, %esi
xorl %ebp, %ebp
/* Disable the cache, but ... DO NOT INVALIDATE the tags. */
/* Memory reads and writes will all hit in the cache. */
/* Cache updates and memory write-backs will not occur ! */
movl %cr0, %eax
orl $(CR0_CD + CR0_NW), %eax /* set the CD and NW bits */
movl %eax, %cr0
/* Now point sp to the cached stack. */
/* The stack will be fully functional at this location. No system memory is required at all ! */
/* set up the stack pointer */
movl $GX2_STACK_END, %eax
movl %eax, %esp
/* test the stack*/
movl $0x0F0F05A5A, %edx
pushl %edx
popl %ecx
cmpl %ecx, %edx
je DCacheSetupGood
post_code(0xc5)
DCacheSetupBad:
hlt /* issues */
jmp DCacheSetupBad
DCacheSetupGood:
/* Go do early init and memory setup */
/* Restore the BIST result */
movl %ebx, %eax
movl %esp, %ebp
pushl %eax
post_code(0x23)
/* Call romstage.c main function */
call mainboard_romstage_entry
done_cache_as_ram_main:
/* We now run over the stack-in-cache, copying it back to itself to invalidate the cache */
push %edi
mov $(CONFIG_DCACHE_RAM_SIZE >> 2),%ecx
push %esi
mov $(CONFIG_DCACHE_RAM_BASE),%edi
mov %edi,%esi
cld
rep movsl %ds:(%esi),%es:(%edi)
pop %esi
pop %edi
/* Clear the cache out to RAM */
wbinvd
/* re-enable the cache */
movl %cr0, %eax
xorl $(CR0_CD + CR0_NW), %eax /* clear the CD and NW bits */
movl %eax, %cr0
__main:
post_code(POST_PREPARE_RAMSTAGE)
/* TODO For suspend/resume low memory needs backup store. */
cld /* clear direction flag */
/* copy coreboot from it's initial load location to
* the location it is compiled to run at.
* Normally this is copying from FLASH ROM to RAM.
*/
call copy_and_run
.Lhlt:
post_code(POST_DEAD_CODE)
hlt
jmp .Lhlt

359
src/cpu/amd/geode_gx2/cpubug.c
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@@ -1,359 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <arch/io.h>
#include <stdint.h>
#include <device/device.h>
#include <stdlib.h>
#include <string.h>
#include <cpu/amd/gx2def.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/cache.h>
#if 0
void bug645(void)
{
msr_t msr;
rdmsr(CPU_ID_CONFIG);
msr.whatever |= ID_CONFIG_SERIAL_SET;
wrmsr(msr);
}
void bug573(void)
{
msr_t msr;
msr = rdmsr(MC_GLD_MSR_PM);
msr.eax &= 0xfff3;
wrmsr(MC_GLD_MSR_PM);
}
#endif
/* pcideadlock
*
* Bugtool #465 and #609
* PCI cache deadlock
* There is also fix code in cache and PCI functions. This bug is very is pervasive.
*/
static void pcideadlock(void)
{
msr_t msr;
/* forces serialization of all load misses. Setting this bit prevents the
* DM pipe from backing up if a read request has to be held up waiting
* for PCI writes to complete.
*/
msr = rdmsr(CPU_DM_CONFIG0);
msr.hi &= ~(7 << DM_CONFIG0_UPPER_WSREQ_SHIFT);
msr.hi |= (2 << DM_CONFIG0_UPPER_WSREQ_SHIFT);
msr.lo |= DM_CONFIG0_LOWER_MISSER_SET;
wrmsr(CPU_DM_CONFIG0, msr);
/* interlock instruction fetches to WS regions with data accesses.
* This prevents an instruction fetch from going out to PCI if the
* data side is about to make a request.
*/
msr = rdmsr(CPU_IM_CONFIG);
msr.lo |= IM_CONFIG_LOWER_QWT_SET;
wrmsr(CPU_IM_CONFIG, msr);
/* write serialize memory hole to PCI. Need to unWS when something is
* shadowed regardless of cachablility.
*/
msr.lo = 0x021212121;
msr.hi = 0x021212121;
wrmsr( CPU_RCONF_A0_BF, msr);
wrmsr( CPU_RCONF_C0_DF, msr);
wrmsr( CPU_RCONF_E0_FF, msr);
}
/* CPUbug784
*
* Bugtool #784 + #792
*
* Fix CPUID instructions for < 3.0 CPUs
*/
static void bug784(void)
{
msr_t msr;
//static char *name = "Geode by NSC";
/* we'll do this the stupid way, for now, but that's the string they want. NO ONE KNOWS why you
* would do this -- the OS can figure this type of stuff out!
*/
msr = rdmsr(0x3006);
msr.hi = 0x646f6547;
wrmsr(0x3006, msr);
msr = rdmsr(0x3007);
msr.hi = 0x79622065;
msr.lo = 0x43534e20;
wrmsr(0x3007, msr);
msr = rdmsr(0x3002);
wrmsr(0x3008, msr);
/* More CPUID to match AMD better. #792*/
msr = rdmsr(0x3009);
msr.hi = 0x0C0C0A13D;
msr.lo = 0x00000000;
wrmsr(0x3009, msr);
}
/* cpubug 1398: enable MC if we KNOW we have DDR*/
/* CPUbugIAENG1398
*
* ClearQuest #IAENG1398
* The MC can not be enabled with SDR memory but can for DDR. Enable for
* DDR here if the setup token is "Default"
* Add this back to core by default once 2.0 CPUs are not supported.
*/
static void eng1398(void)
{
msr_t msr;
msr = rdmsr(MSR_GLCP+0x17);
if ((msr.lo & 0xff) <= CPU_REV_2_0) {
msr = rdmsr(GLCP_SYS_RSTPLL);
if (msr.lo & (1 << RSTPPL_LOWER_SDRMODE_SHIFT))
return;
}
/* no CMOS/NVRAM to check, so enable MC Clock Gating */
msr = rdmsr(MC_GLD_MSR_PM);
msr.lo |= 3; /* enable MC clock gating.*/
wrmsr(MC_GLD_MSR_PM, msr);
}
/* CPUbugIAENG2900
*
* Clear Quest IAENG00002900, VSS 118.150
*
* BTB issue causes blue screen in windows, but the fix is required
* for all operating systems.
*/
static void eng2900(void)
{
msr_t msr;
printk(BIOS_DEBUG, "CPU_BUG:%s\n", __func__);
/* Clear bit 43, disables the sysenter/sysexit in CPUID3 */
msr = rdmsr(0x3003);
msr.hi &= 0xFFFFF7FF;
wrmsr(0x3003, msr);
/* change this value to zero if you need to disable this BTB SWAPSiF. */
if (1) {
/* Disable enable_actions in DIAGCTL while setting up GLCP */
msr.hi = 0;
msr.lo = 0;
wrmsr(MSR_GLCP + 0x005f, msr);
/* Changing DBGCLKCTL register to GeodeLink */
msr.hi = 0;
msr.lo = 0;
wrmsr(MSR_GLCP + 0x0016, msr);
msr.hi = 0;
msr.lo = 2;
wrmsr(MSR_GLCP + 0x0016, msr);
/* The code below sets up the CPU to stall for 4 GeodeLink
* clocks when CPU is snooped. Because setting XSTATE to 0
* overrides any other XSTATE action, the code will always
* stall for 4 GeodeLink clocks after a snoop request goes
* away even if it occurred a clock or two later than a
* different snoop; the stall signal will never 'glitch high'
* for only one or two CPU clocks with this code.
*/
/* Send mb0 port 3 requests to upper GeodeLink diag bits
[63:32] */
msr.hi = 0;
msr.lo = 0x80338041;
wrmsr(MSR_GLIU0 + 0x2005, msr);
/* set5m watches request ready from mb0 to CPU (snoop) */
msr.hi = 0x5ad68000;
msr.lo = 0;
wrmsr(MSR_GLCP + 0x0045, msr);
/* SET4M will be high when state is idle (XSTATE=11) */
msr.hi = 0;
msr.lo = 0x0140;
wrmsr(MSR_GLCP + 0x0044, msr);
/* SET5n to watch for processor stalled state */
msr.hi = 0x2000;
msr.lo = 0;
wrmsr(MSR_GLCP + 0x004D, msr);
/* Writing action number 13: XSTATE=0 to occur when CPU is
snooped unless we're stalled */
msr.hi = 0;
msr.lo = 0x00400000;
wrmsr(MSR_GLCP + 0x0075, msr);
/* Writing action number 11: inc XSTATE every GeodeLink clock
unless we're idle */
msr.hi = 0;
msr.lo = 0x30000;
wrmsr(MSR_GLCP + 0x0073, msr);
/* Writing action number 5: STALL_CPU_PIPE when exiting idle
state or not in idle state */
msr.hi = 0;
msr.lo = 0x00430000;
wrmsr(MSR_GLCP + 0x006D, msr);
/* Writing DIAGCTL Register to enable the stall action and to
let set5m watch the upper GeodeLink diag bits. */
msr.hi = 0;
msr.lo = 0x80004000;
wrmsr(MSR_GLCP + 0x005f, msr);
}
}
static void bug118253(void)
{
/* GLPCI PIO Post Control shouldn't be enabled */
msr_t msr;
msr = rdmsr(GLPCI_SPARE);
msr.lo &= ~GLPCI_SPARE_LOWER_PPC_SET;
wrmsr(GLPCI_SPARE, msr);
}
static void bug118339(void)
{
/* per AMD, do this always */
msr_t msr = {0,0};
int msrnum;
/* Disable enable_actions in DIAGCTL while setting up GLCP */
wrmsr(MSR_GLCP + 0x005f, msr);
/* SET2M fires if VG pri is odd (3, not 2) and Ystate=0 */
msrnum = MSR_GLCP + 0x042;
/* msr.hi = 2d6b8000h; */
msr.hi = 0x596b8000;
msr.lo = 0x00000a00;
wrmsr(msrnum, msr);
/* SET3M fires if MBUS changed and VG pri is odd */
msrnum = MSR_GLCP + 0x043;
msr.hi = 0x596b8040;
msr.lo = 0;
wrmsr(msrnum, msr);
/* Put VG request data on lower diag bus */
msrnum = MSR_GLIU0 + 0x2005;
msr.hi = 0;
msr.lo = 0x80338041;
wrmsr(msrnum, msr);
/* Increment Y state if SET3M if true */
msrnum = MSR_GLCP + 0x074;
msr.hi = 0;
msr.lo = 0x0000c000;
wrmsr(msrnum, msr);
/* Set up MBUS action to PRI=3 read of MBIU */
msrnum = MSR_GLCP + 0x020;
msr.hi = 0x0000d863;
msr.lo = 0x20002000;
wrmsr(msrnum, msr);
/* Trigger MBUS action if VG=pri3 and Y=0, this blocks most PCI */
msrnum = MSR_GLCP + 0x071;
msr.hi = 0;
msr.lo = 0x00000c00;
wrmsr(msrnum, msr);
/* Writing DIAGCTL */
msrnum = MSR_GLCP + 0x005f;
msr.hi = 0;
msr.lo = 0x80004000;
wrmsr(msrnum, msr);
/* Code to enable FS2 even when BTB and VGTEAR SWAPSiFs are enabled
* As per Todd Roberts in PBz1094 and PBz1095
* Moved from CPUREG to CPUBUG per Tom Sylla
*/
msrnum = 0x04C000042; /* GLCP SETMCTL Register */
msr = rdmsr(msrnum);
msr.hi |= 8; /* Bit 35 = MCP_IN */
wrmsr(msrnum, msr);
}
/* DisableMemoryReorder
*
* PBZ 3659:
* The MC reordered transactions incorrectly and breaks coherency.
* Disable reordering and take a potential performance hit.
* This is safe to do here and not in MC init since there is nothing
* to maintain coherency with and the cache is not enabled yet.
*/
static void disablememoryreadorder(void)
{
msr_t msr;
msr = rdmsr(MC_CF8F_DATA);
msr.hi |= CF8F_UPPER_REORDER_DIS_SET;
wrmsr(MC_CF8F_DATA, msr);
}
void cpubug(void)
{
msr_t msr;
int rev;
msr = rdmsr(GLCP_CHIP_REVID);
rev = msr.lo & 0xff;
if (rev < 0x20) {
printk(BIOS_ERR, "%s: rev < 0x20! bailing!\n", __func__);
return;
}
printk(BIOS_DEBUG, "Doing cpubug fixes for rev 0x%x\n", rev);
switch(rev)
{
case 0x20:
pcideadlock();
eng1398();
/* cs 5530 bug; ignore
bug752();
*/
break;
case 0x21:
pcideadlock();
eng1398();
eng2900();
bug118339();
break;
case 0x22:
case 0x30:
break;
default:
printk(BIOS_ERR, "unknown rev %x, bailing\n", rev);
return;
}
bug784();
bug118253();
disablememoryreadorder();
printk(BIOS_DEBUG, "Done cpubug fixes\n");
}

142
src/cpu/amd/geode_gx2/cpureginit.c
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@@ -1,142 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* cpuRegInit */
void cpuRegInit (void)
{
int msrnum;
msr_t msr;
/* The following is only for diagnostics mode; do not use for OLPC */
if (0) {
/* Set Diagnostic Mode */
msrnum = CPU_GLD_MSR_DIAG;
msr.hi = 0;
msr.lo = DIAG_SEL1_SET | DIAG_SET0_SET;
wrmsr(msrnum, msr);
/* Set up GLCP to grab BTM data. */
msrnum = GLCP_DBGOUT; /* GLCP_DBGOUT MSR */
msr.hi = 0x0;
msr.lo = 0x08; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out, */
wrmsr(msrnum, msr); /* exchange it to anything else to prevent this */
/* Turn off debug clock */
msrnum = GLCP_DBGCLKCTL; /* DBG_CLK_CTL */
msr.lo = 0x00; /* No clock */
msr.hi = 0x00;
wrmsr(msrnum, msr);
/* Set debug clock to CPU */
msrnum = GLCP_DBGCLKCTL; /* DBG_CLK_CTL */
msr.lo = 0x01; /* CPU CLOCK */
msr.hi = 0x00;
wrmsr(msrnum, msr);
/* Set fifo ctl to BTM bits wide */
msrnum = GLCP_FIFOCTL; /* FIFO_CTL */
msr.lo = 0x003880000; /* Bit [25:24] are size (11=BTM, 10 = 64 bit, 01= 32 bit, 00 = 16bit) */
wrmsr(msrnum, msr); /* Bit [23:21] are position (100 = CPU downto0) */
/* Bit [19] sets it up in slow data mode. */
/* enable fifo loading - BTM sizing will constrain */
/* only valid BTM packets to load - this action should always be on */
msrnum = 0x04C00006F; /* GLCP ACTION7 - load fifo */
msr.lo = 0x00000F000; /* Any nibble all 1's will always trigger */
msr.hi = 0x000000000;
wrmsr(msrnum, msr);
/* start storing diag data in the fifo */
msrnum = 0x04C00005F; /* DIAG CTL */
msr.lo = 0x080000000; /* enable actions */
msr.hi = 0x000000000;
wrmsr(msrnum, msr);
/* Set up delay on data lines, so that the hold time */
/* is 1 ns. */
msrnum = GLCP_PROCSTAT; /* GLCP IO DELAY CONTROLS */
msr.lo = 0x082b5ad68;
msr.hi = 0x080ad6b57; /* RGB delay = 0x07 */
wrmsr(msrnum, msr);
/* Set up DF to output diag information on DF pins. */
msrnum = DF_GLD_MSR_MASTER_CONF;
msr.lo = 0x0220;
msr.hi = 0;
wrmsr(msrnum, msr);
msrnum = GLCP_DBGOUT; /* GLCP_DBGOUT MSR */
msr.hi = 0x0;
msr.lo = 0x0; /* reset value (SCOPE_SEL = 0) causes FIFO to shift out, */
wrmsr(msrnum, msr);
/* end of code for BTM */
}
/* Enable Suspend on Halt */
msrnum = CPU_XC_CONFIG;
msr = rdmsr(msrnum);
msr.lo |= XC_CONFIG_SUSP_ON_HLT;
wrmsr(msrnum, msr);
/* ENable SUSP and allow TSC to run in Suspend */
/* to keep speed detection happy */
msrnum = CPU_BC_CONF_0;
msr = rdmsr(msrnum);
msr.lo |= TSC_SUSP_SET | SUSP_EN_SET;
wrmsr(msrnum, msr);
/* Setup throttling to proper mode if it is ever enabled. */
msrnum = GLCP_TH_OD;
msr.hi = 0x000000000;
msr.lo = 0x00000603C;
wrmsr(msrnum, msr);
/* FooGlue Setup */
/* Set CS5535/CS5536 mode in FooGlue */
msrnum = FG_GIO_MSR_SEL;
msr = rdmsr(msrnum);
msr.lo &= ~3;
msr.lo |= 2; /* IIOC mode CS5535/CS5536 enable. (according to Jordan Crouse the databook is wrong bits 1:0 have to be 2 instead of 1) */
wrmsr(msrnum, msr);
/* Disable DOT PLL. Graphics init will enable it if needed. */
msrnum = GLCP_DOTPLL;
msr = rdmsr(msrnum);
msr.lo |= DOTPPL_LOWER_PD_SET;
wrmsr(msrnum, msr);
/* Enable RSDC */
msrnum = CPU_AC_SMM_CTL;
msr = rdmsr(msrnum);
msr.lo |= 0x08;
wrmsr(msrnum, msr);
/* Enable BTB */
/* I hate to put this check here but it doesn't really work in cpubug.asm */
msrnum = GLCP_CHIP_REVID;
msr = rdmsr(msrnum);
if (msr.lo >= CPU_REV_2_1){
msrnum = CPU_PF_BTB_CONF;
msr = rdmsr(msrnum);
msr.lo |= BTB_ENABLE_SET | RETURN_STACK_ENABLE_SET;
wrmsr(msrnum, msr);
}
/* FPU imprecise exceptions bit */
{
msrnum = CPU_FPU_MSR_MODE;
msr = rdmsr(msrnum);
msr.lo |= FPU_IE_SET;
wrmsr(msrnum, msr);
}
}

58
src/cpu/amd/geode_gx2/geode_gx2_init.c
View File

@@ -1,58 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <device/device.h>
#include <string.h>
#include <cpu/cpu.h>
#include <cpu/x86/lapic.h>
#include <cpu/x86/cache.h>
static void vsm_end_post_smi(void)
{
__asm__ volatile (
"push %ax\n"
"mov $0x5000, %ax\n"
".byte 0x0f, 0x38\n"
"pop %ax\n"
);
}
static void geode_gx2_init(device_t dev)
{
printk(BIOS_DEBUG, "geode_gx2_init\n");
/* Turn on caching if we haven't already */
x86_enable_cache();
/* Enable the local CPU APICs */
//setup_lapic();
vsm_end_post_smi();
printk(BIOS_DEBUG, "geode_gx2_init DONE\n");
};
static struct device_operations cpu_dev_ops = {
.init = geode_gx2_init,
};
static const struct cpu_device_id cpu_table[] = {
{ X86_VENDOR_NSC, 0x0552 },
{ 0, 0 },
};
static const struct cpu_driver driver __cpu_driver = {
.ops = &cpu_dev_ops,
.id_table = cpu_table,
};

33
src/cpu/amd/geode_gx2/syspreinit.c
View File

@@ -1,33 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/* StartTimer1
*
* Entry: none
* Exit: Starts Timer 1 for port 61 use
* Destroys: Al,
*/
static void StartTimer1(void)
{
outb(0x56, 0x43);
outb(0x12, 0x41);
}
void SystemPreInit(void)
{
/* they want a jump ... */
#if !IS_ENABLED(CONFIG_CACHE_AS_RAM)
__asm__ __volatile__("jmp .+2\ninvd\njmp .+2\n");
#endif
StartTimer1();
}

41
src/mainboard/amd/rumba/Kconfig
View File

@@ -1,41 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
if BOARD_AMD_RUMBA
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_AMD_GEODE_GX2
select NORTHBRIDGE_AMD_GX2
select SOUTHBRIDGE_AMD_CS5536
select SUPERIO_WINBOND_W83627HF
select UDELAY_TSC
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_256
select POWER_BUTTON_FORCE_ENABLE
select GX2_PROCESSOR_MHZ_366
config MAINBOARD_DIR
string
default amd/rumba
config MAINBOARD_PART_NUMBER
string
default "Rumba"
config IRQ_SLOT_COUNT
int
default 2
endif # BOARD_AMD_RUMBA

2
src/mainboard/amd/rumba/Kconfig.name
View File

@@ -1,2 +0,0 @@
config BOARD_AMD_RUMBA
bool "Rumba"

1
src/mainboard/amd/rumba/board_info.txt
View File

@@ -1 +0,0 @@
Category: half

28
src/mainboard/amd/rumba/cmos.layout
View File

@@ -1,28 +0,0 @@
entries
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#392 3 r 0 unused
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
456 1 e 1 ECC_memory
1008 16 h 0 check_sum
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 6 Notice
6 7 Info
6 8 Debug
6 9 Spew
checksums
checksum 392 1007 1008

20
src/mainboard/amd/rumba/devicetree.cb
View File

@@ -1,20 +0,0 @@
chip northbridge/amd/gx2
device cpu_cluster 0 on
chip cpu/amd/geode_gx2
device lapic 0 on end
end
end
device domain 0 on
device pci 1.0 on end
device pci 1.1 on end
chip southbridge/amd/cs5536
register "lpc_serirq_enable" = "0x80" # enabled with default timing
device pci d.0 on end # Realtek 8139 LAN
device pci f.0 on end # ISA Bridge
device pci f.2 on end # IDE Controller
device pci f.3 on end # Audio
device pci f.4 on end # OHCI
device pci f.5 on end # EHCI
end
end
end

55
src/mainboard/amd/rumba/irq_tables.c
View File

@@ -1,55 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/pirq_routing.h>
/* Platform IRQs */
#define PIRQA 11
#define PIRQB 5
#define PIRQC 10
#define PIRQD 10
/* Map */
#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
/* Link */
#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
(0x12 << 3)|0x0, /* Where the interrupt router lies (dev) */
0x800, /* IRQs devoted exclusively to PCI usage */
0x1078, /* Vendor */
0x2, /* Device */
0, /* Miniport data */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0xdf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
{
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x0e << 3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},
{0x00,(0x0f << 3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0},
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
}

50
src/mainboard/amd/rumba/mainboard.c
View File

@@ -1,50 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include <arch/io.h>
static void init(struct device *dev)
{
device_t nic = NULL;
unsigned bus = 0;
unsigned devfn = PCI_DEVFN(0xd, 0);
int nicirq = 1;
printk(BIOS_DEBUG, "AMD RUMBA ENTER %s\n", __func__);
if (nicirq) {
printk(BIOS_DEBUG, "%s (%x,%x)SET PCI interrupt line to %d\n",
__func__, bus, devfn, nicirq);
nic = dev_find_slot(bus, devfn);
if (! nic){
printk(BIOS_ERR, "Could not find NIC\n");
} else {
pci_write_config8(nic, PCI_INTERRUPT_LINE, nicirq);
}
}
printk(BIOS_DEBUG, "AMD RUMBA EXIT %s\n", __func__);
}
static void mainboard_enable(struct device *dev)
{
dev->ops->init = init;
}
struct chip_operations mainboard_ops = {
.enable_dev = mainboard_enable,
};

69
src/mainboard/amd/rumba/romstage.c
View File

@@ -1,69 +0,0 @@
/*
* This file is part of the coreboot project.
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <console/console.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/gx2def.h>
#include <spd.h>
#include <southbridge/amd/cs5536/cs5536.h>
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static inline int spd_read_byte(unsigned device, unsigned address)
{
if (device != DIMM0)
return 0xFF; /* No DIMM1, don't even try. */
return smbus_read_byte(device, address);
}
#include <northbridge/amd/gx2/raminit.h>
#include "northbridge/amd/gx2/pll_reset.c"
#include "northbridge/amd/gx2/raminit.c"
#include "lib/generic_sdram.c"
#include "cpu/amd/geode_gx2/cpureginit.c"
#include "cpu/amd/geode_gx2/syspreinit.c"
#include "cpu/amd/geode_lx/msrinit.c"
void asmlinkage mainboard_romstage_entry(unsigned long bist)
{
static const struct mem_controller memctrl [] = {
{.channel0 = {DIMM0, DIMM1}}
};
SystemPreInit();
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
cs5536_early_setup();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
pll_reset();
cpuRegInit();
printk(BIOS_ERR, "done cpuRegInit\n");
sdram_initialize(1, memctrl);
msr_init();
}

27
src/mainboard/lippert/frontrunner/Kconfig
View File

@@ -1,27 +0,0 @@
if BOARD_LIPPERT_FRONTRUNNER
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_AMD_GEODE_GX2
select NORTHBRIDGE_AMD_GX2
select SOUTHBRIDGE_AMD_CS5535
select SUPERIO_WINBOND_W83627HF
select HAVE_DEBUG_SMBUS
select UDELAY_TSC
select HAVE_PIRQ_TABLE
select BOARD_ROMSIZE_KB_256
select GX2_PROCESSOR_MHZ_366
config MAINBOARD_DIR
string
default lippert/frontrunner
config MAINBOARD_PART_NUMBER
string
default "Cool Frontrunner"
config IRQ_SLOT_COUNT
int
default 2
endif # BOARD_LIPPERT_FRONTRUNNER

2
src/mainboard/lippert/frontrunner/Kconfig.name
View File

@@ -1,2 +0,0 @@
config BOARD_LIPPERT_FRONTRUNNER
bool "Cool FrontRunner"

5
src/mainboard/lippert/frontrunner/board_info.txt
View File

@@ -1,5 +0,0 @@
Category: half
Board URL: http://www.lippertembedded.com/en/productoverview/products-in-detail/85-lipperts-cool-frontrunner.html
ROM package: PLCC
ROM protocol: FWH
ROM socketed: y

28
src/mainboard/lippert/frontrunner/cmos.layout
View File

@@ -1,28 +0,0 @@
entries
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#392 3 r 0 unused
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
456 1 e 1 ECC_memory
1008 16 h 0 check_sum
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 6 Notice
6 7 Info
6 8 Debug
6 9 Spew
checksums
checksum 392 1007 1008

20
src/mainboard/lippert/frontrunner/devicetree.cb
View File

@@ -1,20 +0,0 @@
chip northbridge/amd/gx2
device cpu_cluster 0 on
chip cpu/amd/geode_gx2
device lapic 0 on end
end
end
device domain 0 on
device pci 0.0 on
chip southbridge/amd/cs5535
register "setupflash" = "0"
device pci 12.0 on end
device pci 12.1 off end # SMI
device pci 12.2 on end # IDE
device pci 12.3 off end # Audio
device pci 12.4 off end # VGA
end
end
end
end

42
src/mainboard/lippert/frontrunner/irq_tables.c
View File

@@ -1,42 +0,0 @@
#include <arch/pirq_routing.h>
/* Platform IRQs */
#define PIRQA 11
#define PIRQB 5
#define PIRQC 10
#define PIRQD 10
/* Map */
#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
/* Link */
#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
0x00, /* Where the interrupt router lies (bus) */
(0x12 << 3)|0x0, /* Where the interrupt router lies (dev) */
0x800, /* IRQs devoted exclusively to PCI usage */
0x1078, /* Vendor */
0x2, /* Device */
0, /* Miniport data */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0xdf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
{
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00,(0x0e << 3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},
{0x00,(0x0f << 3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0},
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
}

127
src/mainboard/lippert/frontrunner/romstage.c
View File

@@ -1,127 +0,0 @@
#include <stdint.h>
#include <spd.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <console/console.h>
#include <superio/winbond/common/winbond.h>
#include <superio/winbond/w83627hf/w83627hf.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/gx2def.h>
#include <southbridge/amd/cs5535/cs5535.h>
#include "southbridge/amd/cs5535/early_smbus.c"
#include "southbridge/amd/cs5535/early_setup.c"
#define SERIAL_DEV PNP_DEV(0x2e, W83627HF_SP1)
static const unsigned char spdbytes[] = { /* 4x Qimonda HYB25DC512160CF-6 */
0xFF, 0xFF, /* only values used by raminit.c are set */
[SPD_MEMORY_TYPE] = SPD_MEMORY_TYPE_SDRAM_DDR, /* (Fundamental) memory type */
[SPD_NUM_ROWS] = 0x0D, /* Number of row address bits [13] */
[SPD_NUM_COLUMNS] = 0x0A, /* Number of column address bits [10] */
[SPD_NUM_DIMM_BANKS] = 1, /* Number of module rows (banks) */
0xFF, 0xFF, 0xFF,
[SPD_MIN_CYCLE_TIME_AT_CAS_MAX] = 0x60, /* SDRAM cycle time (highest CAS latency), RAS access time (tRAC) [6.0 ns in BCD] */
0xFF, 0xFF,
[SPD_REFRESH] = 0x82, /* Refresh rate/type [Self Refresh, 7.8 us] */
[SPD_PRIMARY_SDRAM_WIDTH] = 64, /* SDRAM width (primary SDRAM) [64 bits] */
0xFF, 0xFF, 0xFF,
[SPD_NUM_BANKS_PER_SDRAM] = 4, /* SDRAM device attributes, number of banks on SDRAM device */
[SPD_ACCEPTABLE_CAS_LATENCIES] = 0x1C, /* SDRAM device attributes, CAS latency [3, 2.5, 2] */
0xFF, 0xFF,
[SPD_MODULE_ATTRIBUTES] = 0x20, /* SDRAM module attributes [differential clk] */
[SPD_DEVICE_ATTRIBUTES_GENERAL] = 0x40, /* SDRAM device attributes, general [Concurrent AP] */
[SPD_SDRAM_CYCLE_TIME_2ND] = 0x60, /* SDRAM cycle time (2nd highest CAS latency) [6.0 ns in BCD] */
0xFF,
[SPD_SDRAM_CYCLE_TIME_3RD] = 0x75, /* SDRAM cycle time (3rd highest CAS latency) [7.5 ns in BCD] */
0xFF,
[SPD_tRP] = 72, /* Min. row precharge time [18 ns in units of 0.25 ns] */
[SPD_tRRD] = 48, /* Min. row active to row active [12 ns in units of 0.25 ns] */
[SPD_tRCD] = 72, /* Min. RAS to CAS delay [18 ns in units of 0.25 ns] */
[SPD_tRAS] = 42, /* Min. RAS pulse width = active to precharge delay [42 ns] */
[SPD_BANK_DENSITY] = 0x40, /* Density of each row on module [256 MB] */
0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF, 0xFF,
[SPD_tRFC] = 72 /* SDRAM Device Minimum Auto Refresh to Active/Auto Refresh [72 ns] */
};
static inline int spd_read_byte(unsigned int device, unsigned int address)
{
if (device != DIMM0)
return 0xFF; /* No DIMM1, don't even try. */
#if IS_ENABLED(CONFIG_DEBUG_SMBUS)
if (address >= sizeof(spdbytes) || spdbytes[address] == 0xFF) {
printk(BIOS_ERR, "ERROR: spd_read_byte(DIMM0, 0x%02x) "
"returns 0xff\n", address);
}
#endif
/* Fake SPD ROM value */
return (address < sizeof(spdbytes)) ? spdbytes[address] : 0xFF;
}
#include <northbridge/amd/gx2/raminit.h>
#include "northbridge/amd/gx2/pll_reset.c"
#include "northbridge/amd/gx2/raminit.c"
#include "lib/generic_sdram.c"
#include "cpu/amd/geode_gx2/cpureginit.c"
#include "cpu/amd/geode_gx2/syspreinit.c"
#include "cpu/amd/geode_lx/msrinit.c"
void asmlinkage mainboard_romstage_entry(unsigned long bist)
{
static const struct mem_controller memctrl [] = {
{.channel0 = {DIMM0, DIMM1}}
};
unsigned char temp;
SystemPreInit();
msr_init();
winbond_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
console_init();
cs5535_early_setup();
printk(BIOS_ERR, "done cs5535 early\n");
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
pll_reset();
printk(BIOS_ERR, "done pll_reset\n");
cpuRegInit();
printk(BIOS_ERR, "done cpuRegInit\n");
sdram_initialize(1, memctrl);
printk(BIOS_ERR, "Done sdram_initialize\n");
printk(BIOS_ERR, "Disable watchdog\n");
outb( 0x87, 0x4E); //enter SuperIO configuration mode
outb( 0x87, 0x4E);
outb(0x20, 0x4e);
temp = inb(0x4f);
printk(BIOS_DEBUG, "%02x", temp);
if (temp != 0x52){
printk(BIOS_ERR, "CAN NOT READ SUPERIO VID\n");
}
outb(0x29, 0x4e);
outb(0x7c, 0x4f);
outb( 0x07, 0x4E); //enable logical device 9
outb( 0x09, 0x4F);
outb(0x30, 0x4e);
outb(1, 0x4f);
outb( 0xF0, 0x4E); //set GP33 as outbut in configuration register F0h Bit4 = \u20180\u2019
outb( 0xC7, 0x4F);
outb( 0xF1, 0x4E); //clr GP33 (Bit4) value in cofiguration register F1h to \u20181\u2019 disables
temp = inb(0x4F); //watchdog function. Make sure to let the other Bits unchanged!
printk(BIOS_DEBUG, "%02x:", temp);
temp = temp & ~8;
outb( temp, 0x4F);
temp = inb(0x4F); //watchdog function. Make sure to let the other Bits unchanged!
printk(BIOS_DEBUG, "%02x\n", temp);
}

30
src/mainboard/wyse/Kconfig
View File

@@ -1,30 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2010 Nils Jacobs
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
if VENDOR_WYSE
choice
prompt "Mainboard model"
source "src/mainboard/wyse/*/Kconfig.name"
endchoice
source "src/mainboard/wyse/*/Kconfig"
config MAINBOARD_VENDOR
string
default "Wyse"
endif # VENDOR_WYSE

2
src/mainboard/wyse/Kconfig.name
View File

@@ -1,2 +0,0 @@
config VENDOR_WYSE
bool "Wyse"

41
src/mainboard/wyse/s50/Kconfig
View File

@@ -1,41 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2010 Nils Jacobs
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
if BOARD_WYSE_S50
config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y
select CPU_AMD_GEODE_GX2
select NORTHBRIDGE_AMD_GX2
select SOUTHBRIDGE_AMD_CS5536
select UDELAY_TSC
select HAVE_PIRQ_TABLE
select PIRQ_ROUTE
select BOARD_ROMSIZE_KB_256
select POWER_BUTTON_FORCE_DISABLE
select GX2_PROCESSOR_MHZ_366
config MAINBOARD_DIR
string
default wyse/s50
config MAINBOARD_PART_NUMBER
string
default "s50"
config IRQ_SLOT_COUNT
int
default 3
endif # BOARD_WYSE_S50

2
src/mainboard/wyse/s50/Kconfig.name
View File

@@ -1,2 +0,0 @@
config BOARD_WYSE_S50
bool "S50"

7
src/mainboard/wyse/s50/board_info.txt
View File

@@ -1,7 +0,0 @@
Board name: S50
Category: settop
Board URL: http://au.wyse.com/products/hardware/thinclients/S50/index.asp
ROM package: PLCC
ROM protocol: LPC
ROM socketed: y
Flashrom support: y

46
src/mainboard/wyse/s50/cmos.layout
View File

@@ -1,46 +0,0 @@
#
# This file is part of the coreboot project.
#
# Copyright (C) 2010 Nils Jacobs
#
# This program is free software; you can redistribute it and/or
# modify it under the terms of the GNU General Public License as
# published by the Free Software Foundation; version 2 of
# the License.
#
# This program is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# -----------------------------------------------------------------
entries
0 384 r 0 reserved_memory
384 1 e 4 boot_option
388 4 h 0 reboot_counter
#392 3 r 0 unused
400 1 e 1 power_on_after_fail
412 4 e 6 debug_level
456 1 e 1 ECC_memory
1008 16 h 0 check_sum
enumerations
#ID value text
1 0 Disable
1 1 Enable
2 0 Enable
2 1 Disable
4 0 Fallback
4 1 Normal
6 6 Notice
6 7 Info
6 8 Debug
6 9 Spew
checksums
checksum 392 1007 1008

46
src/mainboard/wyse/s50/devicetree.cb
View File

@@ -1,46 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2010 Nils Jacobs
##
## This program is free software; you can redistribute it and/or
## modify it under the terms of the GNU General Public License as
## published by the Free Software Foundation; version 2 of
## the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
chip northbridge/amd/gx2
device domain 0 on
device pci 1.0 on end # Geode GX2 Host Bridge
device pci 1.1 on end # Geode GX2 Graphics Processor
chip southbridge/amd/cs5536
register "enable_gpio_int_route" = "0x0D0C0700"
register "enable_ide_nand_flash" = "0" # 0:ide mode, 1:flash
register "enable_USBP4_device" = "0" #0: host, 1:device
register "enable_USBP4_overcurrent" = "0" #0:off, xxxx:overcurrent setting CS5536 Data Book (pages 380-381)
register "com1_enable" = "1"
register "com1_address" = "0x3F8"
register "com1_irq" = "4"
register "com2_enable" = "0"
register "com2_address" = "0x2F8"
register "com2_irq" = "3"
device pci e.0 on end # Realtek 8139 LAN
device pci f.0 on end # ISA Bridge
device pci f.2 on end # IDE Controller
device pci f.3 on end # Audio
device pci f.4 on end # OHCI
device pci f.5 on end # EHCI
end
end
# APIC cluster is late CPU init.
device cpu_cluster 0 on
chip cpu/amd/geode_gx2
device lapic 0 on end
end
end
end

63
src/mainboard/wyse/s50/irq_tables.c
View File

@@ -1,63 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Nils Jacobs
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2 of the License, or
* (at your option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/pirq_routing.h>
/* Platform IRQs */
#define PIRQA 11
#define PIRQB 5
#define PIRQC 10
#define PIRQD 10
/* Map */
#define M_PIRQA (1 << PIRQA) /* Bitmap of supported IRQs */
#define M_PIRQB (1 << PIRQB) /* Bitmap of supported IRQs */
#define M_PIRQC (1 << PIRQC) /* Bitmap of supported IRQs */
#define M_PIRQD (1 << PIRQD) /* Bitmap of supported IRQs */
/* Link */
#define L_PIRQA 1 /* Means Slot INTx# Connects To Chipset INTA# */
#define L_PIRQB 2 /* Means Slot INTx# Connects To Chipset INTB# */
#define L_PIRQC 3 /* Means Slot INTx# Connects To Chipset INTC# */
#define L_PIRQD 4 /* Means Slot INTx# Connects To Chipset INTD# */
static const struct irq_routing_table intel_irq_routing_table = {
PIRQ_SIGNATURE, /* u32 signature */
PIRQ_VERSION, /* u16 version */
32 + 16 * CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
0x00, /* Interrupt router bus */
(0x0f << 3) | 0x0, /* Interrupt router dev */
0, /* IRQs devoted exclusively to PCI usage */
0x100b, /* Vendor */
0x2b, /* Device */
0, /* Miniport */
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
0xdc, /* Checksum (has to be set to some value that
* would give 0 after the sum of all bytes
* for this structure (including checksum).
*/
{
/* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
{0x00, (0x0f << 3) | 0x0, {{0x01, 0x0800}, {0x02, 0x0020}, {0x03, 0x0400}, {0x04, 0x0400}}, 0x5, 0x0},
{0x00, (0x0d << 3) | 0x0, {{0x04, 0x0400}, {0x03, 0x0400}, {0x02, 0x0020}, {0x01, 0x0800}}, 0x1, 0x0},
{0x00, (0x0e << 3) | 0x0, {{0x01, 0x0800}, {0x02, 0x0020}, {0x03, 0x0400}, {0x04, 0x0400}}, 0x2, 0x0},
}
};
unsigned long write_pirq_routing_table(unsigned long addr)
{
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
}

72
src/mainboard/wyse/s50/romstage.c
View File

@@ -1,72 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Nils Jacobs
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <stdint.h>
#include <device/pci_def.h>
#include <arch/io.h>
#include <device/pnp_def.h>
#include <console/console.h>
#include <lib.h>
#include <cpu/x86/bist.h>
#include <cpu/x86/msr.h>
#include <cpu/amd/gx2def.h>
#include <spd.h>
#include <southbridge/amd/cs5536/cs5536.h>
static inline int spd_read_byte(unsigned int device, unsigned int address)
{
if (device != DIMM0)
return 0xFF; /* No DIMM1, don't even try. */
return smbus_read_byte(device, address);
}
#include <northbridge/amd/gx2/raminit.h>
#include "northbridge/amd/gx2/pll_reset.c"
#include "northbridge/amd/gx2/raminit.c"
#include "lib/generic_sdram.c"
#include "cpu/amd/geode_gx2/cpureginit.c"
#include "cpu/amd/geode_gx2/syspreinit.c"
#include "cpu/amd/geode_lx/msrinit.c"
void asmlinkage mainboard_romstage_entry(unsigned long bist)
{
static const struct mem_controller memctrl [] = {
{.channel0 = {DIMM0, DIMM1}}
};
SystemPreInit();
cs5536_early_setup();
/* cs5536_disable_internal_uart disable them. Set them up now... */
cs5536_setup_onchipuart(1);
console_init();
/* Halt if there was a built in self test failure */
report_bist_failure(bist);
pll_reset();
cpuRegInit();
printk(BIOS_ERR, "done cpuRegInit\n");
sdram_initialize(1, memctrl);
printk(BIOS_ERR, "ram setup done\n");
msr_init();
}

73
src/northbridge/amd/gx2/Kconfig
View File

@@ -1,73 +0,0 @@
##
## This file is part of the coreboot project.
##
## Copyright (C) 2007-2009 coresystems GmbH
##
## This program is free software; you can redistribute it and/or modify
## it under the terms of the GNU General Public License as published by
## the Free Software Foundation; version 2 of the License.
##
## This program is distributed in the hope that it will be useful,
## but WITHOUT ANY WARRANTY; without even the implied warranty of
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
## GNU General Public License for more details.
##
config NORTHBRIDGE_AMD_GX2
bool
select GEODE_VSA
select LATE_CBMEM_INIT
if NORTHBRIDGE_AMD_GX2
choice
prompt "Framebuffer size"
default GX2_VIDEO_MB_8MB
config GX2_VIDEO_MB_4MB
bool "4MB"
config GX2_VIDEO_MB_8MB
bool "8MB"
config GX2_VIDEO_MB_16MB
bool "16MB"
config GX2_VIDEO_MB_32MB
bool "32MB"
config GX2_VIDEO_MB_64MB
bool "64MB"
config GX2_VIDEO_MB_128MB
bool "128MB"
config GX2_VIDEO_MB_256MB
bool "256MB"
config GX2_VIDEO_MB_CMOS
bool "Use CMOS option"
endchoice
config VIDEO_MB
int
default 4 if GX2_VIDEO_MB_4MB
default 8 if GX2_VIDEO_MB_8MB
default 16 if GX2_VIDEO_MB_16MB
default 32 if GX2_VIDEO_MB_32MB
default 64 if GX2_VIDEO_MB_64MB
default 128 if GX2_VIDEO_MB_128MB
default 256 if GX2_VIDEO_MB_256MB
default -1 if GX2_VIDEO_MB_CMOS
# The GX2_PROCESSOR_MHZ options let you chose the correct GX2 processor
# speed in the mainboard's Kconfig file.
config GX2_PROCESSOR_MHZ_300
bool
config GX2_PROCESSOR_MHZ_366
bool
config GX2_PROCESSOR_MHZ_400
bool
# Map the config names to an integer (MHz).
config GX2_PROCESSOR_MHZ
int
default 300 if GX2_PROCESSOR_MHZ_300
default 366 if GX2_PROCESSOR_MHZ_366
default 400 if GX2_PROCESSOR_MHZ_400
endif # NORTHBRIDGE_AMD_GX2

7
src/northbridge/amd/gx2/Makefile.inc
View File

@@ -1,7 +0,0 @@
ifeq ($(CONFIG_NORTHBRIDGE_AMD_GX2),y)
ramstage-y += northbridge.c
ramstage-y += northbridgeinit.c
ramstage-y += grphinit.c
endif

85
src/northbridge/amd/gx2/grphinit.c
View File

@@ -1,85 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
* Copyright (C) 2012 Nils Jacobs
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <arch/io.h>
#include <stdint.h>
#include <cpu/amd/vr.h>
#include <console/console.h>
#include <cpu/amd/gx2def.h>
#include <cpu/x86/msr.h>
#include <stdlib.h>
void geodegx2_vga_msr_init(void);
void graphics_init(void);
struct msrinit {
u32 msrnum;
msr_t msr;
};
static const struct msrinit geodegx2_vga_msr[] = {
/* Enable the GLIU Memory routing to the memory A0000-BFFFF
* PDID1 : Port 4, GLIU0
* PBASE : 0x000A0
* PMASK : 0xFFFE0
*/
{.msrnum = GLIU0_P2D_BM_4, {.lo = 0x0a0fffe0, .hi = 0x80000000}},
};
void geodegx2_vga_msr_init(void)
{
int i;
for (i = 0; i < ARRAY_SIZE(geodegx2_vga_msr); i++)
wrmsr(geodegx2_vga_msr[i].msrnum, geodegx2_vga_msr[i].msr);
}
/* This function mirrors the Graphics_Init routine in GeodeROM. */
void graphics_init(void)
{
uint16_t wClassIndex, wData, res;
/* SoftVG initialization */
printk(BIOS_DEBUG, "Graphics init...\n");
geodegx2_vga_msr_init();
/* Call SoftVG with the main configuration parameters. */
/* NOTE: SoftVG expects the memory size to be given in 512 KB blocks */
wClassIndex = (VRC_VG << 8) + VG_CONFIG;
/*
* Graphics Driver Enabled (13) 0, NO (lets BIOS controls the GP)
* External Monochrome Card Support(12) 0, NO
* Controller Priority Select(11) 1, Primary
* Display Select(10:8) 0x0, CRT
* Graphics Memory Size(7:1) CONFIG_VIDEO_MB >> 1,
* defined in devicetree.cb
* PLL Reference Clock Bypass(0) 0, Default
*/
/* Video RAM has to be given in 512KB chunks
* the value is read @ 7:1 (value in 7:0 looks like /2)
* so we can add the real value in megabytes
*/
wData = VG_CFG_PRIORITY | VG_CFG_DSCRT | ((CONFIG_VIDEO_MB * 2) & VG_MEM_MASK);
vrWrite(wClassIndex, wData);
res = vrRead(wClassIndex);
printk(BIOS_DEBUG, "VRC_VG value: 0x%04x\n", res);
}

347
src/northbridge/amd/gx2/northbridge.c
View File

@@ -1,347 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
* Copyright (C) 2010 Nils Jacobs
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <arch/io.h>
#include <stdint.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <stdlib.h>
#include <string.h>
#include "northbridge.h"
#include <cpu/x86/msr.h>
#include <cpu/x86/cache.h>
#include <cpu/amd/vr.h>
#include <cpu/cpu.h>
#include "../../../southbridge/amd/cs5536/cs5536.h"
void print_conf(void);
/* Print the platform configuration - do before PCI init or it will not
* work right.
*/
void print_conf(void)
{
#if CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR
int i;
unsigned long iol;
msr_t msr;
int cpu_msr_defs[] = { CPU_IM_CONFIG, CPU_DM_CONFIG0,
CPU_RCONF_DEFAULT, CPU_RCONF_BYPASS, CPU_RCONF_A0_BF,
CPU_RCONF_C0_DF, CPU_RCONF_E0_FF, CPU_RCONF_SMM, CPU_RCONF_DMM,
GLCP_DELAY_CONTROLS, GL_END
};
int gliu0_msr_defs[] = { GLIU0_P2D_BM_0, GLIU0_P2D_BM_1,
GLIU0_P2D_BM_2, GLIU0_P2D_BM_3, GLIU0_P2D_BM_4,
GLIU0_P2D_BM_5, GLIU0_P2D_BMO_0, GLIU0_P2D_BMO_1,
GLIU0_P2D_R_0, GLIU0_P2D_RO_0, GLIU0_P2D_RO_1,
GLIU0_P2D_RO_2, GLIU0_P2D_SC_0, GLIU0_IOD_BM_0, GLIU0_IOD_BM_1,
GLIU0_IOD_BM_2, GLIU0_IOD_SC_0, GLIU0_IOD_SC_1, GLIU0_IOD_SC_2,
GLIU0_IOD_SC_3, GLIU0_IOD_SC_4, GLIU0_IOD_SC_5,
GLIU0_GLD_MSR_COH, GL_END
};
int gliu1_msr_defs[] = { GLIU1_P2D_BM_0, GLIU1_P2D_BM_1,
GLIU1_P2D_BM_2, GLIU1_P2D_BM_3, GLIU1_P2D_BM_4,
GLIU1_P2D_BM_5, GLIU1_P2D_BM_6, GLIU1_P2D_BM_7,
GLIU1_P2D_BM_8, GLIU1_P2D_R_0, GLIU1_P2D_R_1,
GLIU1_P2D_R_2, GLIU1_P2D_R_3, GLIU1_P2D_SC_0,
GLIU1_IOD_BM_0, GLIU1_IOD_BM_1, GLIU1_IOD_BM_2, GLIU1_IOD_SC_0,
GLIU1_IOD_SC_1, GLIU1_IOD_SC_2, GLIU1_IOD_SC_3, GLIU1_IOD_SC_4,
GLIU1_IOD_SC_5, GLIU1_GLD_MSR_COH, GL_END
};
int rconf_msr[] = { CPU_RCONF0, CPU_RCONF1, CPU_RCONF2, CPU_RCONF3,
CPU_RCONF4, CPU_RCONF5, CPU_RCONF6, CPU_RCONF7, GL_END
};
int lbar_msr[] = { MDD_LBAR_GPIO, MDD_LBAR_FLSH0, MDD_LBAR_FLSH1, GL_END
};
int irq_msr[] = { MDD_IRQM_YLOW, MDD_IRQM_YHIGH, MDD_IRQM_ZLOW, MDD_IRQM_ZHIGH,
MDD_IRQM_PRIM, GL_END
};
int pci_msr[] = { GLPCI_CTRL, GLPCI_ARB, GLPCI_REN, GLPCI_A0_BF,
GLPCI_C0_DF, GLPCI_E0_FF, GLPCI_RC0, GLPCI_RC1, GLPCI_RC2,
GLPCI_RC3, GLPCI_ExtMSR, GLPCI_SPARE, GL_END
};
int dma_msr[] = { MDD_DMA_MAP, MDD_DMA_SHAD1, MDD_DMA_SHAD2,
MDD_DMA_SHAD3, MDD_DMA_SHAD4, MDD_DMA_SHAD5, MDD_DMA_SHAD6,
MDD_DMA_SHAD7, MDD_DMA_SHAD8, MDD_DMA_SHAD9, GL_END
};
printk(BIOS_DEBUG, "---------- CPU ------------\n");
for (i = 0; cpu_msr_defs[i] != GL_END; i++) {
msr = rdmsr(cpu_msr_defs[i]);
printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
cpu_msr_defs[i], msr.hi, msr.lo);
}
printk(BIOS_DEBUG, "---------- GLIU 0 ------------\n");
for (i = 0; gliu0_msr_defs[i] != GL_END; i++) {
msr = rdmsr(gliu0_msr_defs[i]);
printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
gliu0_msr_defs[i], msr.hi, msr.lo);
}
printk(BIOS_DEBUG, "---------- GLIU 1 ------------\n");
for (i = 0; gliu1_msr_defs[i] != GL_END; i++) {
msr = rdmsr(gliu1_msr_defs[i]);
printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n",
gliu1_msr_defs[i], msr.hi, msr.lo);
}
printk(BIOS_DEBUG, "---------- RCONF ------------\n");
for (i = 0; rconf_msr[i] != GL_END; i++) {
msr = rdmsr(rconf_msr[i]);
printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", rconf_msr[i],
msr.hi, msr.lo);
}
printk(BIOS_DEBUG, "---------- VARIA ------------\n");
msr = rdmsr(ATA_SB_IDE_CFG);
printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", ATA_SB_IDE_CFG, msr.hi,
msr.lo);
msr = rdmsr(MDD_LEG_IO);
printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_LEG_IO, msr.hi,
msr.lo);
msr = rdmsr(MDD_PIN_OPT);
printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", MDD_PIN_OPT, msr.hi,
msr.lo);
printk(BIOS_DEBUG, "---------- PCI ------------\n");
for (i = 0; pci_msr[i] != GL_END; i++) {
msr = rdmsr(pci_msr[i]);
printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", pci_msr[i],
msr.hi, msr.lo);
}
printk(BIOS_DEBUG, "---------- LPC/UART DMA ------------\n");
for (i = 0; dma_msr[i] != GL_END; i++) {
msr = rdmsr(dma_msr[i]);
printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", dma_msr[i],
msr.hi, msr.lo);
}
printk(BIOS_DEBUG, "---------- DIVIL IRQ ------------\n");
for (i = 0; irq_msr[i] != GL_END; i++) {
msr = rdmsr(irq_msr[i]);
printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", irq_msr[i],
msr.hi, msr.lo);
}
printk(BIOS_DEBUG, "---------- DIVIL LBAR -----------\n");
for (i = 0; lbar_msr[i] != GL_END; i++) {
msr = rdmsr(lbar_msr[i]);
printk(BIOS_DEBUG, "MSR 0x%08X is now 0x%08X:0x%08X\n", lbar_msr[i],
msr.hi, msr.lo);
}
iol = inl(GPIO_IO_BASE + GPIOL_INPUT_ENABLE);
printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",
GPIO_IO_BASE + GPIOL_INPUT_ENABLE, iol);
iol = inl(GPIOL_EVENTS_ENABLE);
printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",
GPIO_IO_BASE + GPIOL_EVENTS_ENABLE, iol);
iol = inl(GPIOL_INPUT_INVERT_ENABLE);
printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n",
GPIO_IO_BASE + GPIOL_INPUT_INVERT_ENABLE, iol);
iol = inl(GPIO_MAPPER_X);
printk(BIOS_DEBUG, "IOR 0x%08X is now 0x%08lX\n", GPIO_IO_BASE + GPIO_MAPPER_X,
iol);
#endif /* CONFIG_DEFAULT_CONSOLE_LOGLEVEL >= BIOS_ERR */
}
/* todo: add a resource record. We don't do this here because this may be called when
* very little of the platform is actually working.
*/
int sizeram(void)
{
msr_t msr;
int sizem = 0;
unsigned short dimm;
/* Get the RAM size from the memory controller as calculated and set by auto_size_dimm() */
msr = rdmsr(MC_CF07_DATA);
printk(BIOS_DEBUG, "sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi, msr.lo);
/* dimm 0 */
dimm = msr.hi;
/* installed? */
if ((dimm & 7) != 7)
sizem = (1 << ((dimm >> 12)-1)) * 8;
/* dimm 1 */
dimm = msr.hi >> 16;
/* installed? */
if ((dimm & 7) != 7)
sizem += (1 << ((dimm >> 12)-1)) * 8;
printk(BIOS_DEBUG, "sizeram: sizem 0x%x\n", sizem);
return sizem;
}
static void enable_shadow(device_t dev)
{
}
static void northbridge_init(device_t dev)
{
printk(BIOS_SPEW, ">> Entering northbridge: %s()\n", __func__);
enable_shadow(dev);
}
static void northbridge_set_resources(struct device *dev)
{
uint8_t line;
struct bus *bus;
for (bus = dev->link_list; bus; bus = bus->next) {
if (bus->children) {
printk(BIOS_DEBUG, "my_dev_set_resources: assign_resources %d\n",
bus->secondary);
assign_resources(bus);
}
}
/* set a default latency timer */
pci_write_config8(dev, PCI_LATENCY_TIMER, 0x40);
/* set a default secondary latency timer */
if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) {
pci_write_config8(dev, PCI_SEC_LATENCY_TIMER, 0x40);
}
/* zero the irq settings */
line = pci_read_config8(dev, PCI_INTERRUPT_PIN);
if (line) {
pci_write_config8(dev, PCI_INTERRUPT_LINE, 0);
}
/* set the cache line size, so far 64 bytes is good for everyone */
pci_write_config8(dev, PCI_CACHE_LINE_SIZE, 64 >> 2);
}
static struct device_operations northbridge_operations = {
.read_resources = pci_dev_read_resources,
.set_resources = northbridge_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = northbridge_init,
.enable = 0,
.ops_pci = 0,
};
static const struct pci_driver northbridge_driver __pci_driver = {
.ops = &northbridge_operations,
.vendor = PCI_VENDOR_ID_NS,
.device = PCI_DEVICE_ID_NS_GX2,
};
#include <cbmem.h>
static void pci_domain_set_resources(device_t dev)
{
int idx;
u32 tomk;
device_t mc_dev;
printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
mc_dev = dev->link_list->children;
if (mc_dev) {
tomk = get_systop() / 1024;
/* Report the memory regions
All memory up to systop except 0xa0000-0xbffff */
idx = 10;
ram_resource(dev, idx++, 0, 640);
ram_resource(dev, idx++, 768, tomk - 768); /* Systop - 0xc0000 -> KB */
set_late_cbmem_top(tomk * 1024);
}
assign_resources(dev->link_list);
}
static void pci_domain_enable(device_t dev)
{
printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
/* do this here for now -- this chip really breaks our device model */
northbridge_init_early();
cpubug();
chipsetinit();
print_conf();
do_vsmbios();
graphics_init();
}
static struct device_operations pci_domain_ops = {
.read_resources = pci_domain_read_resources,
.set_resources = pci_domain_set_resources,
.enable_resources = NULL,
.scan_bus = pci_domain_scan_bus,
.enable = pci_domain_enable,
.ops_pci_bus = pci_bus_default_ops,
};
static void cpu_bus_init(device_t dev)
{
printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __func__);
initialize_cpus(dev->link_list);
}
static struct device_operations cpu_bus_ops = {
.read_resources = DEVICE_NOOP,
.set_resources = DEVICE_NOOP,
.enable_resources = DEVICE_NOOP,
.init = cpu_bus_init,
.scan_bus = 0,
};
static void enable_dev(struct device *dev)
{
printk(BIOS_SPEW, ">> Entering northbridge.c: %s with path %d\n",
__func__, dev->path.type);
/* Set the operations if it is a special bus type */
if (dev->path.type == DEVICE_PATH_DOMAIN)
dev->ops = &pci_domain_ops;
else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER)
dev->ops = &cpu_bus_ops;
}
struct chip_operations northbridge_amd_gx2_ops = {
CHIP_NAME("AMD GX (previously GX2) Northbridge")
.enable_dev = enable_dev,
};

16
src/northbridge/amd/gx2/northbridge.h
View File

@@ -1,16 +0,0 @@
#ifndef NORTHBRIDGE_AMD_GX2_H
#define NORTHBRIDGE_AMD_GX2_H
#include <cpu/amd/gx2def.h>
/* northbridge.c */
unsigned int gx2_scan_root_bus(device_t root, unsigned int max);
int sizeram(void);
void do_vsmbios(void);
void graphics_init(void);
/* northbridgeinit.c */
void northbridge_init_early(void);
uint32_t get_systop(void);
#endif /* NORTHBRIDGE_AMD_GX2_H */

673
src/northbridge/amd/gx2/northbridgeinit.c
View File

@@ -1,673 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
* Copyright (C) 2010 Nils Jacobs
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <console/console.h>
#include <arch/io.h>
#include <stdint.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <stdlib.h>
#include <string.h>
#include "northbridge.h"
#include <cpu/amd/gx2def.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/cache.h>
struct gliutable
{
unsigned long desc_name;
unsigned short desc_type;
unsigned long hi, lo;
};
struct gliutable gliu0table[] = {
{.desc_name = GLIU0_P2D_BM_0, .desc_type= BM,.hi= MSR_MC + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */
{.desc_name = GLIU0_P2D_BM_1, .desc_type= BM,.hi= MSR_MC + 0x0,.lo=(0x80 << 20) + 0x0FFFE0}, /* 80000-9ffff to Mc */
{.desc_name = GLIU0_P2D_SC_0, .desc_type= SC_SHADOW,.hi= MSR_MC + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) A0000-Bffff handled by SoftVideo */
{.desc_name = GLIU0_P2D_R_0, .desc_type= R_SYSMEM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */
{.desc_name = GLIU0_P2D_BMO_0, .desc_type= BMO_SMM,.hi= MSR_MC,.lo= 0x0}, /* Catch and fix dynamicly. */
{.desc_name = GLIU0_GLD_MSR_COH, .desc_type= OTHER,.hi= 0x0,.lo= GL0_CPU},
{.desc_name = GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0},
};
struct gliutable gliu1table[] = {
{.desc_name = GLIU1_P2D_BM_0, .desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= 0x0FFF80}, /* 0-7FFFF to MC */
{.desc_name = GLIU1_P2D_BM_1, .desc_type= BM,.hi= MSR_GL0 + 0x0,.lo= (0x80 << 20) + 0x0FFFE0},/* 80000-9ffff to Mc */
{.desc_name = GLIU1_P2D_SC_0, .desc_type= SC_SHADOW,.hi= MSR_GL0 + 0x0,.lo= 0x03}, /* C0000-Fffff split to MC and PCI (sub decode) */
{.desc_name = GLIU1_P2D_R_0, .desc_type= R_SYSMEM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */
{.desc_name = GLIU1_P2D_BM_3, .desc_type= BM_SMM,.hi= MSR_GL0,.lo= 0x0}, /* Catch and fix dynamicly. */
{.desc_name = GLIU1_GLD_MSR_COH, .desc_type= OTHER,.hi= 0x0,.lo= GL1_GLIU0},
{.desc_name = GLIU1_IOD_SC_0, .desc_type= SCIO,.hi= (GL1_GLCP << 29) + 0x0,.lo= 0x033000F0}, /* FooGlue FPU 0xF0 */
{.desc_name = GL_END, .desc_type= GL_END,.hi= 0x0,.lo= 0x0},
};
struct gliutable *gliutables[] = { gliu0table, gliu1table, 0 };
struct msrinit
{
unsigned long msrnum;
msr_t msr;
};
struct msrinit ClockGatingDefault[] = {
{GLIU0_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}},
/* MC must stay off in SDR mode. It is turned on in CPUBug??? lotus #77.142 */
{MC_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}},
{GLIU1_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0005}},
{VG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}}, /* lotus #77.163 */
{GP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0001}},
{DF_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0155}},
{GLCP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}},
{GLPCI_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}},
{FG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}}, /* Always on */
{0xffffffff, {0xffffffff, 0xffffffff}},
};
/* All On */
struct msrinit ClockGatingAllOn[] = {
{GLIU0_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}},
{MC_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}},
{GLIU1_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}},
{VG_GLD_MSR_PM, {.hi = 0x00, .lo = 0x00}},
{GP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x000000001}},
{DF_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}},
{GLCP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}},
{GLPCI_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0FFFFFFFF}},
{FG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}},
{0xffffffff, {0xffffffff, 0xffffffff}},
};
/* Performance */
struct msrinit ClockGatingPerformance[] = {
{VG_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0000}}, /* lotus #77.163 */
{GP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0001}},
{DF_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0155}},
{GLCP_GLD_MSR_PM, {.hi = 0x00,.lo = 0x0015}},
{0xffffffff, {0xffffffff, 0xffffffff}},
};
/* SET GeodeLink PRIORITY */
struct msrinit GeodeLinkPriorityTable[] = {
{CPU_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0220}}, /* CPU Priority. */
{DF_GLD_MSR_MASTER_CONF, {.hi = 0x00,.lo = 0x0000}}, /* DF Priority. */
{VG_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0720}}, /* VG Primary and Secondary Priority. */
{GP_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0010}}, /* Graphics Priority. */
{GLPCI_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0027}}, /* GLPCI Priority + PID */
{GLCP_GLD_MSR_CONF, {.hi = 0x00,.lo = 0x0001}}, /* GLCP Priority + PID */
{FG_GLD_MSR_CONFIG, {.hi = 0x00,.lo = 0x0622}}, /* FG PID */
{0x0FFFFFFFF, {0x0FFFFFFFF, 0x0FFFFFFFF}}, /* END */
};
static void writeglmsr(struct gliutable *gl)
{
msr_t msr;
msr.lo = gl->lo;
msr.hi = gl->hi;
wrmsr(gl->desc_name, msr); /* MSR - see table above */
printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
}
static void ShadowInit(struct gliutable *gl)
{
msr_t msr;
msr = rdmsr(gl->desc_name);
if (msr.lo == 0) {
writeglmsr(gl);
}
}
static void SysmemInit(struct gliutable *gl)
{
msr_t msr;
int sizembytes, sizebytes;
/* Figure out how much RAM is in the machine and alocate all to the
* system. We will adjust for SMM now and Frame Buffer later.
*/
sizembytes = sizeram();
printk(BIOS_DEBUG, "%s: enable for %dMBytes\n", __func__, sizembytes);
sizebytes = sizembytes << 20;
sizebytes -= ((SMM_SIZE * 1024) + 1);
/* 20 bit address The bottom 12 bits go into bits 20-31 in msr.lo
The top 8 bits go into 0-7 of msr.hi. */
sizebytes --;
msr.hi = (gl->hi & 0xFFFFFF00) | (sizebytes >> 24);
sizebytes <<= 8; /* move bits 23:12 in bits 31:20. */
sizebytes &= 0xfff00000;
sizebytes |= 0x100; /* start at 1MB */
msr.lo = sizebytes;
wrmsr(gl->desc_name, msr); /* MSR - see table above */
printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__,
gl->desc_name, msr.hi, msr.lo);
}
static void SMMGL0Init(struct gliutable *gl)
{
msr_t msr;
int sizebytes = sizeram() << 20;
long offset;
sizebytes -= (SMM_SIZE * 1024);
printk(BIOS_DEBUG, "%s: %d bytes\n", __func__, sizebytes);
offset = sizebytes - SMM_OFFSET;
offset = (offset >> 12) & 0x000fffff;
printk(BIOS_DEBUG, "%s: offset is 0x%08x\n", __func__, SMM_OFFSET);
msr.hi = offset << 8 | gl->hi;
msr.hi |= SMM_OFFSET >> 24;
msr.lo = (SMM_OFFSET & 0x00ffffff) << 8;
msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;
wrmsr(gl->desc_name, msr); /* MSR - See table above */
printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
}
static void SMMGL1Init(struct gliutable *gl)
{
msr_t msr;
printk(BIOS_DEBUG, "%s:\n", __func__);
msr.hi = gl->hi;
/* I don't think this is needed */
msr.hi &= 0xffffff00;
msr.hi |= (SMM_OFFSET >> 24);
msr.lo = (SMM_OFFSET & 0x00fff000) << 8;
msr.lo |= ((~(SMM_SIZE * 1024) + 1) >> 12) & 0xfffff;
wrmsr(gl->desc_name, msr); /* MSR - See table above */
printk(BIOS_DEBUG, "%s: MSR 0x%08lx, val 0x%08x:0x%08x\n", __func__, gl->desc_name, msr.hi, msr.lo);
}
static void GLIUInit(struct gliutable *gl)
{
while (gl->desc_type != GL_END) {
switch (gl->desc_type) {
default:
writeglmsr(gl);
case SC_SHADOW: /* Check for a Shadow entry */
ShadowInit(gl);
break;
case R_SYSMEM: /* check for a SYSMEM entry */
SysmemInit(gl);
break;
case BMO_SMM: /* check for a SMM entry */
SMMGL0Init(gl);
break;
case BM_SMM: /* check for a SMM entry */
SMMGL1Init(gl);
break;
}
gl++;
}
}
/* Set up GLPCI settings for reads/write into memory.
*
* R0: 0-640KB,
* R1: 1MB - Top of System Memory
* R2: SMM Memory
* R3: Framebuffer? - not set up yet
* R4: ??
*/
static void GLPCIInit(void)
{
struct gliutable *gl = 0;
int i;
msr_t msr;
int msrnum;
/* R0 - GLPCI settings for Conventional Memory space. */
msr.hi = (0x09F000 >> 12) << GLPCI_RC_UPPER_TOP_SHIFT; /* 640 */
msr.lo = 0; /* 0 */
msr.lo |= GLPCI_RC_LOWER_EN_SET + GLPCI_RC_LOWER_PF_SET + GLPCI_RC_LOWER_WC_SET;
msrnum = GLPCI_RC0;
wrmsr(msrnum, msr);
/* R1 - GLPCI settings for SysMem space. */
/* Get systop from GLIU0 SYSTOP Descriptor */
for (i = 0; gliu0table[i].desc_name != GL_END; i++) {
if (gliu0table[i].desc_type == R_SYSMEM) {
gl = &gliu0table[i];
break;
}
}
if (gl) {
unsigned long pah, pal;
msrnum = gl->desc_name;
msr = rdmsr(msrnum);
/* example R_SYSMEM value: 20:00:00:0f:fb:f0:01:00
* translates to a base of 0x00100000 and top of 0xffbf0000
* base of 1M and top of around 256M
*/
/* we have to create a page-aligned (4KB page) address for base and top
* so we need a high page aligned addresss (pah) and low page aligned address (pal)
* pah is from msr.hi << 12 | msr.low >> 20. pal is msr.lo << 12
*/
pah = ((msr.hi & 0xff) << 12) | ((msr.lo >> 20) & 0xfff);
/* we have the page address. Now make it a page-aligned address */
pah <<= 12;
pal = msr.lo << 12;
msr.hi = pah;
msr.lo = pal;
msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET | GLPCI_RC_LOWER_WC_SET;
printk(BIOS_DEBUG, "GLPCI R1: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
msrnum = GLPCI_RC1;
wrmsr(msrnum, msr);
}
/* R2 - GLPCI settings for SMM space. */
msr.hi = ((SMM_OFFSET + (SMM_SIZE * 1024 - 1)) >> 12) << GLPCI_RC_UPPER_TOP_SHIFT;
msr.lo = (SMM_OFFSET >> 12) << GLPCI_RC_LOWER_BASE_SHIFT;
msr.lo |= GLPCI_RC_LOWER_EN_SET | GLPCI_RC_LOWER_PF_SET;
printk(BIOS_DEBUG, "GLPCI R2: system msr.lo 0x%08x msr.hi 0x%08x\n", msr.lo, msr.hi);
msrnum = GLPCI_RC2;
wrmsr(msrnum, msr);
/* this is done elsewhere already, but it does no harm to do it more than once */
/* write serialize memory hole to PCI. Need to unWS when something is shadowed regardless of cachablility. */
msr.lo = 0x021212121; /* cache disabled and write serialized */
msr.hi = 0x021212121; /* cache disabled and write serialized */
msrnum = CPU_RCONF_A0_BF;
wrmsr(msrnum, msr);
msrnum = CPU_RCONF_C0_DF;
wrmsr(msrnum, msr);
msrnum = CPU_RCONF_E0_FF;
wrmsr(msrnum, msr);
/* Set Non-Cacheable Read Only for NorthBound Transactions to Memory. The Enable bit is handled in the Shadow setup. */
msrnum = GLPCI_A0_BF;
msr.hi = 0x35353535;
msr.lo = 0x35353535;
wrmsr(msrnum, msr);
msrnum = GLPCI_C0_DF;
msr.hi = 0x35353535;
msr.lo = 0x35353535;
wrmsr(msrnum, msr);
msrnum = GLPCI_E0_FF;
msr.hi = 0x35353535;
msr.lo = 0x35353535;
wrmsr(msrnum, msr);
/* Set WSREQ */
msrnum = CPU_DM_CONFIG0;
msr = rdmsr(msrnum);
msr.hi &= ~(7 << DM_CONFIG0_UPPER_WSREQ_SHIFT);
msr.hi |= 2 << DM_CONFIG0_UPPER_WSREQ_SHIFT ; /* reduce to 1 for safe mode. */
wrmsr(msrnum, msr);
/* we are ignoring the 5530 case for now, and perhaps forever. */
/* 553X NB Init */
/* Arbiter setup */
msrnum = GLPCI_ARB;
msr = rdmsr(msrnum);
msr.hi |= GLPCI_ARB_UPPER_PRE0_SET | GLPCI_ARB_UPPER_PRE1_SET;
msr.lo |= GLPCI_ARB_LOWER_IIE_SET;
wrmsr(msrnum, msr);
msrnum = GLPCI_CTRL;
msr = rdmsr(msrnum);
msr.lo |= GLPCI_CTRL_LOWER_ME_SET | GLPCI_CTRL_LOWER_OWC_SET | GLPCI_CTRL_LOWER_PCD_SET; /* (Out will be disabled in CPUBUG649 for < 2.0 parts .) */
msr.lo |= GLPCI_CTRL_LOWER_LDE_SET;
msr.lo &= ~(0x03 << GLPCI_CTRL_LOWER_IRFC_SHIFT);
msr.lo |= 0x02 << GLPCI_CTRL_LOWER_IRFC_SHIFT;
msr.lo &= ~(0x07 << GLPCI_CTRL_LOWER_IRFT_SHIFT);
msr.lo |= 0x06 << GLPCI_CTRL_LOWER_IRFT_SHIFT;
msr.hi &= ~(0x0f << GLPCI_CTRL_UPPER_FTH_SHIFT);
msr.hi |= 0x0F << GLPCI_CTRL_UPPER_FTH_SHIFT;
msr.hi &= ~(0x0f << GLPCI_CTRL_UPPER_RTH_SHIFT);
msr.hi |= 0x0F << GLPCI_CTRL_UPPER_RTH_SHIFT;
msr.hi &= ~(0x0f << GLPCI_CTRL_UPPER_SBRTH_SHIFT);
msr.hi |= 0x0F << GLPCI_CTRL_UPPER_SBRTH_SHIFT;
msr.hi &= ~(0x03 << GLPCI_CTRL_UPPER_WTO_SHIFT);
msr.hi |= 0x06 << GLPCI_CTRL_UPPER_WTO_SHIFT;
msr.hi &= ~(0x03 << GLPCI_CTRL_UPPER_ILTO_SHIFT);
msr.hi |= 0x00 << GLPCI_CTRL_UPPER_ILTO_SHIFT;
wrmsr(msrnum, msr);
/* Set GLPCI Latency Timer. */
msrnum = GLPCI_CTRL;
msr = rdmsr(msrnum);
msr.hi |= 0x1F << GLPCI_CTRL_UPPER_LAT_SHIFT; /* Change once 1.x is gone. */
wrmsr(msrnum, msr);
/* GLPCI_SPARE */
msrnum = GLPCI_SPARE;
msr = rdmsr(msrnum);
msr.lo &= ~0x7;
msr.lo |= GLPCI_SPARE_LOWER_AILTO_SET | GLPCI_SPARE_LOWER_PPD_SET | GLPCI_SPARE_LOWER_PPC_SET | GLPCI_SPARE_LOWER_MPC_SET | GLPCI_SPARE_LOWER_NSE_SET | GLPCI_SPARE_LOWER_SUPO_SET;
wrmsr(msrnum, msr);
}
/* Enable Clock Gating. */
static void ClockGatingInit(void)
{
msr_t msr;
struct msrinit *gating = ClockGatingDefault;
int i;
for (i = 0; gating->msrnum != 0xffffffff; i++) {
msr = rdmsr(gating->msrnum);
msr.hi |= gating->msr.hi;
msr.lo |= gating->msr.lo;
wrmsr(gating->msrnum, msr); /* MSR - See the table above */
gating += 1;
}
}
static void GeodeLinkPriority(void)
{
msr_t msr = { 0, 0 };
struct msrinit *prio = GeodeLinkPriorityTable;
int i;
for (i = 0; prio->msrnum != 0xffffffff; i++) {
msr = rdmsr(prio->msrnum);
msr.hi |= prio->msr.hi;
msr.lo &= ~0xfff;
msr.lo |= prio->msr.lo;
wrmsr(prio->msrnum, msr); /* MSR - See the table above */
prio += 1;
}
}
/* Get the GLIU0 shadow register settings.
*
* If the setShadow function is used then all shadow descriptors
* will stay sync'ed.
*/
static uint64_t getShadow(void)
{
msr_t msr = { 0, 0 };
msr = rdmsr(GLIU0_P2D_SC_0);
return (((uint64_t) msr.hi) << 32) | msr.lo;
}
/* Set the cache RConf registers for the memory hole.
*
* Keeps all cache shadow descriptors sync'ed.
* This is part of the PCI lockup solution.
*
* Entry: EDX:EAX is the shadow settings.
*/
static void setShadowRCONF(uint32_t shadowHi, uint32_t shadowLo)
{
/* ok this is whacky bit translation time. */
int bit;
uint8_t shadowByte;
msr_t msr = { 0, 0 };
shadowByte = (uint8_t) (shadowLo >> 16);
/* load up D000 settings in edx. */
for (bit = 8; (bit > 4); bit--) {
msr.hi <<= 8;
msr.hi |= 1; /* cache disable PCI/Shadow memory */
if (shadowByte && (1 << bit))
msr.hi |= 0x20; /* write serialize PCI memory */
}
/* load up C000 settings in eax. */
for (; bit; bit--) {
msr.lo <<= 8;
msr.lo |= 1; /* cache disable PCI/Shadow memory */
if (shadowByte && (1 << bit))
msr.lo |= 0x20; /* write serialize PCI memory */
}
wrmsr(CPU_RCONF_C0_DF, msr);
shadowByte = (uint8_t) (shadowLo >> 24);
/* load up F000 settings in edx. */
for (bit = 8; (bit > 4); bit--) {
msr.hi <<= 8;
msr.hi |= 1; /* cache disable PCI/Shadow memory */
if (shadowByte && (1 << bit))
msr.hi |= 0x20; /* write serialize PCI memory */
}
/* load up E000 settings in eax. */
for (; bit; bit--) {
msr.lo <<= 8;
msr.lo |= 1; /* cache disable PCI/Shadow memory */
if (shadowByte && (1 << bit))
msr.lo |= 0x20; /* write serialize PCI memory */
}
wrmsr(CPU_RCONF_E0_FF, msr);
}
/* Set the GLPCI registers for the memory hole.
* Keeps all cache shadow descriptors sync'ed.
* Entry: EDX:EAX is the shadow settings
*/
static void setShadowGLPCI(uint32_t shadowHi, uint32_t shadowLo)
{
msr_t msr;
/* Set the Enable Register. */
msr = rdmsr(GLPCI_REN);
msr.lo &= 0xFFFF00FF;
msr.lo |= ((shadowLo & 0xFFFF0000) >> 8);
wrmsr(GLPCI_REN, msr);
}
/* Set the GLIU SC register settings. Scans descriptor tables for SC_SHADOW.
* Keeps all shadow descriptors sync'ed.
* Entry: EDX:EAX is the shadow settings
*/
static void setShadow(uint64_t shadowSettings)
{
int i;
msr_t msr;
struct gliutable *pTable;
uint32_t shadowLo, shadowHi;
shadowLo = (uint32_t) shadowSettings;
shadowHi = (uint32_t) (shadowSettings >> 32);
setShadowRCONF(shadowHi, shadowLo);
setShadowGLPCI(shadowHi, shadowLo);
for (i = 0; gliutables[i]; i++) {
for (pTable = gliutables[i]; pTable->desc_type != GL_END; pTable++) {
if (pTable->desc_type == SC_SHADOW) {
msr = rdmsr(pTable->desc_name);
msr.lo = (uint32_t) shadowSettings;
msr.hi &= 0xFFFF0000; /* maintain PDID in upper EDX */
msr.hi |= ((uint32_t) (shadowSettings >> 32)) & 0x0000FFFF;
wrmsr(pTable->desc_name, msr); /* MSR - See the table above */
}
}
}
}
static void rom_shadow_settings(void)
{
uint64_t shadowSettings = getShadow();
shadowSettings &= (uint64_t) 0xFFFF00000000FFFFULL; /* Disable read & writes */
shadowSettings |= (uint64_t) 0x0000FFFFFFFF0000ULL; /* Enable reads for C0000-FFFFF */
setShadow(shadowSettings);
}
/* Set up RCONF_DEFAULT and any other RCONF registers needed.
*
* DEVRC_RCONF_DEFAULT:
* ROMRC(63:56) = 04h ; write protect ROMBASE
* ROMBASE(36:55) = 0FFFC0h ; Top of PCI/bottom of ROM chipselect area
* DEVRC(35:28) = 39h ; cache disabled in PCI memory + WS bit on + Write Combine + write burst.
* SYSTOP(27:8) = top of system memory
* SYSRC(7:0) = 00h ; writeback, can set to 08h to make writethrough
*/
#define SYSMEM_RCONF_WRITETHROUGH 8
#define DEVRC_RCONF_DEFAULT 0x21ul
#define ROMBASE_RCONF_DEFAULT 0xFFFC0000
#define ROMRC_RCONF_DEFAULT 0x25
static void enable_L_cache(void)
{
struct gliutable *gl = 0;
int i;
msr_t msr;
uint8_t SysMemCacheProp;
/* Locate SYSMEM entry in GLIU0table */
for (i = 0; gliu0table[i].desc_name != GL_END; i++) {
if (gliu0table[i].desc_type == R_SYSMEM) {
gl = &gliu0table[i];
break;
}
}
if (gl == 0) {
post_code(0xCE); /* POST_RCONFInitError */
while (1);
}
/* sysdescfound: */
msr = rdmsr(gl->desc_name);
/* 20 bit address - The bottom 12 bits go into bits 20-31 in eax, the
* top 8 bits go into 0-7 of edx.
*/
msr.lo = (msr.lo & 0xFFFFFF00) | (msr.hi & 0xFF);
msr.lo = ((msr.lo << 12) | (msr.lo >> 20)) & 0x000FFFFF;
msr.lo <<= RCONF_DEFAULT_LOWER_SYSTOP_SHIFT; /* 8 */
/* Set Default SYSMEM region properties */
msr.lo &= ~SYSMEM_RCONF_WRITETHROUGH; /* NOT writethrough == writeback 8 (or ~8) */
/* Set PCI space cache properties */
msr.hi = (DEVRC_RCONF_DEFAULT >> 4); /* setting is split betwwen hi and lo... */
msr.lo |= (DEVRC_RCONF_DEFAULT << 28);
/* Set the ROMBASE. This is usually FFFC0000h */
msr.hi |= (ROMBASE_RCONF_DEFAULT >> 12) << RCONF_DEFAULT_UPPER_ROMBASE_SHIFT;
/* Set ROMBASE cache properties. */
msr.hi |= ((ROMRC_RCONF_DEFAULT >> 8) | (ROMRC_RCONF_DEFAULT << 24));
/* now program RCONF_DEFAULT */
wrmsr(CPU_RCONF_DEFAULT, msr);
printk(BIOS_DEBUG, "CPU_RCONF_DEFAULT (1808): 0x%08X:0x%08X\n", msr.hi, msr.lo);
/* RCONF_BYPASS: Cache tablewalk properties and SMM header access properties. */
/* Set to match system memory cache properties. */
msr = rdmsr(CPU_RCONF_DEFAULT);
SysMemCacheProp = (uint8_t) (msr.lo & 0xFF);
msr = rdmsr(CPU_RCONF_BYPASS);
msr.lo = (msr.lo & 0xFFFF0000) | (SysMemCacheProp << 8) | SysMemCacheProp;
wrmsr(CPU_RCONF_BYPASS, msr);
printk(BIOS_DEBUG, "CPU_RCONF_BYPASS (180A): 0x%08x : 0x%08x\n", msr.hi, msr.lo);
}
static void setup_gx2_cache(void)
{
msr_t msr;
enable_L_cache();
/* Make sure all INVD instructions are treated as WBINVD. We do this
* because we've found some programs which require this behavior.
*/
msr = rdmsr(CPU_DM_CONFIG0);
msr.lo |= DM_CONFIG0_LOWER_WBINVD_SET;
wrmsr(CPU_DM_CONFIG0, msr);
x86_enable_cache();
wbinvd();
}
uint32_t get_systop(void)
{
struct gliutable *gl = 0;
uint32_t systop;
msr_t msr;
int i;
for (i = 0; gliu0table[i].desc_name != GL_END; i++) {
if (gliu0table[i].desc_type == R_SYSMEM) {
gl = &gliu0table[i];
break;
}
}
if (gl) {
msr = rdmsr(gl->desc_name);
systop = ((msr.hi & 0xFF) << 24) | ((msr.lo & 0xFFF00000) >> 8);
systop += 0x1000; /* 4K */
} else {
systop =
((sizeram() - CONFIG_VIDEO_MB) * 1024) - SMM_SIZE - 1024;
}
return systop;
}
/* Core Logic initialization: Host bridge. */
void northbridge_init_early(void)
{
int i;
printk(BIOS_DEBUG, "Enter %s\n", __func__);
for (i = 0; gliutables[i]; i++)
GLIUInit(gliutables[i]);
/* Now that the descriptor to memory is set up. */
/* The memory controller needs one read to synch its lines before it can be used. */
read32(zeroptr);
GeodeLinkPriority();
setup_gx2_cache();
rom_shadow_settings();
GLPCIInit();
ClockGatingInit();
__asm__ __volatile__("FINIT\n");
printk(BIOS_DEBUG, "Exit %s\n", __func__);
}

195
src/northbridge/amd/gx2/pll_reset.c
View File

@@ -1,195 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
* Copyright (C) 2010 Nils Jacobs
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <cpu/x86/tsc.h>
#define CLOCK_TICK_RATE 1193180U /* Underlying HZ */
#define CALIBRATE_INTERVAL ((20*CLOCK_TICK_RATE)/1000) /* 20ms */
#define CALIBRATE_DIVISOR (20*1000) /* 20ms / 20000 == 1usec */
/* spll_raw_clk = SYSREF * FbDIV,
* GLIU Clock = spll_raw_clk / MDIV
* CPU Clock = spll_raw_clk / VDIV
*/
/* table for Feedback divisor to FbDiv register value */
static const unsigned char plldiv2fbdiv[] = {
0, 0, 0, 0, 0, 0, 15, 7, 3, 1, 0, 32, 16, 40, 20, 42, /* pll div 0 - 15 */
21, 10, 37, 50, 25, 12, 38, 19, 9, 4, 34, 17, 8, 36, 18, 41, /* pll div 16 - 31 */
52, 26, 45, 54, 27, 13, 6, 35, 49, 56, 28, 46, 23, 11, 05, 02, /* pll div 32 - 47 */
33, 48, 24, 44, 22, 43, 53, 58, 29, 14, 39, 51, 57, 60, 30, 47, /* pll div 48 - 63 */
};
/* table for FbDiv register value to Feedback divisor */
static const unsigned char fbdiv2plldiv[] = {
10, 9, 47, 8, 25, 46, 38, 7, 28, 24, 17, 45, 21, 37, 57, 6,
12, 27, 30, 23, 14, 16, 52, 44, 50, 20, 33, 36, 42, 56, 0, 0,
11, 48, 26, 39, 29, 18, 22, 58, 13, 31, 15, 53, 51, 34, 43, 0,
49, 40, 19, 59, 32, 54, 35, 0, 41, 60, 55, 0, 61, 0, 0, 0
};
/* FbDIV VDIV MDIV CPU/GeodeLink */
/* 12 2 3 200/133 */
/* 16 2 3 266/177 */
/* 18 2 3 300/200 */
/* 20 2 3 333/222 */
/* 22 2 3 366/244 */
/* 24 2 3 400/266 */
/* 26 2 3 433/289 */
/* PLLCHECK_COMPLETED is the "we've already done this" flag */
#define PLLCHECK_COMPLETED (1 << RSTPLL_LOWER_SWFLAGS_SHIFT)
#ifndef RSTPPL_LOWER_BYPASS_SET
#define RSTPPL_LOWER_BYPASS_SET (1 << GLCP_SYS_RSTPLL_BYPASS)
#endif // RSTPPL_LOWER_BYPASS_SET
#define DEFAULT_MDIV 3
#define DEFAULT_VDIV 2
static void pll_reset(void)
{
msr_t msrGlcpSysRstpll;
unsigned MDIV_VDIV_FBDIV;
unsigned SyncBits; /* store the sync bits in up ebx */
unsigned DEFAULT_FBDIV;
if (CONFIG_GX2_PROCESSOR_MHZ == 400) {
DEFAULT_FBDIV = 24;
} else if (CONFIG_GX2_PROCESSOR_MHZ == 366) {
DEFAULT_FBDIV = 22;
} else if (CONFIG_GX2_PROCESSOR_MHZ == 300) {
DEFAULT_FBDIV = 18;
} else {
post_code(POST_PLL_CPU_VER_FAIL);
die("Unsupported GX2_PROCESSOR_MHZ setting!\n");
}
/* clear the Bypass bit */
/* If the straps say we are in bypass and the syspll is not AND there are no software */
/* bits set then FS2 or something set up the PLL and we should not change it. */
msrGlcpSysRstpll = rdmsr(GLCP_SYS_RSTPLL);
msrGlcpSysRstpll.lo &= ~RSTPPL_LOWER_BYPASS_SET;
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
/* If the "we've already been here" flag is set, don't reconfigure the pll */
if (!(msrGlcpSysRstpll.lo & PLLCHECK_COMPLETED))
{ /* we haven't configured the PLL; do it now */
/* Store PCI33(0)/66(1), SDR(0)/DDR(1), and CRT(0)/TFT(1) in upper esi to get to the */
/* correct Strap Table. */
post_code(POST_PLL_INIT);
/* configure for DDR */
msrGlcpSysRstpll.lo &= ~(1 << RSTPPL_LOWER_SDRMODE_SHIFT);
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
/* Use Manual settings */
/* UseManual: */
post_code(POST_PLL_MANUAL);
/* DIV settings manually entered. */
/* ax = VDIV, upper eax = MDIV, upper ecx = FbDIV */
/* use gs and fs since we don't need them. */
/* ProgramClocks: */
/* ax = VDIV, upper eax = MDIV, upper ecx = FbDIV */
/* move everything into ebx */
/* VDIV */
MDIV_VDIV_FBDIV = ((DEFAULT_VDIV - 2) << RSTPLL_UPPER_VDIV_SHIFT);
/* MDIV */
MDIV_VDIV_FBDIV |= ((DEFAULT_MDIV - 2) << RSTPLL_UPPER_MDIV_SHIFT);
/* FbDIV */
MDIV_VDIV_FBDIV |= (plldiv2fbdiv[DEFAULT_FBDIV] << RSTPLL_UPPER_FBDIV_SHIFT);
/* write GLCP_SYS_RSTPPL (GLCP reg 0x14) with clock values */
msrGlcpSysRstpll.lo &= ~(1 << RSTPPL_LOWER_SDRMODE_SHIFT);
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
msrGlcpSysRstpll.hi = MDIV_VDIV_FBDIV;
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
/* Set Reset, LockWait, and SW flag */
/* DoReset: */
/* CheckSemiSync proc */
/* Check for Semi-Sync in GeodeLink and CPU. */
/* We need to do this here since the strap settings don't account for these bits. */
SyncBits = 0; /* store the sync bits in up ebx */
/* Check for Bypass mode. */
if (msrGlcpSysRstpll.lo & RSTPPL_LOWER_BYPASS_SET)
{
/* If we are in BYPASS PCI may or may not be sync'd but CPU and GeodeLink will. */
SyncBits |= RSTPPL_LOWER_CPU_SEMI_SYNC_SET;
}
else
{
/* CheckPCIsync: */
/* If FBdiv/Mdiv is evenly divisible then set the PCI semi-sync. FB is always greater */
/* look up the real divider... if we get a 0 we have serious problems */
if (!(fbdiv2plldiv[((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_FBDIV_SHIFT) & 0x3f)] %
(((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_MDIV_SHIFT) & 0x0F) + 2)))
{
SyncBits |= RSTPPL_LOWER_PCI_SEMI_SYNC_SET;
}
/* CheckCPUSync: */
/* If Vdiv/Mdiv is evenly divisible then set the CPU semi-sync. */
/* CPU is always greater or equal. */
if (!((((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_MDIV_SHIFT) & 0x07) + 2) %
(((msrGlcpSysRstpll.hi >> RSTPLL_UPPER_VDIV_SHIFT) & 0x0F) + 2)))
{
SyncBits |= RSTPPL_LOWER_CPU_SEMI_SYNC_SET;
}
}
/* SetSync: */
msrGlcpSysRstpll.lo &= ~(RSTPPL_LOWER_PCI_SEMI_SYNC_SET | RSTPPL_LOWER_CPU_SEMI_SYNC_SET);
msrGlcpSysRstpll.lo |= SyncBits;
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
/* CheckSemiSync endp */
/* now we do the reset */
/* Set hold count to 99 (063h) */
msrGlcpSysRstpll.lo &= ~(0x0FF << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
msrGlcpSysRstpll.lo |= (0x0DE << RSTPPL_LOWER_HOLD_COUNT_SHIFT);
msrGlcpSysRstpll.lo |= PLLCHECK_COMPLETED; // Say we are done
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
/* Don't want to use LOCKWAIT */
msrGlcpSysRstpll.lo |= (RSTPPL_LOWER_PLL_RESET_SET + RSTPPL_LOWER_PD_SET);
msrGlcpSysRstpll.lo |= RSTPPL_LOWER_CHIP_RESET_SET;
wrmsr(GLCP_SYS_RSTPLL, msrGlcpSysRstpll);
/* You should never get here..... The chip has reset. */
post_code(POST_PLL_RESET_FAIL);
die("CONFIGURING PLL FAILURE\n");
} /* we haven't configured the PLL; do it now */
}
static unsigned int GeodeLinkSpeed(void)
{
unsigned geodelinkspeed;
geodelinkspeed = ((CONFIG_GX2_PROCESSOR_MHZ * DEFAULT_VDIV) / DEFAULT_MDIV);
return (geodelinkspeed);
}

606
src/northbridge/amd/gx2/raminit.c
View File

@@ -1,606 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2007 Advanced Micro Devices, Inc.
* Copyright (C) 2010 Nils Jacobs
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License version 2 as
* published by the Free Software Foundation.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <cpu/amd/gx2def.h>
#include <spd.h>
#include <stddef.h>
static const unsigned char NumColAddr[] = {
0x00, 0x10, 0x11, 0x00, 0x00, 0x00, 0x00, 0x07,
0x08, 0x09, 0x0A, 0x0B, 0x0C, 0x0D, 0x0E, 0x0F,
};
static void __attribute__((noreturn)) hcf(void)
{
printk(BIOS_EMERG, "DIE\n");
/* this guarantees we flush the UART fifos (if any) and also
* ensures that things, in general, keep going so no debug output
* is lost
*/
while (1)
printk(BIOS_EMERG, (0));
}
static void auto_size_dimm(unsigned int dimm)
{
uint32_t dimm_setting;
uint16_t dimm_size;
uint8_t spd_byte;
msr_t msr;
dimm_setting = 0;
printk(BIOS_DEBUG, "Check present\n");
/* Check that we have a dimm */
if (spd_read_byte(dimm, SPD_MEMORY_TYPE) == 0xFF) {
return;
}
printk(BIOS_DEBUG, "MODBANKS\n");
/* Field: Module Banks per DIMM */
/* EEPROM byte usage: (5) Number of DIMM Banks */
spd_byte = spd_read_byte(dimm, SPD_NUM_DIMM_BANKS);
if ((MIN_MOD_BANKS > spd_byte) || (spd_byte > MAX_MOD_BANKS)) {
printk(BIOS_EMERG, "Number of module banks not compatible\n");
post_code(ERROR_BANK_SET);
hcf();
}
dimm_setting |= (spd_byte >> 1) << CF07_UPPER_D0_MB_SHIFT;
printk(BIOS_DEBUG, "FIELDBANKS\n");
/* Field: Banks per SDRAM device */
/* EEPROM byte usage: (17) Number of Banks on SDRAM Device */
spd_byte = spd_read_byte(dimm, SPD_NUM_BANKS_PER_SDRAM);
if ((MIN_DEV_BANKS > spd_byte) || (spd_byte > MAX_DEV_BANKS)) {
printk(BIOS_EMERG, "Number of device banks not compatible\n");
post_code(ERROR_BANK_SET);
hcf();
}
dimm_setting |= (spd_byte >> 2) << CF07_UPPER_D0_CB_SHIFT;
printk(BIOS_DEBUG, "SPDNUMROWS\n");
/* Field: DIMM size
* EEPROM byte usage:
* (3) Number of Row Addresses
* (4) Number of Column Addresses
* (5) Number of DIMM Banks
* (31) Module Bank Density
* Size = Module Density * Module Banks
*/
if ((spd_read_byte(dimm, SPD_NUM_ROWS) & 0xF0)
|| (spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF0)) {
printk(BIOS_EMERG, "Asymmetric DIMM not compatible\n");
post_code(ERROR_UNSUPPORTED_DIMM);
hcf();
}
printk(BIOS_DEBUG, "SPDBANKDENSITY\n");
dimm_size = spd_read_byte(dimm, SPD_BANK_DENSITY);
printk(BIOS_DEBUG, "DIMMSIZE\n");
dimm_size |= (dimm_size << 8); /* align so 1GB(bit0) is bit 8, this is a little weird to get gcc to not optimize this out */
dimm_size &= 0x01FC; /* and off 2GB DIMM size : not supported and the 1GB size we just moved up to bit 8 as well as all the extra on top */
/* Module Density * Module Banks */
dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1; /* shift to multiply by # DIMM banks */
printk(BIOS_DEBUG, "BEFORT CTZ\n");
dimm_size = __builtin_ctz(dimm_size);
printk(BIOS_DEBUG, "TEST DIMM SIZE > 7\n");
if (dimm_size > 7) { /* 7 is 512MB only support 512MB per DIMM */
printk(BIOS_EMERG, "Only support up to 512MB per DIMM\n");
post_code(ERROR_DENSITY_DIMM);
hcf();
}
dimm_setting |= dimm_size << CF07_UPPER_D0_SZ_SHIFT;
printk(BIOS_DEBUG, "PAGESIZE\n");
/*
* Field: PAGE size
* EEPROM byte usage: (4) Number of Column Addresses
* PageSize = 2^# Column Addresses * Data width in bytes
* (should be 8bytes for a normal DIMM)
*
* But this really works by magic.
* If ma[11:0] is the memory address pins, and pa[13:0] is the physical column
* address that MC generates, here is how the MC assigns the pa onto the
* ma pins:
*
* ma 11 10 09 08 07 06 05 04 03 02 01 00
* ---------------------------------------
* pa 09 08 07 06 05 04 03 (7 col addr bits = 1K page size)
* pa 10 09 08 07 06 05 04 03 (8 col addr bits = 2K page size)
* pa 11 10 09 08 07 06 05 04 03 (9 col addr bits = 4K page size)
* pa 12 11 10 09 08 07 06 05 04 03 (10 col addr bits = 8K page size)
* pa 13 AP 12 11 10 09 08 07 06 05 04 03 (11 col addr bits = 16K page size)
*
* (AP = autoprecharge bit)
*
* Remember that pa[2:0] are zeroed out since it's a 64-bit data bus (8 bytes),
* so lower 3 address bits are dont_cares. So from the table above,
* it's easier to see what the old code is doing: if for example,
* #col_addr_bits = 7(06h), it adds 3 to get 10, then does 2^10 = 1K.
*/
spd_byte = NumColAddr[spd_read_byte(dimm, SPD_NUM_COLUMNS) & 0xF];
printk(BIOS_DEBUG, "MAXCOLADDR\n");
if (spd_byte > MAX_COL_ADDR) {
printk(BIOS_EMERG, "DIMM page size not compatible\n");
post_code(ERROR_SET_PAGE);
hcf();
}
printk(BIOS_DEBUG, ">11address test\n");
spd_byte -= 7;
if (spd_byte > 4) { /* if the value is above 4 it means > 11 col address lines */
spd_byte = 7; /* which means > 16k so set to disabled */
}
dimm_setting |= spd_byte << CF07_UPPER_D0_PSZ_SHIFT; /* 0 = 1k, 1 = 2k, 2 = 4k, etc */
printk(BIOS_DEBUG, "RDMSR CF07\n");
msr = rdmsr(MC_CF07_DATA);
printk(BIOS_DEBUG, "WRMSR CF07\n");
if (dimm == DIMM0) {
msr.hi &= 0xFFFF0000;
msr.hi |= dimm_setting;
} else {
msr.hi &= 0x0000FFFF;
msr.hi |= dimm_setting << 16;
}
wrmsr(MC_CF07_DATA, msr);
printk(BIOS_DEBUG, "ALL DONE\n");
}
static void checkDDRMax(void)
{
uint8_t spd_byte0, spd_byte1;
uint16_t speed;
/* PC133 identifier */
spd_byte0 = spd_read_byte(DIMM0, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
if (spd_byte0 == 0xFF) {
spd_byte0 = 0;
}
spd_byte1 = spd_read_byte(DIMM1, SPD_MIN_CYCLE_TIME_AT_CAS_MAX);
if (spd_byte1 == 0xFF) {
spd_byte1 = 0;
}
/* Use the slowest DIMM */
if (spd_byte0 < spd_byte1) {
spd_byte0 = spd_byte1;
}
/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
speed = 20000 / (((spd_byte0 >> 4) * 10) + (spd_byte0 & 0x0F));
/* current speed > max speed? */
if (GeodeLinkSpeed() > speed) {
printk(BIOS_EMERG, "DIMM overclocked. Check GeodeLink Speed\n");
post_code(POST_PLL_MEM_FAIL);
hcf();
}
}
const uint16_t REF_RATE[] = { 15, 3, 7, 31, 62, 125 }; /* ns */
static void set_refresh_rate(void)
{
uint8_t spd_byte0, spd_byte1;
uint16_t rate0, rate1;
msr_t msr;
spd_byte0 = spd_read_byte(DIMM0, SPD_REFRESH);
spd_byte0 &= 0xF;
if (spd_byte0 > 5) {
spd_byte0 = 5;
}
rate0 = REF_RATE[spd_byte0];
spd_byte1 = spd_read_byte(DIMM1, SPD_REFRESH);
spd_byte1 &= 0xF;
if (spd_byte1 > 5) {
spd_byte1 = 5;
}
rate1 = REF_RATE[spd_byte1];
/* Use the faster rate (lowest number) */
if (rate0 > rate1) {
rate0 = rate1;
}
msr = rdmsr(MC_CF07_DATA);
msr.lo |= ((rate0 * (GeodeLinkSpeed() / 2)) / 16)
<< CF07_LOWER_REF_INT_SHIFT;
wrmsr(MC_CF07_DATA, msr);
}
const uint8_t CASDDR[] = { 5, 5, 2, 6, 0 }; /* 1(1.5), 1.5, 2, 2.5, 0 */
static u8 getcasmap(u32 dimm, u16 glspeed)
{
u16 dimm_speed;
u8 spd_byte, casmap, casmap_shift = 0;
/************************** DIMM0 **********************************/
casmap = spd_read_byte(dimm, SPD_ACCEPTABLE_CAS_LATENCIES);
if (casmap != 0xFF) {
/* IF -.5 timing is supported, check -.5 timing > GeodeLink */
spd_byte = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_2ND);
if (spd_byte != 0) {
/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));
if (dimm_speed >= glspeed) {
casmap_shift = 1; /* -.5 is a shift of 1 */
/* IF -1 timing is supported, check -1 timing > GeodeLink */
spd_byte = spd_read_byte(dimm, SPD_SDRAM_CYCLE_TIME_3RD);
if (spd_byte != 0) {
/* Turn SPD ns time into MHZ. Check what the asm does to this math. */
dimm_speed = 20000 / (((spd_byte >> 4) * 10) + (spd_byte & 0x0F));
if (dimm_speed >= glspeed) {
casmap_shift = 2; /* -1 is a shift of 2 */
}
} /* SPD_SDRAM_CYCLE_TIME_3RD (-1) !=0 */
} else {
casmap_shift = 0;
}
} /* SPD_SDRAM_CYCLE_TIME_2ND (-.5) !=0 */
/* set the casmap based on the shift to limit possible CAS settings */
spd_byte = 31 - __builtin_clz((uint32_t) casmap);
/* just want bits in the lower byte since we have to cast to a 32 */
casmap &= 0xFF << (spd_byte - casmap_shift);
} else { /* No DIMM */
casmap = 0;
}
return casmap;
}
static void setCAS(void)
{
/*
* setCAS
* EEPROM byte usage: (18) SDRAM device attributes - CAS latency
* EEPROM byte usage: (23) SDRAM Minimum Clock Cycle Time @ CLX -.5
* EEPROM byte usage: (25) SDRAM Minimum Clock Cycle Time @ CLX -1
*
* The CAS setting is based on the information provided in each DIMMs SPD.
* The speed at which a DIMM can run is described relative to the slowest
* CAS the DIMM supports. Each speed for the relative CAS settings is
* checked that it is within the GeodeLink speed. If it isn't within the GeodeLink
* speed, the CAS setting is removed from the list of good settings for
* the DIMM. This is done for both DIMMs and the lists are compared to
* find the lowest common CAS latency setting. If there are no CAS settings
* in common we out a ERROR_DIFF_DIMMS (78h) to port 80h and halt.
*
* Entry:
* Exit: Set fastest CAS Latency based on GeodeLink speed and SPD information.
* Destroys: We really use everything !
*/
uint16_t glspeed;
uint8_t spd_byte, casmap0, casmap1;
msr_t msr;
glspeed = GeodeLinkSpeed();
casmap0 = getcasmap(DIMM0, glspeed);
casmap1 = getcasmap(DIMM1, glspeed);
/* CAS_LAT MAP COMPARE */
if (casmap0 == 0) {
spd_byte = CASDDR[__builtin_ctz(casmap1)];
} else if (casmap1 == 0) {
spd_byte = CASDDR[__builtin_ctz(casmap0)];
} else if ((casmap0 &= casmap1)) {
spd_byte = CASDDR[__builtin_ctz(casmap0)];
} else {
printk(BIOS_EMERG, "DIMM CAS Latencies not compatible\n");
post_code(ERROR_DIFF_DIMMS);
hcf();
}
msr = rdmsr(MC_CF8F_DATA);
msr.lo &= ~(7 << CF8F_LOWER_CAS_LAT_SHIFT);
msr.lo |= spd_byte << CF8F_LOWER_CAS_LAT_SHIFT;
wrmsr(MC_CF8F_DATA, msr);
}
static void set_latencies(void)
{
uint32_t memspeed, dimm_setting;
uint8_t spd_byte0, spd_byte1;
msr_t msr;
memspeed = GeodeLinkSpeed() / 2;
dimm_setting = 0;
/* MC_CF8F setup */
/* tRAS */
spd_byte0 = spd_read_byte(DIMM0, SPD_tRAS);
if (spd_byte0 == 0xFF) {
spd_byte0 = 0;
}
spd_byte1 = spd_read_byte(DIMM1, SPD_tRAS);
if (spd_byte1 == 0xFF) {
spd_byte1 = 0;
}
if (spd_byte0 < spd_byte1) {
spd_byte0 = spd_byte1;
}
/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
spd_byte1 = (spd_byte0 * memspeed) / 1000;
if (((spd_byte0 * memspeed) % 1000)) {
++spd_byte1;
}
if (spd_byte1 > 6) {
--spd_byte1;
}
dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2PRE_SHIFT;
/* tRP */
spd_byte0 = spd_read_byte(DIMM0, SPD_tRP);
if (spd_byte0 == 0xFF) {
spd_byte0 = 0;
}
spd_byte1 = spd_read_byte(DIMM1, SPD_tRP);
if (spd_byte1 == 0xFF) {
spd_byte1 = 0;
}
if (spd_byte0 < spd_byte1) {
spd_byte0 = spd_byte1;
}
/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
++spd_byte1;
}
dimm_setting |= spd_byte1 << CF8F_LOWER_PRE2ACT_SHIFT;
/* tRCD */
spd_byte0 = spd_read_byte(DIMM0, SPD_tRCD);
if (spd_byte0 == 0xFF) {
spd_byte0 = 0;
}
spd_byte1 = spd_read_byte(DIMM1, SPD_tRCD);
if (spd_byte1 == 0xFF) {
spd_byte1 = 0;
}
if (spd_byte0 < spd_byte1) {
spd_byte0 = spd_byte1;
}
/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
++spd_byte1;
}
dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2CMD_SHIFT;
/* tRRD */
spd_byte0 = spd_read_byte(DIMM0, SPD_tRRD);
if (spd_byte0 == 0xFF) {
spd_byte0 = 0;
}
spd_byte1 = spd_read_byte(DIMM1, SPD_tRRD);
if (spd_byte1 == 0xFF) {
spd_byte1 = 0;
}
if (spd_byte0 < spd_byte1) {
spd_byte0 = spd_byte1;
}
/* (ns/(1/MHz) = (us*MHZ)/1000 = clocks/1000 = clocks) */
spd_byte1 = ((spd_byte0 >> 2) * memspeed) / 1000;
if ((((spd_byte0 >> 2) * memspeed) % 1000)) {
++spd_byte1;
}
dimm_setting |= spd_byte1 << CF8F_LOWER_ACT2ACT_SHIFT;
/* tRC = tRP + tRAS */
dimm_setting |= (((dimm_setting >> CF8F_LOWER_ACT2PRE_SHIFT) & 0x0F) +
((dimm_setting >> CF8F_LOWER_PRE2ACT_SHIFT) & 0x07))
<< CF8F_LOWER_REF2ACT_SHIFT;
msr = rdmsr(MC_CF8F_DATA);
msr.lo &= 0xF00000FF;
msr.lo |= dimm_setting;
msr.hi |= CF8F_UPPER_REORDER_DIS_SET;
wrmsr(MC_CF8F_DATA, msr);
printk(BIOS_DEBUG, "MSR MC_CF8F_DATA (%08x) value is %08x:%08x\n",
MC_CF8F_DATA, msr.hi, msr.lo);
}
static void set_extended_mode_registers(void)
{
uint8_t spd_byte0, spd_byte1;
msr_t msr;
spd_byte0 = spd_read_byte(DIMM0, SPD_DEVICE_ATTRIBUTES_GENERAL);
if (spd_byte0 == 0xFF) {
spd_byte0 = 0;
}
spd_byte1 = spd_read_byte(DIMM1, SPD_DEVICE_ATTRIBUTES_GENERAL);
if (spd_byte1 == 0xFF) {
spd_byte1 = 0;
}
spd_byte1 &= spd_byte0;
msr = rdmsr(MC_CF07_DATA);
if (spd_byte1 & 1) { /* Drive Strength Control */
msr.lo |= CF07_LOWER_EMR_DRV_SET;
}
if (spd_byte1 & 2) { /* FET Control */
msr.lo |= CF07_LOWER_EMR_QFC_SET;
}
wrmsr(MC_CF07_DATA, msr);
}
static void sdram_set_registers(const struct mem_controller *ctrl)
{
msr_t msr;
uint32_t msrnum;
/* Set Refresh Staggering */
msrnum = MC_CF07_DATA;
msr = rdmsr(msrnum);
msr.lo &= ~0xC0;
msr.lo |= 0x0; /* set refresh to 4SDRAM clocks */
wrmsr(msrnum, msr);
}
static void sdram_set_spd_registers(const struct mem_controller *ctrl)
{
uint8_t spd_byte;
printk(BIOS_DEBUG, "sdram_set_spd_register\n");
post_code(POST_MEM_SETUP); /* post_70h */
spd_byte = spd_read_byte(DIMM0, SPD_MODULE_ATTRIBUTES);
printk(BIOS_DEBUG, "Check DIMM 0\n");
/* Check DIMM is not Register and not Buffered DIMMs. */
if ((spd_byte != 0xFF) && (spd_byte & 3)) {
printk(BIOS_EMERG, "DIMM0 NOT COMPATIBLE\n");
post_code(ERROR_UNSUPPORTED_DIMM);
hcf();
}
printk(BIOS_DEBUG, "Check DIMM 1\n");
spd_byte = spd_read_byte(DIMM1, SPD_MODULE_ATTRIBUTES);
if ((spd_byte != 0xFF) && (spd_byte & 3)) {
printk(BIOS_EMERG, "DIMM1 NOT COMPATIBLE\n");
post_code(ERROR_UNSUPPORTED_DIMM);
hcf();
}
post_code(POST_MEM_SETUP2); /* post_72h */
printk(BIOS_DEBUG, "Check DDR MAX\n");
/* Check that the memory is not overclocked. */
checkDDRMax();
/* Size the DIMMS */
post_code(POST_MEM_SETUP3); /* post_73h */
printk(BIOS_DEBUG, "AUTOSIZE DIMM 0\n");
auto_size_dimm(DIMM0);
post_code(POST_MEM_SETUP4); /* post_74h */
printk(BIOS_DEBUG, "AUTOSIZE DIMM 1\n");
auto_size_dimm(DIMM1);
/* Set CAS latency */
printk(BIOS_DEBUG, "set cas latency\n");
post_code(POST_MEM_SETUP5); /* post_75h */
setCAS();
/* Set all the other latencies here (tRAS, tRP....) */
printk(BIOS_DEBUG, "set all latency\n");
set_latencies();
/* Set Extended Mode Registers */
printk(BIOS_DEBUG, "set emrs\n");
set_extended_mode_registers();
printk(BIOS_DEBUG, "set ref rate\n");
/* Set Memory Refresh Rate */
set_refresh_rate();
}
/* Section 6.1.3, LX processor databooks, BIOS Initialization Sequence
* Section 4.1.4, GX/CS5535 GeodeROM Porting guide */
static void sdram_enable(int controllers, const struct mem_controller *ctrl)
{
int i;
msr_t msr;
/* 2. clock gating for PMode */
msr = rdmsr(MC_GLD_MSR_PM);
msr.lo &= ~0x04;
msr.lo |= 0x01;
wrmsr(MC_GLD_MSR_PM, msr);
/* undocmented bits in GX, in LX there are
* 8 bits in PM1_UP_DLY */
msr = rdmsr(MC_CF1017_DATA);
msr.lo = 0x0101;
wrmsr(MC_CF1017_DATA, msr);
printk(BIOS_DEBUG, "sdram_enable step 2\n");
/* 3. release CKE mask to enable CKE */
msr = rdmsr(MC_CFCLK_DBUG);
msr.lo &= ~(0x03 << 8);
wrmsr(MC_CFCLK_DBUG, msr);
printk(BIOS_DEBUG, "sdram_enable step 3\n");
/* 4. set and clear REF_TST 16 times, more shouldn't hurt
* why this is before EMRS and MRS ? */
for (i = 0; i < 19; i++) {
msr = rdmsr(MC_CF07_DATA);
msr.lo |= (0x01 << 3);
wrmsr(MC_CF07_DATA, msr);
msr.lo &= ~(0x01 << 3);
wrmsr(MC_CF07_DATA, msr);
}
printk(BIOS_DEBUG, "sdram_enable step 4\n");
/* 6. enable DLL, load Extended Mode Register by set and clear PROG_DRAM */
msr = rdmsr(MC_CF07_DATA);
msr.lo |= ((0x01 << 28) | 0x01);
wrmsr(MC_CF07_DATA, msr);
msr.lo &= ~((0x01 << 28) | 0x01);
wrmsr(MC_CF07_DATA, msr);
printk(BIOS_DEBUG, "sdram_enable step 6\n");
/* 7. Reset DLL, Bit 27 is undocumented in GX datasheet,
* it is documented in LX datasheet */
/* load Mode Register by set and clear PROG_DRAM */
msr = rdmsr(MC_CF07_DATA);
msr.lo |= ((0x01 << 27) | 0x01);
wrmsr(MC_CF07_DATA, msr);
msr.lo &= ~((0x01 << 27) | 0x01);
wrmsr(MC_CF07_DATA, msr);
printk(BIOS_DEBUG, "sdram_enable step 7\n");
/* 8. load Mode Register by set and clear PROG_DRAM */
msr = rdmsr(MC_CF07_DATA);
msr.lo |= 0x01;
wrmsr(MC_CF07_DATA, msr);
msr.lo &= ~0x01;
wrmsr(MC_CF07_DATA, msr);
printk(BIOS_DEBUG, "sdram_enable step 8\n");
/* wait 200 SDCLKs */
for (i = 0; i < 200; i++)
outb(0xaa, 0x80);
/* load RDSYNC */
msr = rdmsr(MC_CF_RDSYNC);
msr.hi = 0x000ff310;
/* the above setting is supposed to be good for "slow" ram. We have found that for
* some dram, at some clock rates, e.g. hynix at 366/244, this will actually
* cause errors. The fix is to just set it to 0x310. Tested on 3 boards
* with 3 different type of dram -- Hynix, PSC, infineon.
* I am leaving this comment here so that at some future time nobody is tempted
* to mess with this setting -- RGM, 9/2006
*/
msr.hi = 0x00000310;
msr.lo = 0x00000000;
wrmsr(MC_CF_RDSYNC, msr);
/* set delay control */
msr = rdmsr(GLCP_DELAY_CONTROLS);
msr.hi = 0x830d415a;
msr.lo = 0x8ea0ad6a;
wrmsr(GLCP_DELAY_CONTROLS, msr);
/* The RAM dll needs a write to lock on so generate a few dummy writes */
/* Note: The descriptor needs to be enabled to point at memory */
for (i = 0; i < 5; i++) {
write32(zeroptr + i, i);
}
printk(BIOS_INFO, "RAM DLL lock\n");
}

12
src/northbridge/amd/gx2/raminit.h
View File

@@ -1,12 +0,0 @@
#ifndef RAMINIT_H
#define RAMINIT_H
#define DIMM_SOCKETS 2
struct mem_controller {
uint16_t channel0[DIMM_SOCKETS];
};
void sdram_initialize(int controllers, const struct mem_controller *ctrl);
#endif /* RAMINIT_H */

2
src/southbridge/amd/cs5535/Kconfig
View File

@@ -1,2 +0,0 @@
config SOUTHBRIDGE_AMD_CS5535
bool

8
src/southbridge/amd/cs5535/Makefile.inc
View File

@@ -1,8 +0,0 @@
ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5535),y)
ramstage-y += cs5535.c
#ramstage-y += pci.c
#ramstage-y += ide.c
ramstage-y += chipsetinit.c
endif

8
src/southbridge/amd/cs5535/chip.h
View File

@@ -1,8 +0,0 @@
#ifndef _SOUTHBRIDGE_AMD_CS5535
#define _SOUTHBRIDGE_AMD_CS5535
struct southbridge_amd_cs5535_config {
int setupflash;
};
#endif /* _SOUTHBRIDGE_AMD_CS5535 */

356
src/southbridge/amd/cs5535/chipsetinit.c
View File

@@ -1,356 +0,0 @@
#include <console/console.h>
#include <arch/io.h>
#include <stdint.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <stdlib.h>
#include <string.h>
#include "chip.h"
#include "northbridge/amd/gx2/northbridge.h"
#include <cpu/amd/gx2def.h>
#include <cpu/x86/msr.h>
#include <cpu/x86/cache.h>
#include "southbridge/amd/cs5535/cs5535.h"
/* the structs in this file only set msr.lo. But ... that may not always be true */
struct msrinit {
unsigned long msrnum;
msr_t msr;
};
/* Master Configuration Register for Bus Masters. */
static struct msrinit SB_MASTER_CONF_TABLE[] = {
{ USB1_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000} }, /* NOTE: Must be 1st entry in table */
{ USB2_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000} },
{ ATA_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00048f000} },
{ AC97_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00008f000} },
{ MDD_SB_GLD_MSR_CONF, {.hi = 0,.lo = 0x00000f000} },
/* GLPCI_SB_GLD_MSR_CONF, 0x0FFFFFFFF*/
/* GLCP_SB_GLD_MSR_CONF, 0x0FFFFFFFF*/
/* GLIU_SB_GLD_MSR_CONF, 0x0*/
{0,{0,0}}
};
/* 5535_A3 Clock Gating*/
static struct msrinit CS5535_CLOCK_GATING_TABLE[] = {
{ USB1_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000005} },
{ USB2_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000005} },
{ GLIU_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000004} },
{ GLPCI_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000005} },
{ GLCP_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000004} },
{ MDD_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x050554111} },
{ ATA_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000005} },
{ AC97_SB_GLD_MSR_PM, {.hi = 0, .lo = 0x000000005} },
{ 0, {.hi = 0, .lo = 0x000000000} }
};
#ifdef UNUSED_CODE
struct acpiinit {
unsigned short ioreg;
unsigned long regdata;
unsigned short iolen;
};
static struct acpiinit acpi_init_table[] = {
{ACPI_BASE+0x00, 0x01000000, 4},
{ACPI_BASE+0x08, 0, 4},
{ACPI_BASE+0x0C, 0, 4},
{ACPI_BASE+0x1C, 0, 4},
{ACPI_BASE+0x18, 0x0FFFFFFFF, 4},
{ACPI_BASE+0x00, 0x0000FFFF, 4},
{PM_SCLK, 0x000000E00, 4},
{PM_SED, 0x000004601, 4},
{PM_SIDD, 0x000008C02, 4},
{PM_WKD, 0x0000000A0, 4},
{PM_WKXD, 0x0000000A0, 4},
{0,0,0}
};
/*****************************************************************************
*
* pmChipsetInit
*
* Program ACPI LBAR and initialize ACPI registers.
*
*****************************************************************************/
static void pmChipsetInit(void)
{
unsigned long val = 0;
unsigned short port;
port = (PMLogic_BASE + 0x010);
val = 0x0E00 ; /* 1ms*/
outl(val, port);
/* PM_WKXD*/
/* Make sure bits[3:0]=0000b to clear the*/
/* saved Sx state*/
port = (PMLogic_BASE + 0x034);
val = 0x0A0 ; /* 5ms*/
outl(val, port);
/* PM_WKD*/
port = (PMLogic_BASE + 0x030);
outl(val, port);
/* PM_SED*/
port = (PMLogic_BASE + 0x014);
val = 0x04601 ; /* 5ms*/
outl(val, port);
/* PM_SIDD*/
port = (PMLogic_BASE + 0x020);
val = 0x08C02 ; /* 10ms*/
outl(val, port);
/* GPIO24 OUT_AUX1 function is the external signal for 5535's
* vsb_working_aux which is de-asserted when 5535 enters Standby (S3 or
* S5) state. On Hawk, GPIO24 controls all voltage rails except Vmem
* and Vstandby. This means GX2 will be fully de-powered if this
* control de-asserts in S3/S5.
*/
/* GPIO24 is setup in preChipsetInit for two reasons
* 1. GPIO24 at reset defaults to disabled, since this signal is
* vsb_work_aux on Hawk it controls the FET's for all voltage
* rails except Vstandby & Vmem. BIOS needs to enable GPIO24 as
* OUT_AUX1 & OUTPUT_EN early so it is driven by 5535.
* 2. Non-PM builds will require GPIO24 enabled for instant-off power
* button
*/
/* GPIO11 OUT_AUX1 function is the external signal for 5535's
* slp_clk_n which is asserted when 5535 enters Sleep(S1) state.
* On Hawk, GPIO11 is connected to control input of external clock
* generator for 14MHz, PCI, USB & LPC clocks.
* Programming of GPIO11 will be done by VSA PM code. During VSA
* Init. BIOS writes PM Core Virtual Register indicating if S1 Clocks
* should be On or Off. This is based on a Setup item. We do not want
* to leave GPIO11 enabled because of a Hawk board problem. With
* GPIO11 enabled in S3, something is back-driving GPIO11 causing it
* to float to 1.6-1.7V.
*/
}
#endif
struct FLASH_DEVICE {
unsigned char fType; /* Flash type: NOR or NAND */
unsigned char fInterface; /* Flash interface: I/O or Memory */
unsigned long fMask; /* Flash size/mask */
};
static struct FLASH_DEVICE FlashInitTable[] = {
{ FLASH_TYPE_NAND, FLASH_IF_MEM, FLASH_MEM_4K }, /* CS0, or Flash Device 0 */
{ FLASH_TYPE_NONE, 0, 0 }, /* CS1, or Flash Device 1 */
{ FLASH_TYPE_NONE, 0, 0 }, /* CS2, or Flash Device 2 */
{ FLASH_TYPE_NONE, 0, 0 }, /* CS3, or Flash Device 3 */
};
#define FlashInitTableLen (ARRAY_SIZE(FlashInitTable))
static uint32_t FlashPort[] = {
MDD_LBAR_FLSH0,
MDD_LBAR_FLSH1,
MDD_LBAR_FLSH2,
MDD_LBAR_FLSH3
};
/***************************************************************************
*
* ChipsetFlashSetup
*
* Flash LBARs need to be setup before VSA init so the PCI BARs have
* correct size info. Call this routine only if flash needs to be
* configured (don't call it if you want IDE).
*
**************************************************************************/
static void ChipsetFlashSetup(void)
{
msr_t msr;
int i;
int numEnabled = 0;
printk(BIOS_DEBUG, "ChipsetFlashSetup++\n");
for (i = 0; i < FlashInitTableLen; i++) {
if (FlashInitTable[i].fType != FLASH_TYPE_NONE) {
printk(BIOS_DEBUG, "Enable CS%d\n", i);
/* we need to configure the memory/IO mask */
msr = rdmsr(FlashPort[i]);
msr.hi = 0; /* start with the "enabled" bit clear */
if (FlashInitTable[i].fType == FLASH_TYPE_NAND)
msr.hi |= 0x00000002;
else
msr.hi &= ~0x00000002;
if (FlashInitTable[i].fInterface == FLASH_IF_MEM)
msr.hi |= 0x00000004;
else
msr.hi &= ~0x00000004;
msr.hi |= FlashInitTable[i].fMask;
printk(BIOS_DEBUG, "WRMSR(0x%08X, %08X_%08X)\n", FlashPort[i], msr.hi, msr.lo);
wrmsr(FlashPort[i], msr);
/* now write-enable the device */
msr = rdmsr(MDD_NORF_CNTRL);
msr.lo |= (1 << i);
printk(BIOS_DEBUG, "WRMSR(0x%08X, %08X_%08X)\n", MDD_NORF_CNTRL, msr.hi, msr.lo);
wrmsr(MDD_NORF_CNTRL, msr);
/* update the number enabled */
numEnabled++;
}
}
/* enable the flash */
if (0 != numEnabled) {
msr = rdmsr(MDD_PIN_OPT);
msr.lo &= ~1; /* PIN_OPT_IDE */
printk(BIOS_DEBUG, "WRMSR(0x%08X, %08X_%08X)\n", MDD_PIN_OPT, msr.hi, msr.lo);
wrmsr(MDD_PIN_OPT, msr);
}
printk(BIOS_DEBUG, "ChipsetFlashSetup--\n");
}
/****************************************************************************
*
* ChipsetGeodeLinkInit
*
* Handle chipset specific GeodeLink settings here.
* Called from GeodeLink init code.
*
****************************************************************************/
static void
ChipsetGeodeLinkInit(void)
{
msr_t msr;
unsigned long msrnum;
unsigned long totalmem;
/* SWASIF for A1 DMA */
/* Set all memory to "just above systop" PCI so DMA will work */
/* check A1 */
msrnum = MSR_SB_GLCP + 0x17;
msr = rdmsr(msrnum);
if ((msr.lo&0xff) == 0x11)
return;
totalmem = (sizeram() << 20) - 1; // highest address
totalmem >>= 12;
totalmem = ~totalmem;
totalmem &= 0xfffff;
msr.lo = totalmem;
msr.hi = 0x20000000; /* Port 1 (PCI) */
msrnum = MSR_SB_GLIU + 0x20;
wrmsr(msrnum, msr);
}
void
chipsetinit(void)
{
device_t dev;
struct southbridge_amd_cs5535_config *sb;
msr_t msr;
struct msrinit *csi;
int i;
unsigned long msrnum;
dev = dev_find_device(PCI_VENDOR_ID_AMD,
PCI_DEVICE_ID_NS_CS5535_ISA, 0);
if (!dev) {
printk(BIOS_ERR, "CS5535 not found.\n");
return;
}
sb = (struct southbridge_amd_cs5535_config *)dev->chip_info;
if (!sb) {
printk(BIOS_ERR, "CS5535 configuration not found.\n");
return;
}
post_code(P80_CHIPSET_INIT);
ChipsetGeodeLinkInit();
#ifdef UNUSED_CODE
/* we hope NEVER to be in coreboot when S3 resumes
if (! IsS3Resume()) */
{
struct acpiinit *aci = acpi_init_table;
while (aci->ioreg){
if (aci->iolen == 2) {
outw(aci->regdata, aci->ioreg);
inw(aci->ioreg);
} else {
outl(aci->regdata, aci->ioreg);
inl(aci->ioreg);
}
}
pmChipsetInit();
}
#endif
/* Setup USB. Need more details. #118.18 */
msrnum = MSR_SB_USB1 + 8;
msr.lo = 0x00012090;
msr.hi = 0;
wrmsr(msrnum, msr);
msrnum = MSR_SB_USB2 + 8;
wrmsr(msrnum, msr);
/* set hd IRQ */
outl (GPIOL_2_SET, GPIOL_INPUT_ENABLE);
outl (GPIOL_2_SET, GPIOL_IN_AUX1_SELECT);
/* Allow IO read and writes during a ATA DMA operation. */
/* This could be done in the HD ROM but do it here for easier debugging. */
msrnum = ATA_SB_GLD_MSR_ERR;
msr = rdmsr(msrnum);
msr.lo &= ~0x100;
wrmsr(msrnum, msr);
/* Enable Post Primary IDE. */
msrnum = GLPCI_SB_CTRL;
msr = rdmsr(msrnum);
msr.lo |= GLPCI_CRTL_PPIDE_SET;
wrmsr(msrnum, msr);
/* Set up Master Configuration Register */
/* If 5536, use same master config settings as 5535, except for OHCI MSRs */
i = 0;
csi = &SB_MASTER_CONF_TABLE[i];
for (; csi->msrnum; csi++){
msr.lo = csi->msr.lo;
msr.hi = csi->msr.hi;
wrmsr(csi->msrnum, msr); // MSR - see table above
}
/* Flash Setup */
printk(BIOS_INFO, "%sDOING ChipsetFlashSetup()!\n",
sb->setupflash ? "" : "NOT ");
if (sb->setupflash)
ChipsetFlashSetup();
/* Set up Hardware Clock Gating */
/* if (getnvram(TOKEN_SB_CLK_GATE) != TVALUE_DISABLE) */
{
csi = CS5535_CLOCK_GATING_TABLE;
for (; csi->msrnum; csi++){
msr.lo = csi->msr.lo;
msr.hi = csi->msr.hi;
wrmsr(csi->msrnum, msr); // MSR - see table above
}
}
}

111
src/southbridge/amd/cs5535/cs5535.c
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@@ -1,111 +0,0 @@
#include <arch/io.h>
#include <arch/ioapic.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ops.h>
#include <device/pci_ids.h>
#include <console/console.h>
#include "cs5535.h"
static void nvram_on(struct device *dev)
{
#if 0
volatile char *flash = (volatile unsigned char *)0xFFFc0000;
unsigned char id1, id2;
#endif
unsigned char reg;
/* Enable writes to flash at top of memory */
pci_write_config8(dev, 0x52, 0xee);
/* Set positive decode on ROM */
/* Also, there is no apparent reason to turn off the device on the */
/* IDE devices */
reg = pci_read_config8(dev, 0x5b);
reg |= 1 << 5; /* ROM Decode */
reg |= 1 << 3; /* Primary IDE decode */
reg |= 1 << 4; /* Secondary IDE decode */
pci_write_config8(dev, 0x5b, reg);
#if 0 // just to test if the flash is accessible!
*(flash + 0x555) = 0xaa;
*(flash + 0x2aa) = 0x55;
*(flash + 0x555) = 0x90;
id1 = *(volatile unsigned char *) flash;
id2 = *(volatile unsigned char *) (flash + 1);
*flash = 0xf0;
printk(BIOS_DEBUG, "Flash device: MFGID %02x, DEVID %02x\n", id1, id2);
#endif
}
static void southbridge_init(struct device *dev)
{
printk(BIOS_SPEW, "cs5535: %s\n", __func__);
nvram_on(dev);
}
/*
static void dump_south(struct device *dev)
{
int i, j;
for (i = 0; i < 256; i+=16) {
printk(BIOS_DEBUG, "0x%02x:", i);
for (j = 0; j < 16; j++)
printk(BIOS_DEBUG, " %02x", pci_read_config8(dev, i+j));
printk(BIOS_DEBUG, "\n");
}
}
*/
static void southbridge_enable(struct device *dev)
{
printk(BIOS_SPEW, "%s: dev is %p\n", __func__, dev);
}
static void cs5535_read_resources(device_t dev)
{
struct resource *res;
pci_dev_read_resources(dev);
res = new_resource(dev, 1);
res->base = 0x0UL;
res->size = 0x1000UL;
res->limit = 0xffffUL;
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
res = new_resource(dev, 3); /* IOAPIC */
res->base = IO_APIC_ADDR;
res->size = 0x00001000;
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
}
static struct device_operations southbridge_ops = {
.read_resources = cs5535_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = southbridge_init,
.enable = southbridge_enable,
};
static const struct pci_driver cs5535_pci_driver __pci_driver = {
.ops = &southbridge_ops,
.vendor = PCI_VENDOR_ID_NS,
.device = PCI_DEVICE_ID_NS_CS5535
};
struct chip_operations southbridge_amd_cs5535_ops = {
CHIP_NAME("AMD Geode CS5535 Southbridge")
/* This is only called when this device is listed in the
* static device tree.
*/
.enable_dev = southbridge_enable,
};

121
src/southbridge/amd/cs5535/cs5535.h
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@@ -1,121 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2010 Nils Jacobs
*
* This program is free software; you can redistribute it and/or
* modify it under the terms of the GNU General Public License as
* published by the Free Software Foundation; version 2 of
* the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#ifndef _CS5535_H
#define _CS5535_H
/* SouthBridge Equates */
#define CS5535_GLINK_PORT_NUM 0x02 /* port of the SouthBridge */
#define NB_PCI ((2 << 29) + (4 << 26)) /* NB GLPCI is in the same location on all Geodes. */
#define MSR_SB ((CS5535_GLINK_PORT_NUM << 23) + NB_PCI) /* address to the SouthBridge */
#define SB_SHIFT 20 /* 29 -> 26 -> 23 -> 20...... When making a SB address uses this shift. */
#define CS5535_DEV_NUM 0x0F /* default PCI device number for CS5535 */
#define SMBUS_IO_BASE 0x6000
#define GPIO_IO_BASE 0x6100
#define MFGPT_IO_BASE 0x6200
#define ACPI_IO_BASE 0x9C00
#define PMS_IO_BASE 0x9D00
/* Cs5536 as follows. */
/* SB_GLIU */
/* port0 - GLIU */
/* port1 - GLPCI */
/* port2 - USB Controller #2 */
/* port3 - ATA-5 Controller */
/* port4 - MDD */
/* port5 - AC97 */
/* port6 - USB Controller #1 */
/* port7 - GLCP */
#define MSR_SB_GLIU ((9 << 14) + MSR_SB) /* 51024xxx or 510*xxxx - fake out just like GL0 on CPU. */
#define MSR_SB_GLPCI (MSR_SB) /* 5100xxxx - don't go to the GLIU */
#define MSR_SB_USB2 ((2 << SB_SHIFT) + MSR_SB) /* 5120xxxx */
#define MSR_SB_ATA ((3 << SB_SHIFT) + MSR_SB) /* 5130xxxx */
#define MSR_SB_MDD ((4 << SB_SHIFT) + MSR_SB) /* 5140xxxx, a.k.a. DIVIL = Diverse Integrated Logic device */
#define MSR_SB_AC97 ((5 << SB_SHIFT) + MSR_SB) /* 5150xxxx */
#define MSR_SB_USB1 ((6 << SB_SHIFT) + MSR_SB) /* 5160xxxx */
#define MSR_SB_GLCP ((7 << SB_SHIFT) + MSR_SB) /* 5170xxxx */
/* GLIU */
#define GLIU_SB_GLD_MSR_PM (MSR_SB_GLIU + 0x04)
/* USB1 */
#define USB1_SB_GLD_MSR_CONF (MSR_SB_USB1 + 0x01)
#define USB1_SB_GLD_MSR_PM (MSR_SB_USB1 + 0x04)
/* USB2 */
#define USB2_SB_GLD_MSR_CONF (MSR_SB_USB2 + 0x01)
#define USB2_SB_GLD_MSR_PM (MSR_SB_USB2 + 0x04)
/* ATA */
#define ATA_SB_GLD_MSR_CONF (MSR_SB_ATA + 0x01)
#define ATA_SB_GLD_MSR_ERR (MSR_SB_ATA + 0x03)
#define ATA_SB_GLD_MSR_PM (MSR_SB_ATA + 0x04)
#define ATA_SB_IDE_CFG (MSR_SB_ATA + 0x10)
/* AC97 */
#define AC97_SB_GLD_MSR_CONF (MSR_SB_AC97 + 0x01)
#define AC97_SB_GLD_MSR_PM (MSR_SB_AC97 + 0x04)
/* GLPCI */
#define GLPCI_SB_GLD_MSR_PM (MSR_SB_GLPCI + 0x04)
#define GLPCI_SB_CTRL (MSR_SB_GLPCI + 0x10)
#define GLPCI_CRTL_PPIDE_SET (1 << 17)
/* GLCP */
#define GLCP_SB_GLD_MSR_PM (MSR_SB_GLCP + 0x04)
/* MDD */
#define MDD_SB_GLD_MSR_CONF (MSR_SB_MDD + 0x01)
#define MDD_SB_GLD_MSR_PM (MSR_SB_MDD + 0x04)
#define MDD_LBAR_SMB (MSR_SB_MDD + 0x0B)
#define MDD_LBAR_GPIO (MSR_SB_MDD + 0x0C)
#define MDD_LBAR_MFGPT (MSR_SB_MDD + 0x0D)
#define MDD_LBAR_ACPI (MSR_SB_MDD + 0x0E)
#define MDD_LBAR_PMS (MSR_SB_MDD + 0x0F)
#define MDD_LBAR_FLSH0 (MSR_SB_MDD + 0x10)
#define MDD_LBAR_FLSH1 (MSR_SB_MDD + 0x11)
#define MDD_LBAR_FLSH2 (MSR_SB_MDD + 0x12)
#define MDD_LBAR_FLSH3 (MSR_SB_MDD + 0x13)
#define MDD_PIN_OPT (MSR_SB_MDD + 0x15)
#define MDD_NORF_CNTRL (MSR_SB_MDD + 0x18)
/* GPIO */
#define GPIOL_2_SET (1 << 2)
/* GPIO LOW Bank Bit Registers */
#define GPIOL_INPUT_ENABLE (0x20)
#define GPIOL_IN_AUX1_SELECT (0x34)
/* FLASH device macros */
#define FLASH_TYPE_NONE 0 /* No flash device installed */
#define FLASH_TYPE_NAND 1 /* NAND device */
#define FLASH_IF_MEM 1 /* Memory or memory-mapped I/O interface for Flash device */
/* Flash Memory Mask values */
#define FLASH_MEM_4K 0xFFFFF000
#if !defined(__ASSEMBLER__)
#if defined(__PRE_RAM__)
void cs5535_disable_internal_uart(void);
#else
void chipsetinit(void);
#endif
#endif
#endif /* _CS5535_H */

145
src/southbridge/amd/cs5535/early_setup.c
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@@ -1,145 +0,0 @@
/*
*
* cs5535_early_setup.c: Early chipset initialization for CS5535 companion device
*
*
* This file implements the initialization sequence documented in section 4.2 of
* AMD Geode GX Processor CS5535 Companion Device GoedeROM Porting Guide.
*
*/
/**
* @brief Setup PCI IDSEL for CS5535
*
*
*/
static void cs5535_setup_extmsr(void)
{
msr_t msr;
/* forward MSR access to CS5535_GLINK_PORT_NUM to CS5535_DEV_NUM */
msr.hi = msr.lo = 0x00000000;
#if CS5535_GLINK_PORT_NUM <= 4
msr.lo = CS5535_DEV_NUM << ((CS5535_GLINK_PORT_NUM - 1) * 8);
#else
msr.hi = CS5535_DEV_NUM << ((CS5535_GLINK_PORT_NUM - 5) * 8);
#endif
wrmsr(0x5000201e, msr);
}
static void cs5535_setup_idsel(void)
{
/* write IDSEL to the write once register at address 0x0000 */
outl(0x1 << (CS5535_DEV_NUM + 10), 0);
}
static void cs5535_usb_swapsif(void)
{
msr_t msr;
msr = rdmsr(0x51600005);
//USB Serial short detect bit.
if (msr.hi & 0x10) {
/* We need to preserve bits 32,33,35 and not clear any BIST error, but clear the
* SERSHRT error bit */
msr.hi &= 0xFFFFFFFB;
wrmsr(0x51600005, msr);
}
}
static void cs5535_setup_iobase(void)
{
msr_t msr;
/* setup LBAR for SMBus controller */
msr.hi = 0x0000f001;
msr.lo = SMBUS_IO_BASE;
wrmsr(MDD_LBAR_SMB, msr);
/* setup LBAR for GPIO */
msr.hi = 0x0000f001;
msr.lo = GPIO_IO_BASE;
wrmsr(MDD_LBAR_GPIO, msr);
/* setup LBAR for MFGPT */
msr.hi = 0x0000f001;
msr.lo = MFGPT_IO_BASE;
wrmsr(MDD_LBAR_MFGPT, msr);
/* setup LBAR for ACPI */
msr.hi = 0x0000f001;
msr.lo = ACPI_IO_BASE;
wrmsr(MDD_LBAR_ACPI, msr);
/* setup LBAR for PM Support */
msr.hi = 0x0000f001;
msr.lo = PMS_IO_BASE;
wrmsr(MDD_LBAR_PMS, msr);
}
static void cs5535_setup_gpio(void)
{
uint32_t val;
/* setup GPIO pins 14/15 for SDA/SCL */
val = (1<<14 | 1<<15);
/* Output Enable */
outl(0x3fffc000, 0x6100 + 0x04);
//outl(val, 0x6100 + 0x04);
/* Output AUX1 */
outl(0x3fffc000, 0x6100 + 0x10);
//outl(val, 0x6100 + 0x10);
/* Input Enable */
//outl(0x0f5af0a5, 0x6100 + 0x20);
outl(0x3fffc000, 0x6100 + 0x20);
//outl(val, 0x6100 + 0x20);
/* Input AUX1 */
//outl(0x3ffbc004, 0x6100 + 0x34);
outl(0x3fffc000, 0x6100 + 0x34);
//outl(val, 0x6100 + 0x34);
}
void cs5535_disable_internal_uart(void)
{
}
static void cs5535_setup_cis_mode(void)
{
msr_t msr;
/* Setup CPU serial SouthBridge interface to mode C. */
msr = rdmsr(GLPCI_SB_CTRL);
msr.lo &= ~0x18;
msr.lo |= 0x10;
wrmsr(GLPCI_SB_CTRL, msr);
}
static void dummy(void)
{
}
static void cs5535_early_setup(void)
{
msr_t msr;
cs5535_setup_extmsr();
msr = rdmsr(GLCP_SYS_RSTPLL);
if (msr.lo & (0x3f << 26)) {
/* PLL is already set and we are reboot from PLL reset */
printk(BIOS_DEBUG, "reboot from BIOS reset\n");
return;
}
printk(BIOS_DEBUG, "Setup idsel\n");
cs5535_setup_idsel();
printk(BIOS_DEBUG, "Setup iobase\n");
cs5535_usb_swapsif();
cs5535_setup_iobase();
printk(BIOS_DEBUG, "Setup gpio\n");
cs5535_setup_gpio();
printk(BIOS_DEBUG, "Setup cis_mode\n");
cs5535_setup_cis_mode();
printk(BIOS_DEBUG, "Setup smbus\n");
cs5535_enable_smbus();
dummy();
}

22
src/southbridge/amd/cs5535/early_smbus.c
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@@ -1,22 +0,0 @@
#include "smbus.h"
#define SMBUS_IO_BASE 0x6000
/* initialization for SMBus Controller */
static void cs5535_enable_smbus(void)
{
unsigned char val;
/* reset SMBUS controller */
outb(0, SMBUS_IO_BASE + SMB_CTRL2);
/* Set SCL freq and enable SMB controller */
val = inb(SMBUS_IO_BASE + SMB_CTRL2);
val |= ((0x20 << 1) | SMB_CTRL2_ENABLE);
outb(val, SMBUS_IO_BASE + SMB_CTRL2);
/* Setup SMBus host controller address to 0xEF */
val = inb(SMBUS_IO_BASE + SMB_ADD);
val |= (0xEF | SMB_ADD_SAEN);
outb(val, SMBUS_IO_BASE + SMB_ADD);
}

30
src/southbridge/amd/cs5535/ide.c
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@@ -1,30 +0,0 @@
#include <console/console.h>
#include <device/device.h>
#include <device/pci.h>
#include <device/pci_ids.h>
#include <device/pci_ops.h>
#include "cs5535.h"
static void ide_init(struct device *dev)
{
printk(BIOS_SPEW, "cs5535_ide: %s\n", __func__);
}
static void ide_enable(struct device *dev)
{
printk(BIOS_SPEW, "cs5535_ide: %s\n", __func__);
}
static struct device_operations ide_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = ide_init,
.enable = ide_enable,
};
static const struct pci_driver ide_driver __pci_driver = {
.ops = &ide_ops,
.vendor = PCI_VENDOR_ID_NS,
.device = PCI_DEVICE_ID_NS_CS5535_IDE,
};

46
src/southbridge/amd/cs5535/smbus.h
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@@ -1,46 +0,0 @@
//#include <device/smbus_def.h>
#define SMBUS_ERROR -1
#define SMBUS_WAIT_UNTIL_READY_TIMEOUT -2
#define SMBUS_WAIT_UNTIL_DONE_TIMEOUT -3
#define SMB_SDA 0x00
#define SMB_STS 0x01
#define SMB_CTRL_STS 0x02
#define SMB_CTRL1 0x03
#define SMB_ADD 0x04
#define SMB_CTRL2 0x05
#define SMB_CTRL3 0x06
#define SMB_STS_SLVSTP (0x01 << 7)
#define SMB_STS_SDAST (0x01 << 6)
#define SMB_STS_BER (0x01 << 5)
#define SMB_STS_NEGACK (0x01 << 4)
#define SMB_STS_STASTR (0x01 << 3)
#define SMB_STS_NMATCH (0x01 << 2)
#define SMB_STS_MASTER (0x01 << 1)
#define SMB_STS_XMIT (0x01 << 0)
#define SMB_CSTS_TGSCL (0x01 << 5)
#define SMB_CSTS_TSDA (0x01 << 4)
#define SMB_CSTS_GCMTCH (0x01 << 3)
#define SMB_CSTS_MATCH (0x01 << 2)
#define SMB_CSTS_BB (0x01 << 1)
#define SMB_CSTS_BUSY (0x01 << 0)
#define SMB_CTRL1_STASTRE (0x01 << 7)
#define SMB_CTRL1_NMINTE (0x01 << 6)
#define SMB_CTRL1_GCMEN (0x01 << 5)
#define SMB_CTRL1_ACK (0x01 << 4)
#define SMB_CTRL1_RSVD (0x01 << 3)
#define SMB_CTRL1_INTEN (0x01 << 2)
#define SMB_CTRL1_STOP (0x01 << 1)
#define SMB_CTRL1_START (0x01 << 0)
#define SMB_ADD_SAEN (0x01 << 7)
#define SMB_CTRL2_ENABLE 0x01
#define SMBUS_TIMEOUT (100*1000*10)
#define SMBUS_STATUS_MASK 0xfbff
#define SMBUS_IO_BASE 0x6000