sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

cpu/x86: Require CPU_INFO_V2 when selecting PARALLEL_MP

Browse Source 
This will reduce the number of AP init paths we need to support.

BUG=b:194391185, b:179699789
TEST=Boot guybrush to OS and see all CPUs initialized correctly

Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Change-Id: I05beb591bd7b3a26b6c51c10d4ffd6f8621c12eb
Reviewed-on: https://review.coreboot.org/c/coreboot/+/58146
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
This commit is contained in:
Raul E Rangel
2021-10-08 13:10:38 -06:00
committed by Felix Held
parent 1eae39f4cd
commit 99c84787b8
3 changed files with 7 additions and 20 deletions
Download Patch File Download Diff File Expand all files Collapse all files

1
src/cpu/x86/Kconfig
View File

@@ -2,6 +2,7 @@ config PARALLEL_MP
def_bool y
depends on !LEGACY_SMP_INIT
depends on SMP
select CPU_INFO_V2
help
This option uses common MP infrastructure for bringing up APs
in parallel. It additionally provides a more flexible mechanism

24
src/cpu/x86/mp_init.c
View File

@@ -182,14 +182,12 @@ static void park_this_cpu(void *unused)
* been loaded. */
static void asmlinkage ap_init(unsigned int cpu)
{
struct cpu_info *info;
struct cpu_info *info = cpu_info();
/* Ensure the local APIC is enabled */
enable_lapic();
info = cpu_info();
info->index = cpu;
info->cpu = cpus_dev[cpu];
info->cpu = cpus_dev[info->index];
cpu_add_map_entry(info->index);
@@ -197,10 +195,10 @@ static void asmlinkage ap_init(unsigned int cpu)
info->cpu->path.apic.apic_id = lapicid();
if (cpu_is_intel())
printk(BIOS_INFO, "AP: slot %d apic_id %x, MCU rev: 0x%08x\n", cpu,
printk(BIOS_INFO, "AP: slot %zu apic_id %x, MCU rev: 0x%08x\n", info->index,
info->cpu->path.apic.apic_id, get_current_microcode_rev());
else
printk(BIOS_INFO, "AP: slot %d apic_id %x\n", cpu,
printk(BIOS_INFO, "AP: slot %zu apic_id %x\n", info->index,
info->cpu->path.apic.apic_id);
/* Walk the flight plan */
@@ -215,20 +213,10 @@ static void setup_default_sipi_vector_params(struct sipi_params *sp)
sp->gdt = (uintptr_t)&gdt;
sp->gdtlimit = (uintptr_t)&gdt_end - (uintptr_t)&gdt - 1;
sp->idt_ptr = (uintptr_t)&idtarg;
if (CONFIG(CPU_INFO_V2)) {
sp->per_cpu_segment_descriptors = (uintptr_t)&per_cpu_segment_descriptors;
sp->per_cpu_segment_selector = per_cpu_segment_selector;
}
sp->per_cpu_segment_descriptors = (uintptr_t)&per_cpu_segment_descriptors;
sp->per_cpu_segment_selector = per_cpu_segment_selector;
sp->stack_size = CONFIG_STACK_SIZE;
sp->stack_top = ALIGN_DOWN((uintptr_t)&_estack, CONFIG_STACK_SIZE);
/*
* In the CPU_INFO_V2 case, we don't need to pre-allocate the space on the stack.
* Instead we push them onto the top of the stack in the sipi vector.
*/
if (!CONFIG(CPU_INFO_V2)) {
/* Adjust the stack top to take into account cpu_info. */
sp->stack_top -= sizeof(struct cpu_info);
}
}
#define NUM_FIXED_MTRRS 11

2
src/cpu/x86/sipi_vector.S
View File

@@ -104,7 +104,6 @@ _start:
subl %eax, %edx
mov %edx, %esp
#if CONFIG(CPU_INFO_V2)
push_cpu_info index=%ecx
push_per_cpu_segment_data
@@ -118,7 +117,6 @@ _start:
shl $3, %eax /* The index is << 3 in the segment selector */
add per_cpu_segment_selector, %eax
mov %eax, %gs
#endif
andl $0xfffffff0, %esp /* ensure stack alignment */