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haswell: Factor out max_ddr3_freq

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All mainboards choose the maximum speed of DDR3-1600.

Change-Id: I8863f9d1df950b924f596689ebf1bfda5d317e06
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43120
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Reviewed-by: Michael Niewöhner
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons 2020-07-03 20:36:50 +02:00
parent d7bf3ad939
commit 9a369718d6
8 changed files with 1 additions and 7 deletions
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1
src/mainboard/asrock/b85m_pro4/romstage.c
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@ -30,7 +30,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
pei_data->spd_addresses[3] = 0xa6;
pei_data->ec_present = 0;
pei_data->gbe_enable = 1;
pei_data->max_ddr3_freq = 1600;
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */

1
src/mainboard/asrock/h81m-hds/romstage.c
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@ -27,7 +27,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
pei_data->spd_addresses[0] = 0xa0;
pei_data->spd_addresses[2] = 0xa4;
pei_data->ec_present = 0;
pei_data->max_ddr3_freq = 1600;
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */

1
src/mainboard/google/beltino/romstage.c
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@ -51,7 +51,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
/* Enable 2x refresh mode */
pei_data->ddr_refresh_2x = 1;
pei_data->dq_pins_interleaved = 1;
pei_data->max_ddr3_freq = 1600;
pei_data->usb_xhci_on_resume = 1;
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {

1
src/mainboard/google/slippy/romstage.c
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@ -48,7 +48,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
pei_data->spd_addresses[0] = 0xff;
pei_data->spd_addresses[2] = 0xff;
pei_data->ec_present = 1;
pei_data->max_ddr3_freq = 1600;
pei_data->usb_xhci_on_resume = 1;
variant_romstage_entry(pei_data);

1
src/mainboard/intel/baskingridge/romstage.c
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@ -52,7 +52,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
pei_data->spd_addresses[2] = 0xa4;
pei_data->spd_addresses[3] = 0xa6;
pei_data->ec_present = 0;
pei_data->max_ddr3_freq = 1600;
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */

1
src/mainboard/lenovo/t440p/romstage.c
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@ -50,7 +50,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
pei_data->spd_addresses[2] = 0xa2;
pei_data->ec_present = 1;
pei_data->gbe_enable = 1;
pei_data->max_ddr3_freq = 1600;
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */

1
src/mainboard/supermicro/x10slm-f/romstage.c
View File

@ -29,7 +29,6 @@ void mainboard_fill_pei_data(struct pei_data *pei_data)
pei_data->spd_addresses[3] = 0xa6;
pei_data->ec_present = 0;
pei_data->ddr_refresh_2x = 1;
pei_data->max_ddr3_freq = 1600;
struct usb2_port_setting usb2_ports[MAX_USB2_PORTS] = {
/* Length, Enable, OCn#, Location */

1
src/northbridge/intel/haswell/romstage.c
View File

@ -52,6 +52,7 @@ void mainboard_romstage_entry(void)
.gpiobase = DEFAULT_GPIOBASE,
.temp_mmio_base = 0xfed08000,
.tseg_size = CONFIG_SMM_TSEG_SIZE,
.max_ddr3_freq = 1600,
};
mainboard_fill_pei_data(&pei_data);