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tgl mainboards: Move PCIe root port settings into their device scope

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Change-Id: I110cc95d536cb0fd3b5db85b84cca7a96e31401c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83253
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Felix Singer
2024-06-28 06:28:43 +02:00
parent d9cb2c12d7
commit 9b31a90e7f
6 changed files with 92 additions and 95 deletions
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52
src/mainboard/google/volteer/variants/baseboard/devicetree.cb
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@ -93,29 +93,6 @@ chip soc/intel/tigerlake
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC3)"
register "tcss_ports[1]" = "TCSS_PORT_DEFAULT(OC0)"
# NVMe PCIE 9 using clk 0
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[0]" = "8"
register "PcieClkSrcClkReq[0]" = "0"
register "PcieRpSlotImplemented[8]" = "1"
# Optane PCIE 11 using clk 0
register "PcieRpLtrEnable[10]" = "1"
register "HybridStorageMode" = "0"
register "PcieRpSlotImplemented[10]" = "1"
# SD Card PCIE 8 using clk 3
register "PcieRpLtrEnable[7]" = "1"
register "PcieRpHotPlug[7]" = "1"
register "PcieClkSrcUsage[3]" = "7"
register "PcieClkSrcClkReq[3]" = "3"
# WLAN PCIE 7 using clk 1
register "PcieRpLtrEnable[6]" = "1"
register "PcieClkSrcUsage[1]" = "6"
register "PcieClkSrcClkReq[1]" = "1"
register "PcieRpSlotImplemented[6]" = "1"
# Mark SRCCLKREQ pins as unused that are routed for a Non-Clkreq functionality
register "PcieClkSrcUsage[2]" = "PCIE_CLK_NOTUSED"
register "PcieClkSrcUsage[4]" = "PCIE_CLK_NOTUSED"
@ -450,8 +427,20 @@ chip soc/intel/tigerlake
register "SataPortsDevSlp[1]" = "1"
register "SataPortsEnableDitoConfig[1]" = "1"
end
device ref pcie_rp7 on end
device ref pcie_rp7 on
# WLAN PCIE 7 using clk 1
register "PcieRpLtrEnable[6]" = "1"
register "PcieClkSrcUsage[1]" = "6"
register "PcieClkSrcClkReq[1]" = "1"
register "PcieRpSlotImplemented[6]" = "1"
end
device ref pcie_rp8 on
# SD Card PCIE 8 using clk 3
register "PcieRpLtrEnable[7]" = "1"
register "PcieRpHotPlug[7]" = "1"
register "PcieClkSrcUsage[3]" = "7"
register "PcieClkSrcClkReq[3]" = "3"
probe DB_SD SD_GL9755S
probe DB_SD SD_RTS5261
probe DB_SD SD_RTS5227S
@ -477,8 +466,19 @@ chip soc/intel/tigerlake
end
end
end
device ref pcie_rp9 on end
device ref pcie_rp11 on end
device ref pcie_rp9 on
# NVMe PCIE 9 using clk 0
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[0]" = "8"
register "PcieClkSrcClkReq[0]" = "0"
register "PcieRpSlotImplemented[8]" = "1"
end
device ref pcie_rp11 on
# Optane PCIE 11 using clk 0
register "PcieRpLtrEnable[10]" = "1"
register "HybridStorageMode" = "0"
register "PcieRpSlotImplemented[10]" = "1"
end
device ref uart0 on end
device ref gspi0 on
chip drivers/spi/acpi

14
src/mainboard/google/volteer/variants/chronicler/overridetree.cb
View File

@ -5,12 +5,6 @@ chip soc/intel/tigerlake
register "DdiPort2Hpd" = "0"
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}"
# EMMC PCIE 5 using clk 5
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpHotPlug[4]" = "1"
register "PcieClkSrcUsage[5]" = "4"
register "PcieClkSrcClkReq[5]" = "5"
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
@ -274,7 +268,13 @@ chip soc/intel/tigerlake
device generic 0 on end
end
end
device ref pcie_rp5 on end
device ref pcie_rp5 on
# EMMC PCIE 5 using clk 5
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpHotPlug[4]" = "1"
register "PcieClkSrcUsage[5]" = "4"
register "PcieClkSrcClkReq[5]" = "5"
end
device ref pmc hidden
# The pmc_mux chip driver is a placeholder for the
# PMC.MUX device in the ACPI hierarchy.

14
src/mainboard/google/volteer/variants/elemi/overridetree.cb
View File

@ -5,12 +5,6 @@ chip soc/intel/tigerlake
register "DdiPort2Hpd" = "0"
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}"
# EMMC PCIE 5 using clk 5
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpHotPlug[4]" = "1"
register "PcieClkSrcUsage[5]" = "4"
register "PcieClkSrcClkReq[5]" = "5"
#+-------------------+---------------------------+
#| Field | Value |
#+-------------------+---------------------------+
@ -275,7 +269,13 @@ chip soc/intel/tigerlake
device generic 0 on end
end
end
device ref pcie_rp5 on end
device ref pcie_rp5 on
# EMMC PCIE 5 using clk 5
register "PcieRpLtrEnable[4]" = "1"
register "PcieRpHotPlug[4]" = "1"
register "PcieClkSrcUsage[5]" = "4"
register "PcieClkSrcClkReq[5]" = "5"
end
device ref pmc hidden
# The pmc_mux chip driver is a placeholder for the
# PMC.MUX device in the ACPI hierarchy.

22
src/mainboard/google/volteer/variants/voema/overridetree.cb
View File

@ -8,16 +8,6 @@ chip soc/intel/tigerlake
register "TcssAuxOri" = "1"
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E10, .pad_auxn_dc = GPP_E13}"
# Disable WLAN PCIE 7
register "PcieRpLtrEnable[6]" = "0"
register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED"
register "PcieRpSlotImplemented[6]" = "1"
# Disable SD Card PCIE 8
register "PcieRpLtrEnable[7]" = "0"
register "PcieRpHotPlug[7]" = "0"
register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED"
device domain 0 on
device ref ipu on end # IPU
device ref i2c0 on
@ -97,8 +87,18 @@ chip soc/intel/tigerlake
probe AUDIO MAX98360_ALC5682I_I2S
probe AUDIO RT1011_ALC5682I_I2S
end
device ref pcie_rp7 off end
device ref pcie_rp7 off
# Disable WLAN PCIE 7
register "PcieRpLtrEnable[6]" = "0"
register "PcieClkSrcUsage[1]" = "PCIE_CLK_NOTUSED"
register "PcieRpSlotImplemented[6]" = "1"
end
device ref pcie_rp8 off
# Disable SD Card PCIE 8
register "PcieRpLtrEnable[7]" = "0"
register "PcieRpHotPlug[7]" = "0"
register "PcieClkSrcUsage[3]" = "PCIE_CLK_NOTUSED"
# override-devicetree rules say it's only
# the same device if it has the same probes:
probe DB_SD SD_GL9755S

42
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
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@ -17,28 +17,9 @@ chip soc/intel/tigerlake
# CPU replacement check
register "CpuReplacementCheck" = "1"
register "PcieRpSlotImplemented[2]" = "1"
register "PcieRpSlotImplemented[3]" = "1"
register "PcieRpSlotImplemented[8]" = "1"
register "PcieRpSlotImplemented[10]" = "1"
# Enable RP LTR
register "PcieRpLtrEnable[2]" = "1"
register "PcieRpLtrEnable[3]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[10]" = "1"
# Hybrid storage mode
register "HybridStorageMode" = "1"
register "PcieClkSrcClkReq[1]" = "1"
register "PcieClkSrcClkReq[2]" = "2"
register "PcieClkSrcClkReq[3]" = "3"
register "PcieClkSrcUsage[1]" = "0x2"
register "PcieClkSrcUsage[2]" = "0x3"
register "PcieClkSrcUsage[3]" = "0x8"
# enabling EDP in PortA
register "DdiPortAConfig" = "DDI_PORT_CFG_EDP"
@ -260,8 +241,17 @@ chip soc/intel/tigerlake
device ref uart2 on end
device ref pcie_rp1 off end
device ref pcie_rp2 off end
device ref pcie_rp3 on end
device ref pcie_rp3 on
register "PcieRpSlotImplemented[2]" = "1"
register "PcieRpLtrEnable[2]" = "1"
register "PcieClkSrcUsage[1]" = "0x2"
register "PcieClkSrcClkReq[1]" = "1"
end
device ref pcie_rp4 on
register "PcieRpSlotImplemented[3]" = "1"
register "PcieRpLtrEnable[3]" = "1"
register "PcieClkSrcUsage[2]" = "0x3"
register "PcieClkSrcClkReq[2]" = "2"
chip soc/intel/common/block/pcie/rtd3
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B17)"
register "srcclk_pin" = "2"
@ -272,9 +262,17 @@ chip soc/intel/tigerlake
device ref pcie_rp6 off end
device ref pcie_rp7 off end
device ref pcie_rp8 off end
device ref pcie_rp9 on end
device ref pcie_rp9 on
register "PcieRpSlotImplemented[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[3]" = "0x8"
register "PcieClkSrcClkReq[3]" = "3"
end
device ref pcie_rp10 off end
device ref pcie_rp11 on end
device ref pcie_rp11 on
register "PcieRpSlotImplemented[10]" = "1"
register "PcieRpLtrEnable[10]" = "1"
end
device ref pcie_rp12 off end
device ref uart0 off end
device ref uart1 off end

43
src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
View File

@ -17,28 +17,9 @@ chip soc/intel/tigerlake
# CPU replacement check
register "CpuReplacementCheck" = "1"
register "PcieRpSlotImplemented[2]" = "1"
register "PcieRpSlotImplemented[3]" = "1"
register "PcieRpSlotImplemented[8]" = "1"
register "PcieRpSlotImplemented[10]" = "1"
# Enable PR LTR
register "PcieRpLtrEnable[2]" = "1"
register "PcieRpLtrEnable[3]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieRpLtrEnable[10]" = "1"
# Hybrid storage mode
register "HybridStorageMode" = "1"
register "PcieClkSrcClkReq[1]" = "1"
register "PcieClkSrcClkReq[2]" = "2"
register "PcieClkSrcClkReq[3]" = "3"
register "PcieClkSrcUsage[1]" = "0x2"
register "PcieClkSrcUsage[2]" = "0x3"
register "PcieClkSrcUsage[3]" = "0x8"
# enabling EDP in PortA
register "DdiPortAConfig" = "DDI_PORT_CFG_EDP"
@ -262,8 +243,18 @@ chip soc/intel/tigerlake
device ref uart2 on end
device ref pcie_rp1 off end
device ref pcie_rp2 off end
device ref pcie_rp3 on end
device ref pcie_rp3 on
register "PcieRpSlotImplemented[2]" = "1"
register "PcieRpLtrEnable[2]" = "1"
register "PcieClkSrcUsage[1]" = "0x2"
register "PcieClkSrcClkReq[1]" = "1"
end
device ref pcie_rp4 on
register "PcieRpSlotImplemented[3]" = "1"
register "PcieRpLtrEnable[3]" = "1"
register "PcieClkSrcUsage[2]" = "0x3"
register "PcieClkSrcClkReq[2]" = "2"
chip soc/intel/common/block/pcie/rtd3
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B17)"
register "srcclk_pin" = "2"
@ -274,9 +265,17 @@ chip soc/intel/tigerlake
device ref pcie_rp6 off end
device ref pcie_rp7 off end
device ref pcie_rp8 off end
device ref pcie_rp9 on end
device ref pcie_rp9 on
register "PcieRpSlotImplemented[8]" = "1"
register "PcieRpLtrEnable[8]" = "1"
register "PcieClkSrcUsage[3]" = "0x8"
register "PcieClkSrcClkReq[3]" = "3"
end
device ref pcie_rp10 off end
device ref pcie_rp11 on end
device ref pcie_rp11 on
register "PcieRpSlotImplemented[10]" = "1"
register "PcieRpLtrEnable[10]" = "1"
end
device ref pcie_rp12 off end
device ref uart0 off end
device ref uart1 off end