mb/system76/rpl: Add Oryx Pro 12 as a variant
Change-Id: I7c5bee7e188a1fd73ab1d546e941929471227554 Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
Tim Crawford
parent
bcd34461da
commit
9bd47b4bed
@ -84,6 +84,16 @@ config BOARD_SYSTEM76_ORYP11
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select SOC_INTEL_ALDERLAKE_PCH_P
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select SOC_INTEL_ENABLE_USB4_PCIE_RESOURCES
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config BOARD_SYSTEM76_ORYP12
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select BOARD_SYSTEM76_RPL_COMMON
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select DRIVERS_GFX_NVIDIA
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select DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST
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select DRIVERS_I2C_TAS5825M
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select DRIVERS_INTEL_DTBT
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select EC_SYSTEM76_EC_DGPU
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select PCIEXP_HOTPLUG
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select SOC_INTEL_ALDERLAKE_PCH_S
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config BOARD_SYSTEM76_SERW13
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select BOARD_SYSTEM76_RPL_COMMON
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select DRIVERS_GFX_NVIDIA
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@ -107,6 +117,7 @@ config VARIANT_DIR
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default "gaze18" if BOARD_SYSTEM76_GAZE18
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default "lemp12" if BOARD_SYSTEM76_LEMP12
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default "oryp11" if BOARD_SYSTEM76_ORYP11
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default "oryp12" if BOARD_SYSTEM76_ORYP12
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default "serw13" if BOARD_SYSTEM76_SERW13
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config OVERRIDE_DEVICETREE
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@ -121,6 +132,7 @@ config MAINBOARD_PART_NUMBER
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default "gaze18" if BOARD_SYSTEM76_GAZE18
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default "lemp12" if BOARD_SYSTEM76_LEMP12
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default "oryp11" if BOARD_SYSTEM76_ORYP11
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default "oryp12" if BOARD_SYSTEM76_ORYP12
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default "serw13" if BOARD_SYSTEM76_SERW13
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config MAINBOARD_SMBIOS_PRODUCT_NAME
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@ -130,7 +142,7 @@ config MAINBOARD_SMBIOS_PRODUCT_NAME
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default "Galago Pro" if BOARD_SYSTEM76_GALP7
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default "Gazelle" if BOARD_SYSTEM76_GAZE18
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default "Lemur Pro" if BOARD_SYSTEM76_LEMP12
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default "Oryx Pro" if BOARD_SYSTEM76_ORYP11
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default "Oryx Pro" if BOARD_SYSTEM76_ORYP11 || BOARD_SYSTEM76_ORYP12
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default "Serval WS" if BOARD_SYSTEM76_SERW13
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config MAINBOARD_VERSION
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@ -142,6 +154,7 @@ config MAINBOARD_VERSION
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default "gaze18" if BOARD_SYSTEM76_GAZE18
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default "lemp12" if BOARD_SYSTEM76_LEMP12
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default "oryp11" if BOARD_SYSTEM76_ORYP11
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default "oryp12" if BOARD_SYSTEM76_ORYP12
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default "serw13" if BOARD_SYSTEM76_SERW13
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config CMOS_DEFAULT_FILE
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@ -161,12 +174,12 @@ config DRIVERS_GFX_NVIDIA_BRIDGE
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default 0x02 if BOARD_SYSTEM76_BONW15
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config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_TPP
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default 45 if BOARD_SYSTEM76_ORYP11
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default 45 if BOARD_SYSTEM76_ORYP11 || BOARD_SYSTEM76_ORYP12
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default 55 if BOARD_SYSTEM76_ADDW3 || BOARD_SYSTEM76_ADDW4 || BOARD_SYSTEM76_GAZE18 || BOARD_SYSTEM76_SERW13
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default 80 if BOARD_SYSTEM76_BONW15
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config DRIVERS_GFX_NVIDIA_DYNAMIC_BOOST_MAX
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default 25 if BOARD_SYSTEM76_ADDW3 || BOARD_SYSTEM76_ADDW4 || BOARD_SYSTEM76_BONW15 || BOARD_SYSTEM76_GAZE18 || BOARD_SYSTEM76_ORYP11 || BOARD_SYSTEM76_SERW13
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default 25 if BOARD_SYSTEM76_ADDW3 || BOARD_SYSTEM76_ADDW4 || BOARD_SYSTEM76_BONW15 || BOARD_SYSTEM76_GAZE18 || BOARD_SYSTEM76_ORYP11 || BOARD_SYSTEM76_ORYP12 || BOARD_SYSTEM76_SERW13
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config FMDFILE
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default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/variants/\$(CONFIG_VARIANT_DIR)/board.fmd"
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@ -24,5 +24,8 @@ config BOARD_SYSTEM76_LEMP12
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config BOARD_SYSTEM76_ORYP11
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bool "oryp11"
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config BOARD_SYSTEM76_ORYP12
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bool "oryp12"
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config BOARD_SYSTEM76_SERW13
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bool "serw13"
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@ -14,5 +14,6 @@ romstage-y += variants/$(VARIANT_DIR)/romstage.c
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ramstage-y += ramstage.c
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ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
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ramstage-y += variants/$(VARIANT_DIR)/gpio.c
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ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += variants/$(VARIANT_DIR)/tas5825m.c
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SPD_SOURCES = samsung-M425R1GB4BB0-CQKOD
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12
src/mainboard/system76/rpl/variants/oryp12/board.fmd
Normal file
12
src/mainboard/system76/rpl/variants/oryp12/board.fmd
Normal file
@ -0,0 +1,12 @@
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FLASH 32M {
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SI_DESC 4K
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SI_ME 3944K
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SI_BIOS@16M 16M {
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RW_MRC_CACHE 64K
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SMMSTORE(PRESERVE) 256K
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WP_RO {
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FMAP 4K
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COREBOOT(CBFS)
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}
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}
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}
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@ -0,0 +1,2 @@
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Board name: oryp12
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Release year: 2024
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BIN
src/mainboard/system76/rpl/variants/oryp12/data.vbt
Normal file
BIN
src/mainboard/system76/rpl/variants/oryp12/data.vbt
Normal file
Binary file not shown.
296
src/mainboard/system76/rpl/variants/oryp12/gpio.c
Normal file
296
src/mainboard/system76/rpl/variants/oryp12/gpio.c
Normal file
@ -0,0 +1,296 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <mainboard/gpio.h>
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#include <soc/gpio.h>
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static const struct pad_config gpio_table[] = {
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/* ------- GPIO Group GPD ------- */
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PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // BATLOW_N
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PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
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PAD_NC(GPD2, NONE),
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PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
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PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
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PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
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PAD_NC(GPD6, NONE), // SLP_A# (test)
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PAD_NC(GPD7, NONE), // GPD_7 (strap)
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PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // CNVI_SUSCLK
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PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN#
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PAD_CFG_NF(GPD10, NONE, DEEP, NF1), // SLP_S5# (test)
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PAD_NC(GPD11, NONE),
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PAD_NC(GPD12, NONE),
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/* ------- GPIO Group GPP_A ------- */
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PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
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PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
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PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
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PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
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PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
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PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), // ESPI_CLK_EC
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PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // ESPI_RESET#
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PAD_NC(GPP_A7, NONE),
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PAD_NC(GPP_A8, NONE),
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PAD_NC(GPP_A9, NONE),
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PAD_CFG_NF(GPP_A10, UP_20K, DEEP, NF1), // SERIRQ_ESPI_ALERT0
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PAD_NC(GPP_A11, NONE),
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PAD_NC(GPP_A12, NONE),
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PAD_NC(GPP_A13, NONE),
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PAD_NC(GPP_A14, NONE),
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/* ------- GPIO Group GPP_B ------- */
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_PAD_CFG_STRUCT(GPP_B0, 0x40100100, 0x3000), // PIRQ#_TPM
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PAD_CFG_GPI(GPP_B1, NONE, DEEP),
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PAD_CFG_GPI(GPP_B2, NONE, DEEP), //CNVI_WAKE#
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PAD_CFG_GPO(GPP_B3, 1, PLTRST), // BT_EN
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PAD_NC(GPP_B4, NONE),
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PAD_NC(GPP_B5, NONE),
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PAD_NC(GPP_B6, NONE),
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PAD_NC(GPP_B7, NONE), // M2_SSD2_RST#
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PAD_NC(GPP_B8, NONE), // M2_SSD1_RST#
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PAD_NC(GPP_B9, NONE), // M2_SSD1_PWR_EN
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PAD_NC(GPP_B10, NONE), // M2_SSD2_PWR_EN
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PAD_NC(GPP_B11, NONE),
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PAD_NC(GPP_B12, NONE),
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
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PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // HDA_SPKR
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PAD_CFG_GPO(GPP_B15, 0, DEEP), // PS8461_SW (XXX: NC)
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PAD_NC(GPP_B16, NONE),
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PAD_NC(GPP_B17, NONE),
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PAD_CFG_NF(GPP_B18, NONE, PWROK, NF1), // GPP_B18_PMCALERT#
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PAD_CFG_GPO(GPP_B19, 1, DEEP), // PCH_WLAN_EN (XXX: NC)
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PAD_CFG_GPO(GPP_B20, 0, DEEP), // GPIO_LANRTD3
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_PAD_CFG_STRUCT(GPP_B21, 0x42880100, 0x0000), // GPP_B21_TBT_WAKE#
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PAD_CFG_GPO(GPP_B22, 0, DEEP), // LAN_PLT_RST#
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PAD_CFG_GPI(GPP_B23, NONE, DEEP), // Crystal frequency bit 1 strap
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/* ------- GPIO Group GPP_C ------- */
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PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
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PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
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PAD_CFG_GPI(GPP_C2, NONE, DEEP), // PCH_PORT80_LED
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PAD_CFG_NF(GPP_C3, NONE, DEEP, NF3), // GPPB_I2C2_SDA
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PAD_CFG_NF(GPP_C4, NONE, DEEP, NF3), // GPPB_I2C2_SCL
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PAD_CFG_GPO(GPP_C5, 0, DEEP), // GPP_C_5_SML0ALERT_N
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PAD_CFG_NF(GPP_C6, NONE, DEEP, NF2), // I2C_SDA_AMP
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PAD_CFG_NF(GPP_C7, NONE, DEEP, NF2), // I2C_SCL_AMP
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PAD_CFG_GPI(GPP_C8, NONE, DEEP), // TPM_DET
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PAD_NC(GPP_C9, NONE),
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PAD_NC(GPP_C10, NONE),
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PAD_NC(GPP_C11, NONE),
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PAD_NC(GPP_C12, NONE),
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PAD_NC(GPP_C13, NONE),
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PAD_NC(GPP_C14, NONE),
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PAD_NC(GPP_C15, NONE),
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PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // I2C_SDA_TP
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PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // I2C_SCL_TP
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PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), // PCH_I2C_SDA
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PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), // PCH_I2C_SCL
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// GPP_C20 (UART2_RXD) configured in bootblock
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// GPP_C21 (UART2_TXD) configured in bootblock
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PAD_CFG_GPO(GPP_C22, 0, DEEP),
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PAD_CFG_GPO(GPP_C23, 0, DEEP),
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/* ------- GPIO Group GPP_D ------- */
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PAD_NC(GPP_D0, NONE),
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PAD_NC(GPP_D1, NONE),
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PAD_NC(GPP_D2, NONE),
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PAD_CFG_GPO(GPP_D3, 0, DEEP), // GFX_DETECT_STRAP
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PAD_NC(GPP_D4, NONE), // GPP_D4_SML1CLK
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PAD_CFG_GPO(GPP_D5, 1, DEEP), // M.2_BT_PCMFRM_CRF_RST_N
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// GPP_D6 (M.2_BT_PCMOUT_CLKREQ0) configured by FSP
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PAD_NC(GPP_D7, NONE), // M.2_BT_PCMIN
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PAD_NC(GPP_D8, NONE), // M.2_BT_PCMCLK
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PAD_NC(GPP_D9, NONE), // GPP_D9_SML0CLK
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PAD_NC(GPP_D10, NONE), // GPP_D10_SML0DATA
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PAD_NC(GPP_D11, NONE),
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PAD_NC(GPP_D12, NONE),
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PAD_NC(GPP_D13, NONE),
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PAD_NC(GPP_D14, NONE),
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PAD_NC(GPP_D15, NONE), // GPP_D15_SML1DATA
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PAD_NC(GPP_D16, NONE),
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PAD_NC(GPP_D17, NONE),
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PAD_NC(GPP_D18, NONE),
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PAD_NC(GPP_D19, NONE),
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PAD_NC(GPP_D20, NONE),
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PAD_NC(GPP_D21, NONE),
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PAD_NC(GPP_D22, NONE),
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PAD_NC(GPP_D23, NONE),
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/* ------- GPIO Group GPP_E ------- */
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PAD_NC(GPP_E0, NONE),
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PAD_NC(GPP_E1, NONE),
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PAD_CFG_GPI(GPP_E2, NONE, DEEP), // SWI#
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PAD_CFG_GPI(GPP_E3, NONE, DEEP), // SMI#
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PAD_NC(GPP_E4, NONE),
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PAD_NC(GPP_E5, NONE),
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PAD_NC(GPP_E6, NONE),
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PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, LEVEL), // TP_ATTN#
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PAD_NC(GPP_E8, NONE),
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PAD_CFG_GPI(GPP_E9, NONE, DEEP), // GPP_E_9_USB_OC0_N
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PAD_CFG_GPI(GPP_E10, NONE, DEEP), // GPP_E_10_USB_OC1_N
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PAD_CFG_GPI(GPP_E11, NONE, DEEP), // GPP_E_11_USB_OC2_N
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PAD_CFG_GPI(GPP_E12, NONE, DEEP), // GPP_E_12_USB_OC3_N
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PAD_NC(GPP_E13, NONE),
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PAD_NC(GPP_E14, NONE),
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PAD_CFG_GPO(GPP_E15, 1, DEEP), // ROM_I2C_EN
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PAD_NC(GPP_E16, NONE),
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PAD_CFG_GPI(GPP_E17, NONE, DEEP), // SB_KBCRST#
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PAD_CFG_GPO(GPP_E18, 1, DEEP), // SB_BLON
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PAD_NC(GPP_E19, NONE),
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PAD_NC(GPP_E20, NONE),
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PAD_NC(GPP_E21, NONE),
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/* ------- GPIO Group GPP_F ------- */
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PAD_NC(GPP_F0, NONE),
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PAD_NC(GPP_F1, NONE),
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PAD_CFG_GPO(GPP_F2, 1, DEEP), // GPP_F2_TBT_RST#
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PAD_NC(GPP_F3, NONE),
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PAD_NC(GPP_F4, NONE),
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PAD_CFG_GPI(GPP_F5, NONE, DEEP), // GPIO4_GC6_NVVDD_EN_R
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PAD_NC(GPP_F6, NONE), // GPU_EVENT#
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PAD_NC(GPP_F7, NONE),
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PAD_CFG_GPI(GPP_F8, NONE, PLTRST), // GC6_FB_EN_PCH
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// GPP_F9 (DGPU_PWR_EN) configured in bootblock
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PAD_CFG_GPI(GPP_F10, NONE, DEEP), // GPP_F10
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PAD_NC(GPP_F11, NONE), // CARD_RTD3_RST#
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PAD_NC(GPP_F12, NONE),
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PAD_NC(GPP_F13, NONE),
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PAD_NC(GPP_F14, NONE),
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PAD_CFG_GPI(GPP_F15, NONE, DEEP), // H_SKTOCC_N
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PAD_NC(GPP_F16, NONE),
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PAD_CFG_GPI(GPP_F17, NONE, DEEP), // PLVDD_RST_EC
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PAD_CFG_GPO(GPP_F18, 0, DEEP), // CCD_FW_WP#
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PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
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PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
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PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
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PAD_NC(GPP_F22, NONE),
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PAD_NC(GPP_F23, NONE),
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/* ------- GPIO Group GPP_G ------- */
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PAD_NC(GPP_G0, NONE),
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PAD_NC(GPP_G1, NONE),
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PAD_NC(GPP_G2, NONE),
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PAD_CFG_GPI(GPP_G3, NONE, DEEP), // L: W/Pantone, H: W/O Pantone
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PAD_CFG_GPI(GPP_G4, NONE, DEEP), // L: BID_X2, H: BID_X6/X4
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PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), // GPP_G_5_SLP_DRAM_N
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PAD_CFG_GPI(GPP_G6, NONE, DEEP),
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PAD_CFG_GPI(GPP_G7, NONE, DEEP),
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/* ------- GPIO Group GPP_H ------- */
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PAD_CFG_GPI(GPP_H0, NONE, DEEP), // VAL_SV_ADVANCE_STRAP
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PAD_NC(GPP_H1, NONE),
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PAD_CFG_GPI(GPP_H2, NONE, DEEP), // LAN_GPIO_WAKE_N
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// GPP_H3 (PEX_SSD2_CLKREQ#) configured by FSP
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// GPP_H4 (PEX_SSD1_CLKREQ#) configured by FSP
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// GPP_H5 (WLAN_CLKREQ#) configured by FSP
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// GPP_H6 (CARD_CLKREQ#) configured by FSP
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// GPP_H7 (LAN_CLKREQ#) configured by FSP
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// GPP_H8 (PEG_CLKREQ#) configured by FSP
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// GPP_H9 (TBT_CLKREQ#) configured by FSP
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PAD_NC(GPP_H10, NONE),
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PAD_NC(GPP_H11, NONE),
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PAD_CFG_GPO(GPP_H12, 0, DEEP), // L: MAFS, H: SAFS
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PAD_NC(GPP_H13, NONE),
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PAD_NC(GPP_H14, NONE),
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PAD_CFG_GPO(GPP_H15, 0, DEEP), // JTAG ODT: L: disabled, H: enabled
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PAD_NC(GPP_H16, NONE),
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PAD_NC(GPP_H17, NONE), // M2_WLAN_RST#
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PAD_CFG_GPO(GPP_H18, 0, DEEP), // VCCSPI: L: 3.3V, H: 1.8V
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PAD_NC(GPP_H19, NONE),
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PAD_NC(GPP_H20, NONE),
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PAD_CFG_GPO(GPP_H21, 0, DEEP), // TBT_MRESET_PCH
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PAD_NC(GPP_H22, NONE),
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PAD_NC(GPP_H23, NONE),
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/* ------- GPIO Group GPP_I ------- */
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PAD_NC(GPP_I0, NONE),
|
||||
PAD_CFG_NF(GPP_I1, NONE, PLTRST, NF1), // CPU_DP_B_HPD
|
||||
PAD_CFG_NF(GPP_I2, NONE, PLTRST, NF1), // HDMI_HPD
|
||||
PAD_CFG_NF(GPP_I3, NONE, PLTRST, NF1), // CPU_DP_D_HPD
|
||||
PAD_CFG_NF(GPP_I4, NONE, PLTRST, NF1), // G_DP_A_HPD_L
|
||||
PAD_CFG_GPO(GPP_I5, 0, DEEP), // GPIO_TBT_RESET
|
||||
PAD_NC(GPP_I6, NONE),
|
||||
PAD_NC(GPP_I7, NONE),
|
||||
PAD_NC(GPP_I8, NONE),
|
||||
PAD_NC(GPP_I9, NONE),
|
||||
PAD_NC(GPP_I10, NONE),
|
||||
PAD_CFG_GPI(GPP_I11, NONE, DEEP), // GPP_I_11_USB_OC4_N
|
||||
PAD_CFG_GPI(GPP_I12, NONE, DEEP), // GPP_I_12_USB_OC5_N
|
||||
PAD_CFG_GPI(GPP_I13, NONE, DEEP), // GPP_I_13_USB_OC6_N
|
||||
PAD_CFG_GPI(GPP_I14, NONE, DEEP), // GPP_I_14_USB_OC7_N
|
||||
PAD_NC(GPP_I15, NONE),
|
||||
PAD_NC(GPP_I16, NONE),
|
||||
PAD_NC(GPP_I17, NONE),
|
||||
PAD_CFG_GPO(GPP_I18, 0, DEEP), // No Reboot: L: disable H: enable
|
||||
PAD_NC(GPP_I19, NONE),
|
||||
PAD_NC(GPP_I20, NONE),
|
||||
PAD_NC(GPP_I21, NONE),
|
||||
PAD_CFG_GPO(GPP_I22, 0, DEEP), // BIOS fetch routing:
|
||||
// L: SPI (MAF) or eSPI Flash Ch (SAF)
|
||||
// H: eSPI Peripheral Ch
|
||||
|
||||
/* ------- GPIO Group GPP_J ------- */
|
||||
PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
|
||||
PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1), // CPU_C10_GATE_N
|
||||
PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), // CNVI_BRI_DT
|
||||
PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
|
||||
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_RGI_DT
|
||||
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
|
||||
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
|
||||
PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
|
||||
PAD_CFG_GPI(GPP_J8, NONE, DEEP), // VAL_TEST_SETUP_MENU
|
||||
PAD_NC(GPP_J9, NONE),
|
||||
PAD_NC(GPP_J10, NONE),
|
||||
PAD_NC(GPP_J11, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_K ------- */
|
||||
_PAD_CFG_STRUCT(GPP_K0, 0x42800100, 0x0000), // TBCIO_PLUG_EVENT#
|
||||
PAD_NC(GPP_K1, NONE),
|
||||
PAD_NC(GPP_K2, NONE),
|
||||
PAD_CFG_GPO(GPP_K3, 1, PLTRST), // TBT_RTD3_PWR_EN_R
|
||||
PAD_CFG_TERM_GPO(GPP_K4, 0, UP_20K, DEEP), // TBT_FORCE_PWR_R
|
||||
PAD_NC(GPP_K5, NONE),
|
||||
// GPP_K6 not in schematics
|
||||
// GPP_K7 not in schematics
|
||||
PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1), // VCCIN_AUX_VID0
|
||||
PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1), // VCCIN_AUX_VID1
|
||||
// GPP_K10 not in schematics
|
||||
PAD_NC(GPP_K11, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_R ------- */
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT / ME_WE
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#
|
||||
PAD_CFG_GPO(GPP_R5, 0, DEEP), // PCH_MUTE (XXX: SMART_AMP_EN)
|
||||
PAD_NC(GPP_R6, NONE),
|
||||
PAD_NC(GPP_R7, NONE),
|
||||
PAD_CFG_GPI(GPP_R8, NONE, DEEP), // DGPU_PWRGD_R
|
||||
PAD_CFG_NF(GPP_R9, NONE, DEEP, NF1), // PCH_EDP_HPD
|
||||
PAD_NC(GPP_R10, NONE),
|
||||
PAD_NC(GPP_R11, NONE),
|
||||
PAD_NC(GPP_R12, NONE),
|
||||
PAD_NC(GPP_R13, NONE),
|
||||
PAD_NC(GPP_R14, NONE),
|
||||
PAD_NC(GPP_R15, NONE),
|
||||
// GPP_R16 (DGPU_RST#_PCH) configured in bootblock
|
||||
PAD_NC(GPP_R17, NONE),
|
||||
PAD_NC(GPP_R18, NONE),
|
||||
PAD_CFG_GPI(GPP_R19, NONE, DEEP), // SCI#
|
||||
PAD_NC(GPP_R20, NONE),
|
||||
PAD_NC(GPP_R21, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_S ------- */
|
||||
PAD_NC(GPP_S0, NONE),
|
||||
PAD_NC(GPP_S1, NONE),
|
||||
PAD_NC(GPP_S2, NONE),
|
||||
PAD_NC(GPP_S3, NONE),
|
||||
PAD_NC(GPP_S4, NONE),
|
||||
PAD_NC(GPP_S5, NONE),
|
||||
PAD_NC(GPP_S6, NONE),
|
||||
PAD_NC(GPP_S7, NONE),
|
||||
};
|
||||
|
||||
void mainboard_configure_gpios(void)
|
||||
{
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
}
|
||||
16
src/mainboard/system76/rpl/variants/oryp12/gpio_early.c
Normal file
16
src/mainboard/system76/rpl/variants/oryp12/gpio_early.c
Normal file
@ -0,0 +1,16 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <mainboard/gpio.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
|
||||
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
|
||||
PAD_CFG_GPO(GPP_F9, 0, DEEP), // DGPU_PWR_EN
|
||||
PAD_CFG_GPO(GPP_R16, 0, DEEP), // DGPU_RST#_PCH
|
||||
};
|
||||
|
||||
void mainboard_configure_early_gpios(void)
|
||||
{
|
||||
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
|
||||
}
|
||||
41
src/mainboard/system76/rpl/variants/oryp12/hda_verb.c
Normal file
41
src/mainboard/system76/rpl/variants/oryp12/hda_verb.c
Normal file
@ -0,0 +1,41 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC1220 */
|
||||
0x10ec1220, /* Vendor ID */
|
||||
0x155866a6, /* Subsystem ID */
|
||||
24, /* Number of entries */
|
||||
|
||||
0x02050008, 0x020480cb, 0x02050008, 0x0204c0cb,
|
||||
|
||||
AZALIA_SUBVENDOR(0, 0x155866a6),
|
||||
AZALIA_RESET(1),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60120),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x04a11030),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40a7952d),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x411111f0),
|
||||
|
||||
0x05b50000, 0x05b43530, 0x05750002, 0x05741400,
|
||||
0x02050058, 0x02048ed1, 0x02050063, 0x0204e430,
|
||||
0x02050016, 0x02048020, 0x02050016, 0x02048020,
|
||||
0x02050043, 0x02043005, 0x02050058, 0x02048ed1,
|
||||
0x02050063, 0x0204e430, 0x05b50000, 0x05b43530,
|
||||
0x05750002, 0x05741400, 0x05b5000a, 0x05b45520,
|
||||
0x02050042, 0x020486cb, 0x0143b000, 0x01470740,
|
||||
0x02050036, 0x02042a6a, 0x02050008, 0x0204800b,
|
||||
0x02050007, 0x020403c3, 0x02050007, 0x020403c3,
|
||||
0x0205001b, 0x02044002, 0x0205001b, 0x02044002,
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
@ -0,0 +1,12 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef VARIANT_GPIO_H
|
||||
#define VARIANT_GPIO_H
|
||||
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#define DGPU_RST_N GPP_R16
|
||||
#define DGPU_PWR_EN GPP_F9
|
||||
#define DGPU_SSID 0x66a61558
|
||||
|
||||
#endif
|
||||
121
src/mainboard/system76/rpl/variants/oryp12/overridetree.cb
Normal file
121
src/mainboard/system76/rpl/variants/oryp12/overridetree.cb
Normal file
@ -0,0 +1,121 @@
|
||||
chip soc/intel/alderlake
|
||||
# Support 5600 MT/s memory
|
||||
register "max_dram_speed_mts" = "5600"
|
||||
|
||||
device domain 0 on
|
||||
subsystemid 0x1558 0x66a6 inherit
|
||||
|
||||
device ref xhci on
|
||||
register "usb2_ports" = "{
|
||||
[0] = USB2_PORT_MID(OC_SKIP), // J_AUD1
|
||||
[2] = USB2_PORT_MID(OC_SKIP), // J_TYPEC2
|
||||
[5] = USB2_PORT_MID(OC_SKIP), // J_USB1
|
||||
[7] = USB2_PORT_MID(OC_SKIP), // Camera
|
||||
[8] = USB2_PORT_MID(OC_SKIP), // J_TYPEC1 (TBT)
|
||||
[13] = USB2_PORT_MID(OC_SKIP), // Bluetooth
|
||||
}"
|
||||
register "usb3_ports" = "{
|
||||
[0] = USB3_PORT_DEFAULT(OC_SKIP), // J_AUD1
|
||||
[1] = USB3_PORT_DEFAULT(OC_SKIP), // J_USB1
|
||||
[3] = USB3_PORT_DEFAULT(OC_SKIP), // J_TYPEC2
|
||||
}"
|
||||
end
|
||||
|
||||
device ref i2c0 on
|
||||
# Touchpad I2C bus
|
||||
register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""ELAN0412""
|
||||
register "generic.desc" = ""ELAN Touchpad""
|
||||
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E7)"
|
||||
register "generic.detect" = "1"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 15 on end
|
||||
end
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""FTCS1000""
|
||||
register "generic.desc" = ""FocalTech Touchpad""
|
||||
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E7)"
|
||||
register "generic.detect" = "1"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 38 on end
|
||||
end
|
||||
end
|
||||
device ref i2c1 on
|
||||
# Thunderbolt
|
||||
register "serial_io_i2c_mode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
|
||||
end
|
||||
device ref i2c2 on
|
||||
# Pantone
|
||||
register "serial_io_i2c_mode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
|
||||
end
|
||||
device ref i2c3 on
|
||||
# TAS5825M smart amp
|
||||
register "serial_io_i2c_mode[PchSerialIoIndexI2C3]" = "PchSerialIoPci"
|
||||
chip drivers/i2c/tas5825m
|
||||
register "id" = "0"
|
||||
device i2c 4e on end # (8bit address: 0x9c)
|
||||
end
|
||||
end
|
||||
|
||||
device ref pcie5_0 on
|
||||
# GPU
|
||||
register "cpu_pcie_rp[CPU_RP(2)]" = "{
|
||||
.clk_src = 14,
|
||||
.clk_req = 14,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
end
|
||||
device ref pcie_rp3 on
|
||||
# GLAN
|
||||
register "pch_pcie_rp[PCH_RP(3)]" = "{
|
||||
.clk_src = 13,
|
||||
.clk_req = 13,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
end
|
||||
device ref pcie_rp5 on
|
||||
# CARD
|
||||
register "pch_pcie_rp[PCH_RP(5)]" = "{
|
||||
.clk_src = 12,
|
||||
.clk_req = 12,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG,
|
||||
}"
|
||||
end
|
||||
device ref pcie_rp8 on
|
||||
# WLAN
|
||||
register "pch_pcie_rp[PCH_RP(8)]" = "{
|
||||
.clk_src = 11,
|
||||
.clk_req = 11,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
end
|
||||
device ref pcie_rp9 on
|
||||
# SSD1
|
||||
register "pch_pcie_rp[PCH_RP(9)]" = "{
|
||||
.clk_src = 10,
|
||||
.clk_req = 10,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
end
|
||||
device ref pcie_rp13 on
|
||||
# SSD2
|
||||
register "pch_pcie_rp[PCH_RP(13)]" = "{
|
||||
.clk_src = 9,
|
||||
.clk_req = 9,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
end
|
||||
device ref pcie_rp25 on
|
||||
# TBT
|
||||
register "pch_pcie_rp[PCH_RP(25)]" = "{
|
||||
.clk_src = 15,
|
||||
.clk_req = 15,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER | PCIE_RP_HOTPLUG,
|
||||
}"
|
||||
chip drivers/intel/dtbt
|
||||
device pci 00.0 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
43
src/mainboard/system76/rpl/variants/oryp12/romstage.c
Normal file
43
src/mainboard/system76/rpl/variants/oryp12/romstage.c
Normal file
@ -0,0 +1,43 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <drivers/gfx/nvidia/gpu.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <soc/romstage.h>
|
||||
#include <variant/gpio.h>
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
{
|
||||
const struct mb_cfg board_cfg = {
|
||||
.type = MEM_TYPE_DDR5,
|
||||
.ect = true,
|
||||
.LpDdrDqDqsReTraining = 1,
|
||||
.ddr_config = {
|
||||
.dq_pins_interleaved = true,
|
||||
},
|
||||
};
|
||||
const struct mem_spd spd_info = {
|
||||
.topo = MEM_TOPO_DIMM_MODULE,
|
||||
.smbus = {
|
||||
[0] = { .addr_dimm[0] = 0x50, },
|
||||
[1] = { .addr_dimm[0] = 0x52, },
|
||||
},
|
||||
};
|
||||
const bool half_populated = false;
|
||||
|
||||
const struct nvidia_gpu_config config = {
|
||||
.power_gpio = DGPU_PWR_EN,
|
||||
.reset_gpio = DGPU_RST_N,
|
||||
.enable = true,
|
||||
};
|
||||
|
||||
// Enable dGPU power
|
||||
nvidia_set_power(&config);
|
||||
|
||||
// Set primary display to hybrid graphics
|
||||
mupd->FspmConfig.PrimaryDisplay = 4;
|
||||
|
||||
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
|
||||
mupd->FspmConfig.GpioOverride = 0;
|
||||
|
||||
memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
|
||||
}
|
||||
1053
src/mainboard/system76/rpl/variants/oryp12/tas5825m.c
Normal file
1053
src/mainboard/system76/rpl/variants/oryp12/tas5825m.c
Normal file
File diff suppressed because it is too large
Load Diff
Loading…
x
Reference in New Issue
Block a user