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CMOS: Add set_option and rework get_option.

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To ease some of my debugging pain on the unichrome, i decided i needed to
move FB size selection into cmos, so i could test a size and then reset it
to the default after loading this value so that the next reboot uses the
(working) default again. This meant implementing set_option in parallel to
get_option.

get_option was then found to have inversed argument ordering (like outb) and
passing char * and then depending on the cmos layout length, which made me
feel quite uncomfortable. Since we either have reserved space (which we
shouldn't do anything with in these two functions), an enum or a
hexadecimal value, unsigned int seemed like the way to go. So all users of
get_option now have their arguments inversed and switched from using ints
to unsigned ints now.

The way get_cmos_value was implemented forced us to not overlap byte and to
have multibyte values be byte aligned. This logic is now adapted to do a
full uint32_t read (when needed) at any offset and any length up to 32, and
the shifting all happens inside an uint32_t as well. set_cmos_value was
implemented similarly. Both routines have been extensively tested in a
quick separate little program as it is not easy to get this stuff right.

build_opt_tbl.c was altered to function correctly within these new
parameters. The enum value retrieval has been changed strol(..., NULL, 10)
to stroul(..., NULL, 0), so that we not only are able to use unsigned ints
now but so that we also interprete hex values correctly. The 32bit limit
gets imposed on all entries not marked reserved, an unused "user_data" field
that appeared in a lot of cmos.layouts has been changed to reserved as well.

Signed-off-by: Luc Verhaegen <libv@skynet.be>
Acked-by: Peter Stuge <peter@stuge.se>

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@4332 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Luc Verhaegen
2009-06-03 10:47:19 +00:00
parent a922b3195b
commit 9ceae905f1
81 changed files with 286 additions and 275 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/southbridge/amd/amd8111/amd8111_acpi.c
View File

@@ -76,7 +76,7 @@ static void acpi_init(struct device *dev)
uint16_t word;
uint16_t pm10_bar;
uint32_t dword;
int on;
uint32_t on;
#if 0
printk_debug("ACPI: disabling NMI watchdog.. ");
@@ -113,7 +113,7 @@ static void acpi_init(struct device *dev)
/* power on after power fail */
on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
get_option(&on, "power_on_after_fail");
get_option("power_on_after_fail", &on);
byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
byte &= ~0x40;
if (!on) {
@@ -130,7 +130,7 @@ static void acpi_init(struct device *dev)
/* Throttle the CPU speed down for testing */
on = SLOW_CPU_OFF;
get_option(&on, "slow_cpu");
get_option("slow_cpu", &on);
if(on) {
pm10_bar = (pci_read_config16(dev, 0x58)&0xff00);
outl(((on<<1)+0x10) ,(pm10_bar + 0x10));

4
src/southbridge/amd/amd8111/amd8111_lpc.c
View File

@@ -108,7 +108,7 @@ static void enable_hpet(struct device *dev)
static void lpc_init(struct device *dev)
{
uint8_t byte;
int nmi_option;
uint32_t nmi_option;
/* IO APIC initialization */
byte = pci_read_config8(dev, 0x4B);
@@ -142,7 +142,7 @@ static void lpc_init(struct device *dev)
byte |= (1 << 6); /* clear LPCERR */
pci_write_config8(dev, 0x40, byte);
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
get_option("nmi", &nmi_option);
if (nmi_option) {
byte |= (1 << 7); /* set NMI */
pci_write_config8(dev, 0x40, byte);

4
src/southbridge/amd/amd8131/amd8131_bridge.c
View File

@@ -278,7 +278,7 @@ static void amd8131_pcix_init(device_t dev)
uint32_t dword;
uint16_t word;
uint8_t byte;
int nmi_option;
uint32_t nmi_option;
/* Enable memory write and invalidate ??? */
byte = pci_read_config8(dev, 0x04);
@@ -323,7 +323,7 @@ static void amd8131_pcix_init(device_t dev)
/* NMI enable */
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
get_option("nmi", &nmi_option);
if(nmi_option) {
dword = pci_read_config32(dev, 0x44);
dword |= (1<<0);

4
src/southbridge/amd/sb600/sb600_sm.c
View File

@@ -165,7 +165,7 @@ static void sm_init(device_t dev)
/* power after power fail */
on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
get_option(&on, "power_on_after_fail");
get_option("power_on_after_fail", &on);
byte = pm_ioread(0x74);
byte &= ~0x03;
if (on) {
@@ -226,7 +226,7 @@ static void sm_init(device_t dev)
byte = inb(0x70); /* RTC70 */
byte_old = byte;
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
get_option("nmi", &nmi_option);
if (nmi_option) {
byte &= ~(1 << 7); /* set NMI */
printk_info("++++++++++set NMI+++++\n");

6
src/southbridge/broadcom/bcm5785/bcm5785_sb_pci_main.c
View File

@@ -23,7 +23,7 @@ static void sb_init(device_t dev)
{
uint8_t byte;
uint8_t byte_old;
int nmi_option;
uint32_t nmi_option;
uint32_t dword;
@@ -31,8 +31,8 @@ static void sb_init(device_t dev)
byte = inb(0x70); // RTC70
byte_old = byte;
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
if (nmi_option) {
get_option("nmi", &nmi_option);
if (nmi_option) {
byte &= ~(1 << 7); /* set NMI */
} else {
byte |= ( 1 << 7); // Can not mask NMI from PCI-E and NMI_NOW

4
src/southbridge/intel/esb6300/esb6300_lpc.c
View File

@@ -277,7 +277,7 @@ static void lpc_init(struct device *dev)
{
uint8_t byte;
uint32_t value;
int pwr_on=MAINBOARD_POWER_ON_AFTER_FAIL;
uint32_t pwr_on=MAINBOARD_POWER_ON_AFTER_FAIL;
/* sata settings */
pci_write_config32(dev, 0x58, 0x00001181);
@@ -326,7 +326,7 @@ static void lpc_init(struct device *dev)
esb6300_enable_lpc(dev);
get_option(&pwr_on, "power_on_after_fail");
get_option("power_on_after_fail", &pwr_on);
byte = pci_read_config8(dev, 0xa4);
byte &= 0xfe;
if (!pwr_on) {

4
src/southbridge/intel/i3100/i3100_lpc.c
View File

@@ -297,7 +297,7 @@ static void i3100_gpio_init(device_t dev)
static void lpc_init(struct device *dev)
{
u8 byte;
int pwr_on = MAINBOARD_POWER_ON_AFTER_FAIL;
uint32_t pwr_on = MAINBOARD_POWER_ON_AFTER_FAIL;
setup_ioapic(dev);
@@ -306,7 +306,7 @@ static void lpc_init(struct device *dev)
i3100_enable_serial_irqs(dev);
get_option(&pwr_on, "power_on_after_fail");
get_option("power_on_after_fail", &pwr_on);
byte = pci_read_config8(dev, 0xa4);
byte &= 0xfe;
if (!pwr_on) {

8
src/southbridge/intel/i82801ca/i82801ca_lpc.c
View File

@@ -88,7 +88,7 @@ void i82801ca_rtc_init(struct device *dev)
{
uint32_t dword;
int rtc_failed;
int pwr_on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
uint32_t pwr_on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
uint8_t pmcon3 = pci_read_config8(dev, GEN_PMCON_3);
rtc_failed = pmcon3 & RTC_BATTERY_DEAD;
@@ -99,7 +99,7 @@ void i82801ca_rtc_init(struct device *dev)
pmcon3 &= ~RTC_POWER_FAILED;
}
get_option(&pwr_on, "power_on_after_fail");
get_option("power_on_after_fail", &pwr_on);
pmcon3 &= ~SLEEP_AFTER_POWER_FAIL;
if (!pwr_on) {
pmcon3 |= SLEEP_AFTER_POWER_FAIL;
@@ -158,7 +158,7 @@ static void lpc_init(struct device *dev)
{
uint8_t byte;
int pwr_on=-1;
int nmi_option;
uint32_t nmi_option;
/* IO APIC initialization */
i82801ca_enable_ioapic(dev);
@@ -186,7 +186,7 @@ static void lpc_init(struct device *dev)
outb(byte, 0x61);
byte = inb(0x70);
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
get_option("nmi", &nmi_option);
if (nmi_option) {
byte &= ~(1 << 7); /* set NMI */
outb(byte, 0x70);

4
src/southbridge/intel/i82801dbm/i82801dbm_lpc.c
View File

@@ -119,7 +119,7 @@ static void lpc_init(struct device *dev)
{
uint8_t byte;
int pwr_on=-1;
int nmi_option;
uint32_t nmi_option;
/* IO APIC initialization */
i82801dbm_enable_ioapic(dev);
@@ -159,7 +159,7 @@ static void lpc_init(struct device *dev)
outb(byte, 0x61);
byte = inb(0x70);
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
get_option("nmi", &nmi_option);
if (nmi_option) {
byte &= ~(1 << 7); /* set NMI */
outb(byte, 0x70);

4
src/southbridge/intel/i82801er/i82801er_lpc.c
View File

@@ -283,7 +283,7 @@ static void lpc_init(struct device *dev)
{
uint8_t byte;
uint32_t value;
int pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
uint32_t pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
/* IO APIC initialization */
value = pci_read_config32(dev, 0xd0);
@@ -303,7 +303,7 @@ static void lpc_init(struct device *dev)
/* Clear SATA to non raid */
pci_write_config8(dev, 0xae, 0x00);
get_option(&pwr_on, "power_on_after_fail");
get_option("power_on_after_fail", &pwr_on);
byte = pci_read_config8(dev, 0xa4);
byte &= 0xfe;
if (!pwr_on) {

8
src/southbridge/intel/i82801gx/i82801gx_lpc.c
View File

@@ -185,14 +185,14 @@ static void i82801gx_power_options(device_t dev)
u8 reg8;
u16 reg16;
int pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
int nmi_option;
uint32_t pwr_on=MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
uint32_t nmi_option;
/* Which state do we want to goto after g3 (power restored)?
* 0 == S0 Full On
* 1 == S5 Soft Off
*/
get_option(&pwr_on, "power_on_after_fail");
get_option("power_on_after_fail", &pwr_on);
reg8 = pci_read_config8(dev, GEN_PMCON_3);
reg8 &= 0xfe;
if (pwr_on) {
@@ -216,7 +216,7 @@ static void i82801gx_power_options(device_t dev)
reg8 = inb(0x70);
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
get_option("nmi", &nmi_option);
if (nmi_option) {
printk_info ("NMI sources enabled.\n");
reg8 &= ~(1 << 7); /* Set NMI. */

4
src/southbridge/intel/i82801xx/i82801xx_lpc.c
View File

@@ -180,7 +180,7 @@ static void i82801xx_power_options(device_t dev)
{
uint8_t byte;
int pwr_on = -1;
int nmi_option;
uint32_t nmi_option;
/* power after power fail */
/* FIXME this doesn't work! */
@@ -199,7 +199,7 @@ static void i82801xx_power_options(device_t dev)
byte = inb(0x70);
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
get_option("nmi", &nmi_option);
if (nmi_option) {
byte &= ~(1 << 7); /* Set NMI. */
outb(byte, 0x70);

8
src/southbridge/intel/pxhd/pxhd_bridge.c
View File

@@ -38,12 +38,12 @@ static void pxhd_enable(device_t dev)
static unsigned int pxhd_scan_bridge(device_t dev, unsigned int max)
{
int bus_100Mhz = 0;
uint32_t bus_100Mhz = 0;
dev->link[0].dev = dev;
dev->links = 1;
get_option(&bus_100Mhz, "pxhd_bus_speed_100");
get_option("pxhd_bus_speed_100", &bus_100Mhz);
if(bus_100Mhz) {
uint16_t word;
@@ -66,7 +66,7 @@ static void pcix_init(device_t dev)
uint32_t dword;
uint16_t word;
uint8_t byte;
int nmi_option;
uint32_t nmi_option;
/* Bridge control ISA enable */
pci_write_config8(dev, 0x3e, 0x07);
@@ -115,7 +115,7 @@ static void pcix_init(device_t dev)
/* NMI enable */
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
get_option("nmi", &nmi_option);
if(nmi_option) {
dword = pci_read_config32(dev, 0x44);
dword |= (1<<0);

8
src/southbridge/nvidia/ck804/ck804_lpc.c
View File

@@ -179,7 +179,7 @@ unsigned pm_base=0;
static void lpc_init(device_t dev)
{
uint8_t byte, byte_old;
int on, nmi_option;
uint32_t on, nmi_option;
lpc_common_init(dev);
@@ -199,7 +199,7 @@ static void lpc_init(device_t dev)
/* power after power fail */
on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
get_option(&on, "power_on_after_fail");
get_option("power_on_after_fail", &on);
byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
byte &= ~0x40;
if (!on)
@@ -209,7 +209,7 @@ static void lpc_init(device_t dev)
/* Throttle the CPU speed down for testing. */
on = SLOW_CPU_OFF;
get_option(&on, "slow_cpu");
get_option("slow_cpu", &on);
if (on) {
uint16_t pm10_bar;
uint32_t dword;
@@ -238,7 +238,7 @@ static void lpc_init(device_t dev)
byte = inb(0x70); /* RTC70 */
byte_old = byte;
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
get_option("nmi", &nmi_option);
if (nmi_option) {
byte &= ~(1 << 7); /* Set NMI. */
} else {

10
src/southbridge/nvidia/mcp55/mcp55_lpc.c
View File

@@ -170,8 +170,8 @@ static void lpc_init(device_t dev)
{
uint8_t byte;
uint8_t byte_old;
int on;
int nmi_option;
uint32_t on;
uint32_t nmi_option;
lpc_common_init(dev, 1);
@@ -184,7 +184,7 @@ static void lpc_init(device_t dev)
#if 1
on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
get_option(&on, "power_on_after_fail");
get_option("power_on_after_fail", &on);
byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
byte &= ~0x40;
if (!on) {
@@ -195,7 +195,7 @@ static void lpc_init(device_t dev)
#endif
/* Throttle the CPU speed down for testing */
on = SLOW_CPU_OFF;
get_option(&on, "slow_cpu");
get_option("slow_cpu", &on);
if(on) {
uint16_t pm10_bar;
uint32_t dword;
@@ -225,7 +225,7 @@ static void lpc_init(device_t dev)
byte = inb(0x70); // RTC70
byte_old = byte;
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
get_option("nmi", &nmi_option);
if (nmi_option) {
byte &= ~(1 << 7); /* set NMI */
} else {

10
src/southbridge/sis/sis966/sis966_lpc.c
View File

@@ -167,8 +167,8 @@ static void lpc_init(device_t dev)
{
uint8_t byte;
uint8_t byte_old;
int on;
int nmi_option;
uint32_t on;
uint32_t nmi_option;
printk_debug("LPC_INIT -------->\n");
init_pc_keyboard(0x60, 0x64, 0);
@@ -180,7 +180,7 @@ static void lpc_init(device_t dev)
on = MAINBOARD_POWER_ON_AFTER_POWER_FAIL;
get_option(&on, "power_on_after_fail");
get_option("power_on_after_fail", &on);
byte = pci_read_config8(dev, PREVIOUS_POWER_STATE);
byte &= ~0x40;
if (!on) {
@@ -191,7 +191,7 @@ static void lpc_init(device_t dev)
/* Throttle the CPU speed down for testing */
on = SLOW_CPU_OFF;
get_option(&on, "slow_cpu");
get_option("slow_cpu", &on);
if(on) {
uint16_t pm10_bar;
uint32_t dword;
@@ -213,7 +213,7 @@ static void lpc_init(device_t dev)
byte = inb(0x70); // RTC70
byte_old = byte;
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
get_option("nmi", &nmi_option);
if (nmi_option) {
byte &= ~(1 << 7); /* set NMI */
} else {