nb/intel: Remove space between function name and '('

Change-Id: Ibffaf86f9e32d747c8f2f7a3643df8935fb00047
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77763
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>

src/northbridge/intel/gm45/raminit.c

@@ -733,7 +733,7 @@ static void collect_dimm_config(sysinfo_t *const sysinfo)
 	for (i = 0; i < 4; i++)
 		if (sysinfo->spd_map[i]) {
 			const u8 spd = smbus_read_byte(sysinfo->spd_map[i], 2);
-			printk (BIOS_DEBUG, "%x:%x:%x\n",
+			printk(BIOS_DEBUG, "%x:%x:%x\n",
 				i, sysinfo->spd_map[i],
 				spd);
 			if ((spd == 7) || (spd == 8) || (spd == 0xb)) {

src/northbridge/intel/haswell/broadwell_mrc/pei_data.h

@@ -9,7 +9,7 @@
 
 #define ABI_X86 __attribute__((regparm(0)))
 
-typedef void ABI_X86 (*tx_byte_func)(unsigned char byte);
+typedef void ABI_X86(*tx_byte_func)(unsigned char byte);
 
 enum board_type {
 	BOARD_TYPE_CRB_MOBILE = 0,	/* CRB Mobile */

src/northbridge/intel/haswell/broadwell_mrc/raminit.c

@@ -90,7 +90,7 @@ static void report_memory_config(void)
 	}
 }
 
-typedef int ABI_X86 (*pei_wrapper_entry_t)(struct pei_data *pei_data);
+typedef int ABI_X86(*pei_wrapper_entry_t)(struct pei_data *pei_data);
 
 static void ABI_X86 send_to_console(unsigned char b)
 {

src/northbridge/intel/haswell/report_platform.c

@@ -90,7 +90,7 @@ static void report_pch_info(void)
 			break;
 		}
 	}
-	printk (BIOS_DEBUG, "PCH type: %s, device id: %x, rev id %x\n",
+	printk(BIOS_DEBUG, "PCH type: %s, device id: %x, rev id %x\n",
 		pch_type, dev_id, pci_read_config8(PCH_LPC_DEV, 8));
 }
 

src/northbridge/intel/ironlake/quickpath.c

@@ -611,9 +611,9 @@ void late_quickpath_init(struct raminfo *info, const int s3resume)
 	if (deven & 8) {
 		mchbar_setbits32(0xff8, 3 << 11);
 		mchbar_clrbits32(0x2cb0, ~0);
-		pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4c);
-		pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4c);
-		pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4e);
+		pci_read_config8(PCI_DEV(0, 0x2, 0x0), 0x4c);
+		pci_read_config8(PCI_DEV(0, 0x2, 0x0), 0x4c);
+		pci_read_config8(PCI_DEV(0, 0x2, 0x0), 0x4e);
 
 		mchbar_read8(0x1150);
 		mchbar_read8(0x1151);

src/northbridge/intel/ironlake/raminit.c

@@ -34,7 +34,7 @@
 
 #define NORTHBRIDGE PCI_DEV(0, 0, 0)
 #define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
-#define GMA PCI_DEV (0, 0x2, 0x0)
+#define GMA PCI_DEV(0, 0x2, 0x0)
 
 #define FOR_ALL_RANKS					   \
   for (channel = 0; channel < NUM_CHANNELS; channel++)	   \
@@ -134,7 +134,7 @@ static u32 gav_real(int line, u32 in)
 	return in;
 }
 
-#define gav(x) gav_real (__LINE__, (x))
+#define gav(x) gav_real(__LINE__, (x))
 
 /* Global allocation of timings_car */
 timing_bounds_t timings_car[64];

src/northbridge/intel/sandybridge/raminit.c

@@ -153,7 +153,7 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl)
 	int channel, slot, spd_slot;
 	bool can_use_ecc = ctrl->ecc_supported;
 
-	memset (ctrl->rankmap, 0, sizeof(ctrl->rankmap));
+	memset(ctrl->rankmap, 0, sizeof(ctrl->rankmap));
 
 	ctrl->extended_temperature_range = 1;
 	ctrl->auto_self_refresh = 1;

src/northbridge/intel/sandybridge/raminit_mrc.c

@@ -156,7 +156,7 @@ static void sdram_initialize(struct pei_data *pei_data)
 	entry = cbfs_map("mrc.bin", NULL);
 	if (entry) {
 		int rv;
-		rv = entry (pei_data);
+		rv = entry(pei_data);
 		if (rv) {
 			switch (rv) {
 			case -1:

src/northbridge/intel/x4x/raminit.h

@@ -76,7 +76,7 @@
 #define FOR_EACH_BYTELANE(l) \
 	for (l = 0; l < TOTAL_BYTELANES; l++)
 #define FOR_EACH_POPULATED_CHANNEL_AND_BYTELANE(dimms, ch, l) \
-	FOR_EACH_POPULATED_CHANNEL (dimms, ch) FOR_EACH_BYTELANE(l)
+	FOR_EACH_POPULATED_CHANNEL(dimms, ch) FOR_EACH_BYTELANE(l)
 
 #define DDR3_MAX_CAS 18