nb/intel: Remove space between function name and '('
Change-Id: Ibffaf86f9e32d747c8f2f7a3643df8935fb00047 Signed-off-by: Elyes Haouas <ehaouas@noos.fr> Reviewed-on: https://review.coreboot.org/c/coreboot/+/77763 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
This commit is contained in:
committed by
Martin L Roth
parent
98a9b34854
commit
9d450b2248
@@ -733,7 +733,7 @@ static void collect_dimm_config(sysinfo_t *const sysinfo)
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for (i = 0; i < 4; i++)
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if (sysinfo->spd_map[i]) {
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const u8 spd = smbus_read_byte(sysinfo->spd_map[i], 2);
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printk (BIOS_DEBUG, "%x:%x:%x\n",
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printk(BIOS_DEBUG, "%x:%x:%x\n",
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i, sysinfo->spd_map[i],
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spd);
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if ((spd == 7) || (spd == 8) || (spd == 0xb)) {
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@@ -9,7 +9,7 @@
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#define ABI_X86 __attribute__((regparm(0)))
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typedef void ABI_X86 (*tx_byte_func)(unsigned char byte);
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typedef void ABI_X86(*tx_byte_func)(unsigned char byte);
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enum board_type {
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BOARD_TYPE_CRB_MOBILE = 0, /* CRB Mobile */
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@@ -90,7 +90,7 @@ static void report_memory_config(void)
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}
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}
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typedef int ABI_X86 (*pei_wrapper_entry_t)(struct pei_data *pei_data);
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typedef int ABI_X86(*pei_wrapper_entry_t)(struct pei_data *pei_data);
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static void ABI_X86 send_to_console(unsigned char b)
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{
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@@ -90,7 +90,7 @@ static void report_pch_info(void)
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break;
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}
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}
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printk (BIOS_DEBUG, "PCH type: %s, device id: %x, rev id %x\n",
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printk(BIOS_DEBUG, "PCH type: %s, device id: %x, rev id %x\n",
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pch_type, dev_id, pci_read_config8(PCH_LPC_DEV, 8));
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}
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@@ -611,9 +611,9 @@ void late_quickpath_init(struct raminfo *info, const int s3resume)
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if (deven & 8) {
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mchbar_setbits32(0xff8, 3 << 11);
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mchbar_clrbits32(0x2cb0, ~0);
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pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4c);
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pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4c);
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pci_read_config8(PCI_DEV (0, 0x2, 0x0), 0x4e);
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pci_read_config8(PCI_DEV(0, 0x2, 0x0), 0x4c);
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pci_read_config8(PCI_DEV(0, 0x2, 0x0), 0x4c);
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pci_read_config8(PCI_DEV(0, 0x2, 0x0), 0x4e);
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mchbar_read8(0x1150);
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mchbar_read8(0x1151);
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@@ -34,7 +34,7 @@
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#define NORTHBRIDGE PCI_DEV(0, 0, 0)
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#define SOUTHBRIDGE PCI_DEV(0, 0x1f, 0)
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#define GMA PCI_DEV (0, 0x2, 0x0)
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#define GMA PCI_DEV(0, 0x2, 0x0)
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#define FOR_ALL_RANKS \
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for (channel = 0; channel < NUM_CHANNELS; channel++) \
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@@ -134,7 +134,7 @@ static u32 gav_real(int line, u32 in)
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return in;
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}
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#define gav(x) gav_real (__LINE__, (x))
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#define gav(x) gav_real(__LINE__, (x))
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/* Global allocation of timings_car */
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timing_bounds_t timings_car[64];
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@@ -153,7 +153,7 @@ static void dram_find_spds_ddr3(spd_raw_data *spd, ramctr_timing *ctrl)
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int channel, slot, spd_slot;
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bool can_use_ecc = ctrl->ecc_supported;
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memset (ctrl->rankmap, 0, sizeof(ctrl->rankmap));
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memset(ctrl->rankmap, 0, sizeof(ctrl->rankmap));
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ctrl->extended_temperature_range = 1;
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ctrl->auto_self_refresh = 1;
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@@ -156,7 +156,7 @@ static void sdram_initialize(struct pei_data *pei_data)
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entry = cbfs_map("mrc.bin", NULL);
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if (entry) {
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int rv;
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rv = entry (pei_data);
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rv = entry(pei_data);
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if (rv) {
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switch (rv) {
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case -1:
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@@ -76,7 +76,7 @@
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#define FOR_EACH_BYTELANE(l) \
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for (l = 0; l < TOTAL_BYTELANES; l++)
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#define FOR_EACH_POPULATED_CHANNEL_AND_BYTELANE(dimms, ch, l) \
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FOR_EACH_POPULATED_CHANNEL (dimms, ch) FOR_EACH_BYTELANE(l)
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FOR_EACH_POPULATED_CHANNEL(dimms, ch) FOR_EACH_BYTELANE(l)
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#define DDR3_MAX_CAS 18
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