soc/intel/common: Include Meteor Lake device IDs

Reference: chapter2 in Meteor Lake EDS vol1 (640228)

Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ie71abb70b88db0acec8a320c3e2c20c54bbb4a8a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/62581
Reviewed-by: Subrata Banik <subratabanik@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/drivers/intel/ish/ish.c

@@ -51,6 +51,7 @@ static const struct device_operations pci_ish_device_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_MTL_ISHB,
 	PCI_DID_INTEL_CNL_ISHB,
 	PCI_DID_INTEL_CML_ISHB,
 	PCI_DID_INTEL_TGL_ISHB,

src/include/cpu/intel/cpu_ids.h

@@ -56,5 +56,6 @@
 #define CPUID_ALDERLAKE_A2		0x906a2
 #define CPUID_ALDERLAKE_A3		0x906a4
 #define CPUID_ALDERLAKE_N_A0		0xb06e0
-
+#define CPUID_METEORLAKE_A0_1		0xa06a0
+#define CPUID_METEORLAKE_A0_2		0xa06a1
 #endif /* CPU_INTEL_CPU_IDS_H */

src/include/device/pci_ids.h

@@ -2180,6 +2180,7 @@
 #define PCI_DID_INTEL_CML_ISHB		0x02fc
 #define PCI_DID_INTEL_TGL_ISHB		0xa0fc
 #define PCI_DID_INTEL_TGL_H_ISHB	0x43fc
+#define PCI_DID_INTEL_MTL_ISHB		0x7e45
 
 /* Intel 82371FB (PIIX) */
 #define PCI_DID_INTEL_82371FB_ISA		0x122e
@@ -3074,6 +3075,14 @@
 #define PCI_DID_INTEL_ADP_M_N_ESPI_31			0x549f
 #define PCI_DID_INTEL_ADP_M_ESPI_32			0x5186
 #define PCI_DID_INTEL_SPR_ESPI_1			0x1b80
+#define PCI_DID_INTEL_MTL_ESPI_0			0x7e00
+#define PCI_DID_INTEL_MTL_ESPI_1			0x7e01
+#define PCI_DID_INTEL_MTL_ESPI_2			0x7e02
+#define PCI_DID_INTEL_MTL_ESPI_3			0x7e03
+#define PCI_DID_INTEL_MTL_ESPI_4			0x7e04
+#define PCI_DID_INTEL_MTL_ESPI_5			0x7e05
+#define PCI_DID_INTEL_MTL_ESPI_6			0x7e06
+#define PCI_DID_INTEL_MTL_ESPI_7			0x7e07
 
 /* Intel PCIE device ids  */
 #define PCI_DID_INTEL_LPT_H_PCIE_RP1			0x8c10
@@ -3411,6 +3420,19 @@
 #define PCI_DID_INTEL_ADP_N_PCIE_RP11			0x54b2
 #define PCI_DID_INTEL_ADP_N_PCIE_RP12			0x54b3
 
+#define PCI_DID_INTEL_MTL_SOC_PCIE_RP1			0x7e38
+#define PCI_DID_INTEL_MTL_SOC_PCIE_RP2			0x7e39
+#define PCI_DID_INTEL_MTL_SOC_PCIE_RP3			0x7e3a
+#define PCI_DID_INTEL_MTL_SOC_PCIE_RP4			0x7e3b
+#define PCI_DID_INTEL_MTL_SOC_PCIE_RP5			0x7e3c
+#define PCI_DID_INTEL_MTL_SOC_PCIE_RP6			0x7e3d
+#define PCI_DID_INTEL_MTL_SOC_PCIE_RP7			0x7e3e
+#define PCI_DID_INTEL_MTL_SOC_PCIE_RP8			0x7e3f
+#define PCI_DID_INTEL_MTL_SOC_PCIE_RP9			0x7e4d
+#define PCI_DID_INTEL_MTL_IOE_P_PCIE_RP10		0x7eca
+#define PCI_DID_INTEL_MTL_IOE_P_PCIE_RP11		0x7ecb
+#define PCI_DID_INTEL_MTL_IOE_P_PCIE_RP12		0x7ecc
+
 /* Intel SATA device Ids */
 #define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_IDE			0x8c00
 #define PCI_DID_INTEL_LPT_H_DESKTOP_SATA_AHCI			0x8c02
@@ -3482,6 +3504,7 @@
 #define PCI_DID_INTEL_ADP_M_SATA_1		0x54d3
 #define PCI_DID_INTEL_ADP_M_SATA_2		0x54d7
 #define PCI_DID_INTEL_ADP_M_SATA_3		0x282a
+#define PCI_DID_INTEL_MTL_SATA			0x7e63
 
 /* Intel PMC device Ids */
 #define PCI_DID_INTEL_SPT_LP_PMC		0x9d21
@@ -3503,6 +3526,9 @@
 #define PCI_DID_INTEL_ADP_P_PMC			0x7a21
 #define PCI_DID_INTEL_ADP_S_PMC			0x7aa1
 #define PCI_DID_INTEL_ADP_M_N_PMC		0x54a1
+#define PCI_DID_INTEL_MTL_SOC_PMC		0x7e21
+#define PCI_DID_INTEL_MTL_IOE_M_PMC		0x7ebe
+#define PCI_DID_INTEL_MTL_IOE_P_PMC		0x7ece
 
 /* Intel I2C device Ids */
 #define PCI_DID_INTEL_LPT_LP_I2C0		0x9c61
@@ -3613,6 +3639,13 @@
 #define PCI_DID_INTEL_ADP_M_N_I2C4		0x54c5
 #define PCI_DID_INTEL_ADP_M_N_I2C5		0x54c6
 
+#define PCI_DID_INTEL_MTL_I2C0			0x7e78
+#define PCI_DID_INTEL_MTL_I2C1			0x7e79
+#define PCI_DID_INTEL_MTL_I2C2			0x7e7a
+#define PCI_DID_INTEL_MTL_I2C3			0x7e7b
+#define PCI_DID_INTEL_MTL_I2C4			0x7e50
+#define PCI_DID_INTEL_MTL_I2C5			0x7e51
+
 /* Intel UART device Ids */
 #define PCI_DID_INTEL_LPT_LP_UART0		0x9c63
 #define PCI_DID_INTEL_LPT_LP_UART1		0x9c64
@@ -3683,6 +3716,10 @@
 #define PCI_DID_INTEL_ADP_M_N_UART2		0x54c7
 #define PCI_DID_INTEL_ADP_M_N_UART3		0x54da
 
+#define PCI_DID_INTEL_MTL_UART0			0x7e25
+#define PCI_DID_INTEL_MTL_UART1			0x7e26
+#define PCI_DID_INTEL_MTL_UART2			0x7e52
+
 /* Intel SPI device Ids */
 #define PCI_DID_INTEL_LPT_LP_GSPI0		0x9c65
 #define PCI_DID_INTEL_LPT_LP_GSPI1		0x9c66
@@ -3765,6 +3802,11 @@
 
 #define PCI_DID_INTEL_SPR_HWSEQ_SPI		0x1bca
 
+#define PCI_DID_INTEL_MTL_HWSEQ_SPI		0x7e23
+#define PCI_DID_INTEL_MTL_GSPI0			0x7e27
+#define PCI_DID_INTEL_MTL_GSPI1			0x7e30
+#define PCI_DID_INTEL_MTL_GSPI2			0x7e46
+
 /* Intel IGD device Ids */
 #define PCI_DID_INTEL_SKL_GT1F_DT2			0x1902
 #define PCI_DID_INTEL_SKL_GT1_SULTM			0x1906
@@ -3913,6 +3955,9 @@
 #define PCI_DID_INTEL_ADL_N_GT1				0x46D0
 #define PCI_DID_INTEL_ADL_N_GT2				0x46D1
 #define PCI_DID_INTEL_ADL_N_GT3				0x46D2
+#define PCI_DID_INTEL_MTL_M_GT2				0x7d40
+#define PCI_DID_INTEL_MTL_P_GT2_1			0x7d50
+#define PCI_DID_INTEL_MTL_P_GT2_2			0x7d60
 
 
 /* Intel Northbridge Ids */
@@ -4030,6 +4075,9 @@
 #define PCI_DID_INTEL_ADL_N_ID_2		0x461B
 #define PCI_DID_INTEL_ADL_N_ID_3		0x461c
 #define PCI_DID_INTEL_ADL_N_ID_4		0x4614
+#define PCI_DID_INTEL_MTL_M_ID			0x7D00
+#define PCI_DID_INTEL_MTL_P_ID_1		0x7D01
+#define PCI_DID_INTEL_MTL_P_ID_2		0x7D02
 
 /* Intel SMBUS device Ids */
 #define PCI_DID_INTEL_LPT_H_SMBUS			0x8c22
@@ -4052,6 +4100,7 @@
 #define PCI_DID_INTEL_ADP_P_SMBUS			0xa0a3
 #define PCI_DID_INTEL_ADP_S_SMBUS			0x7aa3
 #define PCI_DID_INTEL_ADP_M_N_SMBUS			0x54a3
+#define PCI_DID_INTEL_MTL_SMBUS				0x7e22
 
 /* Intel EHCI device IDs */
 #define PCI_DID_INTEL_LPT_H_EHCI_1		0x8c26
@@ -4083,6 +4132,9 @@
 #define PCI_DID_INTEL_ADP_S_XHCI		0x7ae0
 #define PCI_DID_INTEL_ADP_TCSS_XHCI		0x461e
 #define PCI_DID_INTEL_ADP_M_XHCI		0x54ed
+#define PCI_DID_INTEL_MTL_XHCI			0x7e7d
+#define PCI_DID_INTEL_MTL_M_TCSS_XHCI		0x7eb0
+#define PCI_DID_INTEL_MTL_P_TCSS_XHCI		0x7ec0
 
 /* Intel P2SB device Ids */
 #define PCI_DID_INTEL_APL_P2SB			0x5a92
@@ -4104,6 +4156,9 @@
 #define PCI_DID_INTEL_ADP_P_P2SB		0x7a20
 #define PCI_DID_INTEL_ADP_S_P2SB		0x7aa0
 #define PCI_DID_INTEL_ADP_M_P2SB          0x54a0
+#define PCI_DID_INTEL_MTL_SOC_P2SB		0x7e20
+#define PCI_DID_INTEL_MTL_IOE_M_P2SB		0x7eb8
+#define PCI_DID_INTEL_MTL_IOE_P_P2SB		0x7ec8
 
 /* Intel SRAM device Ids */
 #define PCI_DID_INTEL_APL_SRAM			0x5aec
@@ -4116,6 +4171,9 @@
 #define PCI_DID_INTEL_TGL_H_SRAM		0x43ef
 #define PCI_DID_INTEL_MCC_SRAM			0x4b7f
 #define PCI_DID_INTEL_JSP_SRAM			0x4def
+#define PCI_DID_INTEL_MTL_SOC_SRAM		0x7e7f
+#define PCI_DID_INTEL_MTL_IOE_M_SRAM		0x7ebf
+#define PCI_DID_INTEL_MTL_IOE_P_SRAM		0x7ecf
 
 /* Intel AUDIO device Ids */
 #define PCI_DID_INTEL_LPT_H_AUDIO		0x8c20
@@ -4155,6 +4213,15 @@
 #define PCI_DID_INTEL_ADP_M_N_AUDIO_6		0x54cd
 #define PCI_DID_INTEL_ADP_M_N_AUDIO_7		0x54ce
 
+#define PCI_DID_INTEL_MTL_AUDIO_1		0x7e28
+#define PCI_DID_INTEL_MTL_AUDIO_2		0x7e29
+#define PCI_DID_INTEL_MTL_AUDIO_3		0x7e2a
+#define PCI_DID_INTEL_MTL_AUDIO_4		0x7e2b
+#define PCI_DID_INTEL_MTL_AUDIO_5		0x7e2c
+#define PCI_DID_INTEL_MTL_AUDIO_6		0x7e2d
+#define PCI_DID_INTEL_MTL_AUDIO_7		0x7e2e
+#define PCI_DID_INTEL_MTL_AUDIO_8		0x7e2f
+
 /* Intel HECI/ME device Ids */
 #define PCI_DID_INTEL_LPT_H_MEI			0x8c3a
 #define PCI_DID_INTEL_LPT_LP_MEI		0x9c3a
@@ -4194,6 +4261,7 @@
 #define PCI_DID_INTEL_ADP_M_CSE1		0x54e1
 #define PCI_DID_INTEL_ADP_M_CSE2		0x54e4
 #define PCI_DID_INTEL_ADP_M_CSE3		0x54e5
+#define PCI_DID_INTEL_MTL_CSE0			0x7e70
 
 /* Intel XDCI device Ids */
 #define PCI_DID_INTEL_APL_XDCI			0x5aaa
@@ -4213,6 +4281,9 @@
 #define PCI_DID_INTEL_ADP_S_XDCI		0x7ae1
 #define PCI_DID_INTEL_ADP_TCSS_XDCI		0x460e
 #define PCI_DID_INTEL_ADP_M_XDCI		0x54ee
+#define PCI_DID_INTEL_MTL_XDCI			0x7e7e
+#define PCI_DID_INTEL_MTL_M_TCSS_XDCI		0x7eb1
+#define PCI_DID_INTEL_MTL_P_TCSS_XDCI		0x7ec1
 
 /* Intel SD device Ids */
 #define PCI_DID_INTEL_LPT_LP_SD			0x9c35
@@ -4255,6 +4326,15 @@
 #define PCI_DID_INTEL_TGL_H_TBT_DMA1		0x9a21
 #define PCI_DID_INTEL_ADL_TBT_DMA0		0x463e
 #define PCI_DID_INTEL_ADL_TBT_DMA1		0x466d
+#define PCI_DID_INTEL_MTL_M_TBT_RP0		0x7eb4
+#define PCI_DID_INTEL_MTL_M_TBT_RP1		0x7eb5
+#define PCI_DID_INTEL_MTL_P_TBT_RP0		0x7ec4
+#define PCI_DID_INTEL_MTL_P_TBT_RP1		0x7ec5
+#define PCI_DID_INTEL_MTL_P_TBT_RP2		0x7ec6
+#define PCI_DID_INTEL_MTL_P_TBT_RP3		0x7ec7
+#define PCI_DID_INTEL_MTL_M_TBT_DMA0		0x7eb2
+#define PCI_DID_INTEL_MTL_P_TBT_DMA0		0x7ec2
+#define PCI_DID_INTEL_MTL_P_TBT_DMA1		0x7ec3
 
 /* Intel WIFI Ids */
 #define PCI_DID_1000_SERIES_WIFI		0x0084
@@ -4293,12 +4373,14 @@
 #define PCI_DID_INTEL_JSL_IPU			0x4e19
 #define PCI_DID_INTEL_ADL_IPU			0x465d
 #define PCI_DID_INTEL_ADL_N_IPU			0x462e
+#define PCI_DID_INTEL_MTL_IPU			0x7d19
 
 /* Intel Dynamic Tuning Technology Device */
 #define PCI_DID_INTEL_CML_DTT			0x1903
 #define PCI_DID_INTEL_TGL_DTT			0x9A03
 #define PCI_DID_INTEL_JSL_DTT			0x4E03
 #define PCI_DID_INTEL_ADL_DTT			0x461d
+#define PCI_DID_INTEL_MTL_DTT			0x7d03
 
 /* Intel CNVi WiFi/BT device IDs */
 #define PCI_DID_INTEL_CML_LP_CNVI_WIFI		0x02f0
@@ -4330,6 +4412,10 @@
 #define PCI_DID_INTEL_ADL_N_CNVI_WIFI_1		0x54f1
 #define PCI_DID_INTEL_ADL_N_CNVI_WIFI_2		0x54f2
 #define PCI_DID_INTEL_ADL_N_CNVI_WIFI_3		0x54f3
+#define PCI_DID_INTEL_MTL_CNVI_WIFI_0		0x7e40
+#define PCI_DID_INTEL_MTL_CNVI_WIFI_1		0x7e41
+#define PCI_DID_INTEL_MTL_CNVI_WIFI_2		0x7e42
+#define PCI_DID_INTEL_MTL_CNVI_WIFI_3		0x7e43
 
 /* Intel Crashlog */
 #define PCI_DID_INTEL_TGL_CPU_CRASHLOG_SRAM		0x9a0d
@@ -4338,6 +4424,7 @@
 #define PCI_DID_INTEL_ADP_P_PMC_CRASHLOG_SRAM		0x51ef
 #define PCI_DID_INTEL_ADP_N_PMC_CRASHLOG_SRAM		0x54ef
 #define PCI_DID_INTEL_TGP_PMC_CRASHLOG_SRAM		0xa0ef
+#define PCI_DID_INTEL_MTL_CRASHLOG_SRAM			0x7d0d
 
 #define PCI_VID_COMPUTONE		0x8e0e
 #define PCI_DID_COMPUTONE_IP2EX		0x0291

src/soc/intel/common/block/cnvi/cnvi.c

@@ -21,6 +21,10 @@ static struct device_operations cnvi_wifi_ops = {
 };
 
 static const unsigned short wifi_pci_device_ids[] = {
+	PCI_DID_INTEL_MTL_CNVI_WIFI_0,
+	PCI_DID_INTEL_MTL_CNVI_WIFI_1,
+	PCI_DID_INTEL_MTL_CNVI_WIFI_2,
+	PCI_DID_INTEL_MTL_CNVI_WIFI_3,
 	PCI_DID_INTEL_CML_LP_CNVI_WIFI,
 	PCI_DID_INTEL_CML_H_CNVI_WIFI,
 	PCI_DID_INTEL_CNL_LP_CNVI_WIFI,

src/soc/intel/common/block/cpu/mp_init.c

@@ -28,6 +28,8 @@ static struct device_operations cpu_dev_ops = {
 };
 
 static const struct cpu_device_id cpu_table[] = {
+	{ X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_1},
+	{ X86_VENDOR_INTEL, CPUID_METEORLAKE_A0_2},
 	{ X86_VENDOR_INTEL, CPUID_SKYLAKE_C0 },
 	{ X86_VENDOR_INTEL, CPUID_SKYLAKE_D0 },
 	{ X86_VENDOR_INTEL, CPUID_SKYLAKE_HQ0 },

src/soc/intel/common/block/cse/cse.c

@@ -1257,6 +1257,7 @@ static struct device_operations cse_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_MTL_CSE0,
 	PCI_DID_INTEL_APL_CSE0,
 	PCI_DID_INTEL_GLK_CSE0,
 	PCI_DID_INTEL_CNL_CSE0,

src/soc/intel/common/block/dsp/dsp.c

@@ -13,6 +13,14 @@ static struct device_operations dsp_dev_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_MTL_AUDIO_1,
+	PCI_DID_INTEL_MTL_AUDIO_2,
+	PCI_DID_INTEL_MTL_AUDIO_3,
+	PCI_DID_INTEL_MTL_AUDIO_4,
+	PCI_DID_INTEL_MTL_AUDIO_5,
+	PCI_DID_INTEL_MTL_AUDIO_6,
+	PCI_DID_INTEL_MTL_AUDIO_7,
+	PCI_DID_INTEL_MTL_AUDIO_8,
 	PCI_DID_INTEL_APL_AUDIO,
 	PCI_DID_INTEL_CNL_AUDIO,
 	PCI_DID_INTEL_GLK_AUDIO,

src/soc/intel/common/block/dtt/dtt.c

@@ -5,6 +5,7 @@
 #include <device/pci_ids.h>
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_MTL_DTT,
 	PCI_DID_INTEL_CML_DTT,
 	PCI_DID_INTEL_TGL_DTT,
 	PCI_DID_INTEL_JSL_DTT,

src/soc/intel/common/block/graphics/graphics.c

@@ -177,6 +177,9 @@ static const struct device_operations graphics_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_MTL_M_GT2,
+	PCI_DID_INTEL_MTL_P_GT2_1,
+	PCI_DID_INTEL_MTL_P_GT2_2,
 	PCI_DID_INTEL_APL_IGD_HD_505,
 	PCI_DID_INTEL_APL_IGD_HD_500,
 	PCI_DID_INTEL_CNL_GT2_ULX_1,

src/soc/intel/common/block/hda/hda.c

@@ -21,6 +21,14 @@ static struct device_operations hda_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_MTL_AUDIO_1,
+	PCI_DID_INTEL_MTL_AUDIO_2,
+	PCI_DID_INTEL_MTL_AUDIO_3,
+	PCI_DID_INTEL_MTL_AUDIO_4,
+	PCI_DID_INTEL_MTL_AUDIO_5,
+	PCI_DID_INTEL_MTL_AUDIO_6,
+	PCI_DID_INTEL_MTL_AUDIO_7,
+	PCI_DID_INTEL_MTL_AUDIO_8,
 	PCI_DID_INTEL_SKL_AUDIO,
 	PCI_DID_INTEL_SKL_H_AUDIO,
 	PCI_DID_INTEL_LWB_AUDIO,

src/soc/intel/common/block/i2c/i2c.c

@@ -175,6 +175,12 @@ static struct device_operations i2c_dev_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_MTL_I2C0,
+	PCI_DID_INTEL_MTL_I2C1,
+	PCI_DID_INTEL_MTL_I2C2,
+	PCI_DID_INTEL_MTL_I2C3,
+	PCI_DID_INTEL_MTL_I2C4,
+	PCI_DID_INTEL_MTL_I2C5,
 	PCI_DID_INTEL_SPT_I2C0,
 	PCI_DID_INTEL_SPT_I2C1,
 	PCI_DID_INTEL_SPT_I2C2,

src/soc/intel/common/block/lpc/lpc.c

@@ -106,6 +106,14 @@ static struct device_operations device_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_MTL_ESPI_0,
+	PCI_DID_INTEL_MTL_ESPI_1,
+	PCI_DID_INTEL_MTL_ESPI_2,
+	PCI_DID_INTEL_MTL_ESPI_3,
+	PCI_DID_INTEL_MTL_ESPI_4,
+	PCI_DID_INTEL_MTL_ESPI_5,
+	PCI_DID_INTEL_MTL_ESPI_6,
+	PCI_DID_INTEL_MTL_ESPI_7,
 	PCI_DID_INTEL_SPT_LP_SAMPLE,
 	PCI_DID_INTEL_SPT_LP_U_BASE,
 	PCI_DID_INTEL_SPT_LP_U_PREMIUM,

src/soc/intel/common/block/p2sb/p2sb.c

@@ -144,6 +144,9 @@ static const struct device_operations device_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_MTL_SOC_P2SB,
+	PCI_DID_INTEL_MTL_IOE_M_P2SB,
+	PCI_DID_INTEL_MTL_IOE_P_P2SB,
 	PCI_DID_INTEL_APL_P2SB,
 	PCI_DID_INTEL_GLK_P2SB,
 	PCI_DID_INTEL_LWB_P2SB,

src/soc/intel/common/block/pcie/pcie.c

@@ -66,6 +66,18 @@ static struct device_operations device_ops = {
 };
 
 static const unsigned short pcie_device_ids[] = {
+	PCI_DID_INTEL_MTL_SOC_PCIE_RP1,
+	PCI_DID_INTEL_MTL_SOC_PCIE_RP2,
+	PCI_DID_INTEL_MTL_SOC_PCIE_RP3,
+	PCI_DID_INTEL_MTL_SOC_PCIE_RP4,
+	PCI_DID_INTEL_MTL_SOC_PCIE_RP5,
+	PCI_DID_INTEL_MTL_SOC_PCIE_RP6,
+	PCI_DID_INTEL_MTL_SOC_PCIE_RP7,
+	PCI_DID_INTEL_MTL_SOC_PCIE_RP8,
+	PCI_DID_INTEL_MTL_SOC_PCIE_RP9,
+	PCI_DID_INTEL_MTL_IOE_P_PCIE_RP10,
+	PCI_DID_INTEL_MTL_IOE_P_PCIE_RP11,
+	PCI_DID_INTEL_MTL_IOE_P_PCIE_RP12,
 	PCI_DID_INTEL_SPT_LP_PCIE_RP1,
 	PCI_DID_INTEL_SPT_LP_PCIE_RP2,
 	PCI_DID_INTEL_SPT_LP_PCIE_RP3,

src/soc/intel/common/block/pmc/pmc.c

@@ -111,6 +111,9 @@ static struct device_operations device_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_MTL_SOC_PMC,
+	PCI_DID_INTEL_MTL_IOE_M_PMC,
+	PCI_DID_INTEL_MTL_IOE_P_PMC,
 	PCI_DID_INTEL_DNV_PMC,
 	PCI_DID_INTEL_SPT_LP_PMC,
 	PCI_DID_INTEL_SPT_H_PMC,

src/soc/intel/common/block/sata/sata.c

@@ -13,6 +13,7 @@ static struct device_operations sata_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_MTL_SATA,
 	PCI_DID_INTEL_SPT_U_SATA,
 	PCI_DID_INTEL_SPT_U_Y_PREMIUM_SATA,
 	PCI_DID_INTEL_SPT_KBL_SATA,

src/soc/intel/common/block/smbus/smbus.c

@@ -74,6 +74,7 @@ static struct device_operations smbus_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_MTL_SMBUS,
 	PCI_DID_INTEL_APL_SMBUS,
 	PCI_DID_INTEL_CNL_SMBUS,
 	PCI_DID_INTEL_CNP_H_SMBUS,

src/soc/intel/common/block/spi/spi.c

@@ -39,6 +39,10 @@ static struct device_operations spi_dev_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_MTL_HWSEQ_SPI,
+	PCI_DID_INTEL_MTL_GSPI0,
+	PCI_DID_INTEL_MTL_GSPI1,
+	PCI_DID_INTEL_MTL_GSPI2,
 	PCI_DID_INTEL_SPT_SPI1,
 	PCI_DID_INTEL_SPT_SPI2,
 	PCI_DID_INTEL_SPT_SPI3,

src/soc/intel/common/block/sram/sram.c

@@ -33,6 +33,10 @@ static const struct device_operations device_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_MTL_SOC_SRAM,
+	PCI_DID_INTEL_MTL_IOE_M_SRAM,
+	PCI_DID_INTEL_MTL_IOE_P_SRAM,
+	PCI_DID_INTEL_MTL_CRASHLOG_SRAM,
 	PCI_DID_INTEL_APL_SRAM,
 	PCI_DID_INTEL_GLK_SRAM,
 	PCI_DID_INTEL_ICL_SRAM,

src/soc/intel/common/block/systemagent/systemagent.c

@@ -327,6 +327,9 @@ static struct device_operations systemagent_ops = {
 };
 
 static const unsigned short systemagent_ids[] = {
+	PCI_DID_INTEL_MTL_M_ID,
+	PCI_DID_INTEL_MTL_P_ID_1,
+	PCI_DID_INTEL_MTL_P_ID_2,
 	PCI_DID_INTEL_GLK_NB,
 	PCI_DID_INTEL_APL_NB,
 	PCI_DID_INTEL_CNL_ID_U,

src/soc/intel/common/block/uart/uart.c

@@ -344,6 +344,9 @@ static struct device_operations device_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_MTL_UART0,
+	PCI_DID_INTEL_MTL_UART1,
+	PCI_DID_INTEL_MTL_UART2,
 	PCI_DID_INTEL_SPT_UART0,
 	PCI_DID_INTEL_SPT_UART1,
 	PCI_DID_INTEL_SPT_UART2,

src/soc/intel/common/block/usb4/usb4.c

@@ -53,6 +53,9 @@ static void tbt_dma_fill_ssdt(const struct device *dev)
 #endif
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_MTL_M_TBT_DMA0,
+	PCI_DID_INTEL_MTL_P_TBT_DMA0,
+	PCI_DID_INTEL_MTL_P_TBT_DMA1,
 	PCI_DID_INTEL_TGL_TBT_DMA0,
 	PCI_DID_INTEL_TGL_TBT_DMA1,
 	PCI_DID_INTEL_TGL_H_TBT_DMA0,

src/soc/intel/common/block/usb4/xhci.c

@@ -26,6 +26,8 @@ static struct device_operations usb4_xhci_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_MTL_M_TCSS_XHCI,
+	PCI_DID_INTEL_MTL_P_TCSS_XHCI,
 	PCI_DID_INTEL_TGP_TCSS_XHCI,
 	PCI_DID_INTEL_TGP_H_TCSS_XHCI,
 	PCI_DID_INTEL_ADP_TCSS_XHCI,

src/soc/intel/common/block/xdci/xdci.c

@@ -27,6 +27,7 @@ static struct device_operations usb_xdci_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_MTL_XDCI,
 	PCI_DID_INTEL_APL_XDCI,
 	PCI_DID_INTEL_CNL_LP_XDCI,
 	PCI_DID_INTEL_GLK_XDCI,

src/soc/intel/common/block/xhci/xhci.c

@@ -106,6 +106,7 @@ static struct device_operations usb_xhci_ops = {
 };
 
 static const unsigned short pci_device_ids[] = {
+	PCI_DID_INTEL_MTL_XHCI,
 	PCI_DID_INTEL_APL_XHCI,
 	PCI_DID_INTEL_CNL_LP_XHCI,
 	PCI_DID_INTEL_GLK_XHCI,