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cpu/x86: Rename X86_AMD_INIT_SIPI to X86_INIT_NEED_1_SIPI

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This patch renames X86_AMD_INIT_SIPI Kconfig to leverage
the same logic (to skip 2nd SIPI and reduce delay between
INIT and SIPI while perform AP initialization) even on
newer Intel platform.

Change-Id: I7a4e6a8b1edc6e8ba43597259bd8b2de697e4e62
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/56651
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Subrata Banik 2021-07-28 15:38:32 +05:30 committed by Felix Held
parent 561a2afc18
commit 9f91ced9dd
4 changed files with 7 additions and 7 deletions
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8
src/cpu/x86/Kconfig
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@ -164,15 +164,15 @@ config X86_AMD_FIXED_MTRRS
This option informs the MTRR code to use the RdMem and WrMem fields This option informs the MTRR code to use the RdMem and WrMem fields
in the fixed MTRR MSRs. in the fixed MTRR MSRs.
config X86_AMD_INIT_SIPI config X86_INIT_NEED_1_SIPI
bool bool
default n default n
help help
This option limits the number of SIPI signals sent during during the This option limits the number of SIPI signals sent during during the
common AP setup. Intel documentation specifies an INIT SIPI SIPI common AP setup. Intel documentation specifies an INIT SIPI SIPI
sequence, however this doesn't work on some AMD platforms. These sequence, however this doesn't work on some AMD and Intel platforms.
newer AMD platforms don't need the 10ms wait between INIT and SIPI, These newer AMD and Intel platforms don't need the 10ms wait between
so skip that too to save some time. INIT and SIPI, so skip that too to save some time.
config SOC_SETS_MSRS config SOC_SETS_MSRS
bool bool

2
src/cpu/x86/mp_init.c
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@ -469,7 +469,7 @@ static enum cb_err start_aps(struct bus *cpu_bus, int ap_count, atomic_t *num_ap
/* Send INIT IPI to all but self. */ /* Send INIT IPI to all but self. */
lapic_send_ipi(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT, 0); lapic_send_ipi(LAPIC_DEST_ALLBUT | LAPIC_INT_ASSERT | LAPIC_DM_INIT, 0);
if (!CONFIG(X86_AMD_INIT_SIPI)) { if (!CONFIG(X86_INIT_NEED_1_SIPI)) {
printk(BIOS_DEBUG, "Waiting for 10ms after sending INIT.\n"); printk(BIOS_DEBUG, "Waiting for 10ms after sending INIT.\n");
mdelay(10); mdelay(10);

2
src/soc/amd/cezanne/Kconfig
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@ -73,7 +73,7 @@ config SOC_SPECIFIC_OPTIONS
select SSE2 select SSE2
select UDK_2017_BINDING select UDK_2017_BINDING
select X86_AMD_FIXED_MTRRS select X86_AMD_FIXED_MTRRS
select X86_AMD_INIT_SIPI select X86_INIT_NEED_1_SIPI
config ARCH_ALL_STAGES_X86 config ARCH_ALL_STAGES_X86
default n default n

2
src/soc/amd/picasso/Kconfig
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@ -16,7 +16,7 @@ config CPU_SPECIFIC_OPTIONS
select ARCH_X86 select ARCH_X86
select RESET_VECTOR_IN_RAM select RESET_VECTOR_IN_RAM
select X86_AMD_FIXED_MTRRS select X86_AMD_FIXED_MTRRS
select X86_AMD_INIT_SIPI select X86_INIT_NEED_1_SIPI
select ACPI_SOC_NVS select ACPI_SOC_NVS
select ADD_FSP_BINARIES if USE_AMD_BLOBS select ADD_FSP_BINARIES if USE_AMD_BLOBS
select DRIVERS_I2C_DESIGNWARE select DRIVERS_I2C_DESIGNWARE