mb/system76/rpl: Add bonw15-b variant
The Bonobo has been updated with a Thunderbolt 5 controller (Barlow Ridge). Identified chip changes from the schematics: - JHL8540_MP -> JHL9580_QS - TPS65994BF -> TPS65994BH - IT5570E-128 -> IT5570E-256 Change-Id: I784e489cdd034febeaaac0182ab5b4fe672381ec Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
parent
5f21837245
commit
9fdb2550b9
@ -44,6 +44,12 @@ config BOARD_SYSTEM76_BONW15
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select PCIEXP_HOTPLUG
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select SOC_INTEL_ALDERLAKE_PCH_S
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config BOARD_SYSTEM76_BONW15_B
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select BOARD_SYSTEM76_RPL_COMMON
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select EC_SYSTEM76_EC_DGPU
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select PCIEXP_HOTPLUG
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select SOC_INTEL_ALDERLAKE_PCH_S
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config BOARD_SYSTEM76_DARP9
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select BOARD_SYSTEM76_RPL_COMMON
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select PCIEXP_HOTPLUG
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@ -93,6 +99,7 @@ config VARIANT_DIR
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default "addw3" if BOARD_SYSTEM76_ADDW3
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default "addw4" if BOARD_SYSTEM76_ADDW4
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default "bonw15" if BOARD_SYSTEM76_BONW15
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default "bonw15-b" if BOARD_SYSTEM76_BONW15_B
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default "darp9" if BOARD_SYSTEM76_DARP9
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default "galp7" if BOARD_SYSTEM76_GALP7
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default "gaze18" if BOARD_SYSTEM76_GAZE18
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@ -108,6 +115,7 @@ config MAINBOARD_PART_NUMBER
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default "addw3" if BOARD_SYSTEM76_ADDW3
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default "addw4" if BOARD_SYSTEM76_ADDW4
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default "bonw15" if BOARD_SYSTEM76_BONW15
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default "bonw15-b" if BOARD_SYSTEM76_BONW15_B
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default "darp9" if BOARD_SYSTEM76_DARP9
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default "galp7" if BOARD_SYSTEM76_GALP7
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default "gaze18" if BOARD_SYSTEM76_GAZE18
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@ -118,7 +126,7 @@ config MAINBOARD_PART_NUMBER
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config MAINBOARD_SMBIOS_PRODUCT_NAME
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default "Adder WS" if BOARD_SYSTEM76_ADDW3 || BOARD_SYSTEM76_ADDW4
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default "Bonobo WS" if BOARD_SYSTEM76_BONW15
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default "Bonobo WS" if BOARD_SYSTEM76_BONW15 || BOARD_SYSTEM76_BONW15_B
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default "Darter Pro" if BOARD_SYSTEM76_DARP9
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default "Galago Pro" if BOARD_SYSTEM76_GALP7
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default "Gazelle" if BOARD_SYSTEM76_GAZE18
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@ -130,6 +138,7 @@ config MAINBOARD_VERSION
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default "addw3" if BOARD_SYSTEM76_ADDW3
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default "addw4" if BOARD_SYSTEM76_ADDW4
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default "bonw15" if BOARD_SYSTEM76_BONW15
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default "bonw15-b" if BOARD_SYSTEM76_BONW15_B
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default "darp9" if BOARD_SYSTEM76_DARP9
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default "galp7" if BOARD_SYSTEM76_GALP7
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default "gaze18" if BOARD_SYSTEM76_GAZE18
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@ -9,6 +9,9 @@ config BOARD_SYSTEM76_ADDW4
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config BOARD_SYSTEM76_BONW15
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bool "bonw15"
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config BOARD_SYSTEM76_BONW15_B
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bool "bonw15-b"
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config BOARD_SYSTEM76_DARP9
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bool "darp9"
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12
src/mainboard/system76/rpl/variants/bonw15-b/board.fmd
Normal file
12
src/mainboard/system76/rpl/variants/bonw15-b/board.fmd
Normal file
@ -0,0 +1,12 @@
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FLASH 32M {
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SI_DESC 4K
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SI_ME 3944K
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SI_BIOS@16M 16M {
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RW_MRC_CACHE 64K
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SMMSTORE(PRESERVE) 256K
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WP_RO {
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FMAP 4K
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COREBOOT(CBFS)
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}
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}
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}
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@ -0,0 +1,2 @@
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Board name: bonw15-b
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Release year: 2024
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BIN
src/mainboard/system76/rpl/variants/bonw15-b/data.vbt
Normal file
BIN
src/mainboard/system76/rpl/variants/bonw15-b/data.vbt
Normal file
Binary file not shown.
294
src/mainboard/system76/rpl/variants/bonw15-b/gpio.c
Normal file
294
src/mainboard/system76/rpl/variants/bonw15-b/gpio.c
Normal file
@ -0,0 +1,294 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <mainboard/gpio.h>
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#include <soc/gpio.h>
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static const struct pad_config gpio_table[] = {
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/* ------- GPIO Group GPD ------- */
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PAD_NC(GPD0, NONE),
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PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
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_PAD_CFG_STRUCT(GPD2, 0x42880100, 0x0000), // PCH_LAN_WAKE#
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PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWR_BTN#
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PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
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PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
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PAD_NC(GPD6, NONE),
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PAD_CFG_GPI(GPD7, NONE, PWROK), // GPD_7
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PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // CNVI_SUSCLK
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PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN_N
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PAD_NC(GPD10, NONE),
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PAD_CFG_GPO(GPD11, 0, DEEP), // LANPHYPC
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PAD_NC(GPD12, NONE),
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/* ------- GPIO Group GPP_A ------- */
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PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
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PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
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PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
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PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
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PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
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PAD_CFG_NF(GPP_A5, DN_20K, DEEP, NF1), // ESPI_CLK_EC
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PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1), // ESPI_RESET_N
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PAD_NC(GPP_A7, NONE),
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PAD_NC(GPP_A8, NONE),
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PAD_NC(GPP_A9, NONE),
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PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_ALERT0#
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PAD_NC(GPP_A11, NONE),
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PAD_NC(GPP_A12, NONE),
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PAD_NC(GPP_A13, NONE),
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PAD_NC(GPP_A14, NONE),
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/* ------- GPIO Group GPP_B ------- */
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_PAD_CFG_STRUCT(GPP_B0, 0x82900100, 0x0000), // TPM_PIRQ#
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PAD_NC(GPP_B1, NONE),
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PAD_CFG_GPI(GPP_B2, NONE, DEEP), // CNVI_WAKE#
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PAD_CFG_GPO(GPP_B3, 1, DEEP), // PCH_BT_EN
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PAD_NC(GPP_B4, NONE),
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PAD_NC(GPP_B5, NONE),
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PAD_NC(GPP_B6, NONE),
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PAD_NC(GPP_B7, NONE),
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PAD_NC(GPP_B8, NONE),
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PAD_NC(GPP_B9, NONE),
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PAD_NC(GPP_B10, NONE),
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PAD_NC(GPP_B11, NONE),
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PAD_NC(GPP_B12, NONE),
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
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PAD_CFG_NF(GPP_B14, NONE, DEEP, NF1), // HDA_SPKR
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PAD_NC(GPP_B15, NONE), // PS8461_SW
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PAD_NC(GPP_B16, NONE),
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PAD_NC(GPP_B17, NONE), // 2.5G_LAN_EN
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PAD_CFG_NF(GPP_B18, NONE, RSMRST, NF1), // PMCALERT# (tied high)
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PAD_CFG_GPO(GPP_B19, 1, DEEP), // PCH_WLAN_EN
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PAD_NC(GPP_B20, NONE),
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PAD_NC(GPP_B21, NONE),
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PAD_CFG_GPO(GPP_B22, 1, DEEP), // LAN_RST#
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PAD_CFG_GPI(GPP_B23, NONE, RSMRST), // GPP_B23 (XTAL FREQ SEL1)
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/* ------- GPIO Group GPP_C ------- */
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PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
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PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
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PAD_CFG_GPI(GPP_C2, NONE, PLTRST), // TLS confidentiality strap
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PAD_CFG_GPO(GPP_C3, 0, DEEP), // GPPC_I2C2_SDA (Pantone)
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PAD_CFG_GPO(GPP_C4, 0, DEEP), // GPPC_I2C2_SCL (Pantone)
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PAD_NC(GPP_C5, NONE), // eSPI disable strap
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PAD_NC(GPP_C6, NONE),
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PAD_NC(GPP_C7, NONE),
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PAD_CFG_GPI(GPP_C8, NONE, DEEP), // TPM_DET
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PAD_NC(GPP_C9, NONE),
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PAD_NC(GPP_C10, NONE),
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PAD_NC(GPP_C11, NONE),
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PAD_NC(GPP_C12, NONE),
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PAD_NC(GPP_C13, NONE),
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PAD_NC(GPP_C14, NONE),
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PAD_NC(GPP_C15, NONE),
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PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), // I2C_SDA_TP
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PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), // I2C_SCL_TP
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PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), // PCH_I2C_SDA (TPS65994)
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PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), // PCH_I2C_SCL (TPS65994)
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// GPP_C20 (UART2_RXD) configured in bootblock
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// GPP_C21 (UART2_TXD) configured in bootblock
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PAD_CFG_GPO(GPP_C22, 0, DEEP), // ROM_I2C_EN (TPS65994)
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PAD_NC(GPP_C23, NONE),
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/* ------- GPIO Group GPP_D ------- */
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PAD_NC(GPP_D0, NONE),
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PAD_NC(GPP_D1, NONE),
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PAD_NC(GPP_D2, NONE),
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PAD_NC(GPP_D3, NONE), // GFX_DETECT_STRAP
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PAD_NC(GPP_D4, NONE),
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PAD_CFG_GPO(GPP_D5, 1, DEEP), // M.2_BT_PCMFRM_CRF_RST_N
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// GPP_D6 (M.2_BT_PCMOUT_CLKREQ0) configured by FSP
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PAD_NC(GPP_D7, NONE),
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PAD_NC(GPP_D8, NONE),
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PAD_NC(GPP_D9, NONE),
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PAD_NC(GPP_D10, NONE),
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PAD_NC(GPP_D11, NONE),
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PAD_NC(GPP_D12, NONE),
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PAD_NC(GPP_D13, NONE),
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PAD_NC(GPP_D14, NONE),
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PAD_NC(GPP_D15, NONE),
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PAD_NC(GPP_D16, NONE),
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PAD_NC(GPP_D17, NONE),
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PAD_NC(GPP_D18, NONE),
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PAD_NC(GPP_D19, NONE),
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PAD_NC(GPP_D20, NONE),
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PAD_NC(GPP_D21, NONE),
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PAD_NC(GPP_D22, NONE),
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PAD_NC(GPP_D23, NONE),
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/* ------- GPIO Group GPP_E ------- */
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PAD_CFG_GPO(GPP_E0, 1, DEEP), // GPP_E0_TBT_RST#
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PAD_NC(GPP_E1, NONE),
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PAD_NC(GPP_E2, NONE),
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PAD_NC(GPP_E3, NONE),
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PAD_NC(GPP_E4, NONE),
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PAD_NC(GPP_E5, NONE),
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PAD_NC(GPP_E6, NONE),
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PAD_CFG_GPI_INT(GPP_E7, NONE, PLTRST, LEVEL), // TP_ATTN#
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PAD_CFG_NF(GPP_E8, NONE, DEEP, NF1), // SATA_LED#
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PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // GPP_E_9_USB_OC0_N
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PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1), // GPP_E_10_USB_OC1_N
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PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), // GPP_E_11_USB_OC2_N
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PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), // GPP_E_12_USB_OC3_N
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PAD_NC(GPP_E13, NONE),
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PAD_NC(GPP_E14, NONE),
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PAD_NC(GPP_E15, NONE),
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PAD_NC(GPP_E16, NONE),
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PAD_NC(GPP_E17, NONE),
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PAD_CFG_GPO(GPP_E18, 1, DEEP), // SB_BLON
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_PAD_CFG_STRUCT(GPP_E19, 0x42880100, 0x0000), // GPP_E19_TBT_WAKE#
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PAD_NC(GPP_E20, NONE),
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PAD_NC(GPP_E21, NONE),
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/* ------- GPIO Group GPP_F ------- */
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PAD_NC(GPP_F0, NONE),
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PAD_NC(GPP_F1, NONE),
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PAD_NC(GPP_F2, NONE),
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PAD_NC(GPP_F3, NONE),
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PAD_NC(GPP_F4, NONE),
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PAD_NC(GPP_F5, NONE),
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PAD_NC(GPP_F6, NONE),
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PAD_NC(GPP_F7, NONE),
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PAD_CFG_GPI(GPP_F8, NONE, DEEP), // GC6_FB_EN_PCH
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PAD_NC(GPP_F9, NONE),
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PAD_NC(GPP_F10, NONE),
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PAD_NC(GPP_F11, NONE),
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PAD_NC(GPP_F12, NONE),
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PAD_NC(GPP_F13, NONE),
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PAD_CFG_GPI(GPP_F14, NONE, DEEP), // TBT5 strap
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PAD_CFG_GPI(GPP_F15, NONE, DEEP), // H_SKTOCC_N
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PAD_NC(GPP_F16, NONE),
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PAD_NC(GPP_F17, NONE),
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PAD_CFG_GPO(GPP_F18, 0, DEEP), // CCD_FW_WP#
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PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // NB_ENAVDD
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PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1), // BLON
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PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1), // EDP_BRIGHTNESS
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// GPP_F22 (DGPU_PWR_EN) configured in bootblock
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PAD_NC(GPP_F23, NONE),
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/* ------- GPIO Group GPP_G ------- */
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PAD_NC(GPP_G0, NONE),
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PAD_CFG_GPI(GPP_G1, NONE, DEEP), // GPU SKU strap (L: X9, H: X11)
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PAD_NC(GPP_G2, NONE),
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PAD_CFG_GPI(GPP_G3, NONE, DEEP), // DDS strap (L: Non-DDS, H: DDS)
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PAD_CFG_GPI(GPP_G4, NONE, DEEP), // Smart AMP strap (L: TI, H: Realtek)
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PAD_CFG_NF(GPP_G5, NONE, DEEP, NF1), // SLP_DRAM_N
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PAD_CFG_GPI(GPP_G6, NONE, DEEP), // Pantone (L: W/O, H: W)
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PAD_NC(GPP_G7, NONE),
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/* ------- GPIO Group GPP_H ------- */
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PAD_CFG_GPI(GPP_H0, NONE, DEEP), // VAL_SV_ADVANCE_STRAP
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PAD_NC(GPP_H1, NONE),
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PAD_NC(GPP_H2, NONE), // WLAN_WAKE_N
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// GPP_H3 (WLAN_CLKREQ9#) configured by FSP
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// GPP_H4 (SSD1_CLKREQ10#) configured by FSP
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// GPP_H5 (SSD2_CLKREQ11#) configured by FSP
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// GPP_H6 (SSD3_CLKREQ12#) configured by FSP
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// GPP_H7 (TBT_CLKREQ13#) configured by FSP
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// GPP_H8 (GPU_PCIE_CLKREQ14#) configured by FSP
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// GPP_H9 (GLAN_CLKREQ15#) configured by FSP
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PAD_NC(GPP_H10, NONE),
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PAD_NC(GPP_H11, NONE),
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PAD_CFG_GPI(GPP_H12, NONE, RSMRST), // eSPI flash sharing mode strap (L: MAF, H: SAF)
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PAD_NC(GPP_H13, NONE),
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PAD_NC(GPP_H14, NONE),
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PAD_CFG_GPI(GPP_H15, NONE, RSMRST), // JTAG ODT disable strap (L: Disable, H: Enable)
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PAD_NC(GPP_H16, NONE),
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PAD_CFG_GPO(GPP_H17, 1, DEEP), // M.2_PLT_RST_CNTRL3#
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PAD_CFG_GPI(GPP_H18, NONE, RSMRST), // VCCPSPI strap (L: 3.3V, H: 1.8V)
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PAD_NC(GPP_H19, NONE),
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PAD_NC(GPP_H20, NONE),
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PAD_NC(GPP_H21, NONE), // TBT_MRESET_PCH
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PAD_NC(GPP_H22, NONE),
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PAD_NC(GPP_H23, NONE),
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/* ------- GPIO Group GPP_I ------- */
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PAD_NC(GPP_I0, NONE),
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_PAD_CFG_STRUCT(GPP_I1, 0x86880100, 0x0000), // G_DP_DHPD_E
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_PAD_CFG_STRUCT(GPP_I2, 0x86880100, 0x0000), // DP_D_HPD
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_PAD_CFG_STRUCT(GPP_I3, 0x86880100, 0x0000), // HDMI_HPD
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_PAD_CFG_STRUCT(GPP_I4, 0x86880100, 0x0000), // DP_A_HPD
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PAD_NC(GPP_I5, NONE),
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PAD_NC(GPP_I6, NONE),
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PAD_NC(GPP_I7, NONE),
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PAD_NC(GPP_I8, NONE),
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PAD_NC(GPP_I9, NONE),
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PAD_NC(GPP_I10, NONE),
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PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1), // GPP_I_11_USB_OC4_N
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PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1), // GPP_I_12_USB_OC5_N
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PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1), // GPP_I_13_USB_OC6_N
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PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1), // GPP_I_14_USB_OC7_N
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PAD_NC(GPP_I15, NONE),
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PAD_NC(GPP_I16, NONE),
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PAD_NC(GPP_I17, NONE),
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PAD_CFG_GPI(GPP_I18, NONE, PWROK), // No reboot strap (L: Disable, H: Enable)
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PAD_NC(GPP_I19, NONE),
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PAD_NC(GPP_I20, NONE),
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PAD_NC(GPP_I21, NONE),
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PAD_CFG_GPI(GPP_I22, NONE, PWROK), // Boot BIOS strap (L: MAF or SAF, H: eSPI)
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/* ------- GPIO Group GPP_J ------- */
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PAD_CFG_NF(GPP_J0, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
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PAD_CFG_NF(GPP_J1, NONE, DEEP, NF1), // CPU_C10_GATE#
|
||||
PAD_CFG_NF(GPP_J2, NONE, DEEP, NF1), // CNVI_BRI_DT_R
|
||||
PAD_CFG_NF(GPP_J3, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
|
||||
PAD_CFG_NF(GPP_J4, NONE, DEEP, NF1), // CNVI_RGI_DT_R
|
||||
PAD_CFG_NF(GPP_J5, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
|
||||
PAD_CFG_NF(GPP_J6, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
|
||||
PAD_CFG_NF(GPP_J7, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
|
||||
PAD_CFG_GPI(GPP_J8, NONE, DEEP), // VAL_TEST_SETUP_MENU
|
||||
PAD_NC(GPP_J9, NONE),
|
||||
PAD_NC(GPP_J10, NONE),
|
||||
PAD_NC(GPP_J11, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_K ------- */
|
||||
PAD_NC(GPP_K0, NONE),
|
||||
PAD_NC(GPP_K1, NONE),
|
||||
PAD_NC(GPP_K2, NONE),
|
||||
PAD_NC(GPP_K3, NONE),
|
||||
PAD_NC(GPP_K4, NONE),
|
||||
PAD_NC(GPP_K5, NONE),
|
||||
// GPP_K6 missing
|
||||
// GPP_K7 missing
|
||||
PAD_CFG_NF(GPP_K8, NONE, DEEP, NF1), // GPP_K_8_CORE_VID_0
|
||||
PAD_CFG_NF(GPP_K9, NONE, DEEP, NF1), // GPP_K_9_CORE_VID_1
|
||||
PAD_CFG_NF(GPP_K10, NONE, DEEP, NF2),
|
||||
PAD_NC(GPP_K11, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_R ------- */
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#
|
||||
PAD_NC(GPP_R5, NONE),
|
||||
PAD_NC(GPP_R6, NONE),
|
||||
PAD_CFG_GPO(GPP_R7, 1, DEEP), // GPP_R7_TBT_RTD3
|
||||
PAD_CFG_GPI(GPP_R8, NONE, DEEP), // DGPU_PWRGD
|
||||
PAD_CFG_NF(GPP_R9, NONE, DEEP, NF1), // EDP_HPD
|
||||
PAD_NC(GPP_R10, NONE),
|
||||
PAD_NC(GPP_R11, NONE),
|
||||
PAD_NC(GPP_R12, NONE),
|
||||
PAD_NC(GPP_R13, NONE),
|
||||
PAD_NC(GPP_R14, NONE),
|
||||
PAD_NC(GPP_R15, NONE),
|
||||
// GPP_R16 (DGPU_RST#_PCH) configured in bootblock
|
||||
PAD_NC(GPP_R17, NONE),
|
||||
PAD_NC(GPP_R18, NONE),
|
||||
PAD_NC(GPP_R19, NONE),
|
||||
PAD_NC(GPP_R20, NONE),
|
||||
PAD_NC(GPP_R21, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_S ------- */
|
||||
PAD_NC(GPP_S0, NONE),
|
||||
PAD_NC(GPP_S1, NONE),
|
||||
PAD_NC(GPP_S2, NONE),
|
||||
PAD_NC(GPP_S3, NONE),
|
||||
PAD_NC(GPP_S4, NONE), // GPPS_DMIC_CLK
|
||||
PAD_NC(GPP_S5, NONE), // GPPS_DMIC_DATA
|
||||
PAD_NC(GPP_S6, NONE),
|
||||
PAD_NC(GPP_S7, NONE),
|
||||
};
|
||||
|
||||
void mainboard_configure_gpios(void)
|
||||
{
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
}
|
||||
16
src/mainboard/system76/rpl/variants/bonw15-b/gpio_early.c
Normal file
16
src/mainboard/system76/rpl/variants/bonw15-b/gpio_early.c
Normal file
@ -0,0 +1,16 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <mainboard/gpio.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), // UART2_RXD
|
||||
PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), // UART2_TXD
|
||||
PAD_CFG_GPO(GPP_F22, 0, DEEP), // DGPU_PWR_EN
|
||||
PAD_CFG_GPO(GPP_R16, 0, DEEP), // DGPU_RST#_PCH
|
||||
};
|
||||
|
||||
void mainboard_configure_early_gpios(void)
|
||||
{
|
||||
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
|
||||
}
|
||||
263
src/mainboard/system76/rpl/variants/bonw15-b/hda_verb.c
Normal file
263
src/mainboard/system76/rpl/variants/bonw15-b/hda_verb.c
Normal file
@ -0,0 +1,263 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC1220 */
|
||||
0x10ec1220, /* Vendor ID */
|
||||
0x15583702, /* Subsystem ID */
|
||||
243, /* Number of entries */
|
||||
|
||||
0x02050008, 0x020480cb, 0x02050008, 0x0204c0cb,
|
||||
AZALIA_SUBVENDOR(0, 0x15583702),
|
||||
AZALIA_RESET(1),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
|
||||
|
||||
// ALC1318 smart amp
|
||||
0x05b50000, 0x05b43530, 0x05750002, 0x05741400,
|
||||
0x02050058, 0x02048ed1, 0x02050063, 0x0204e430,
|
||||
0x02050016, 0x02048020, 0x02050016, 0x02048020,
|
||||
0x02050043, 0x02043005, 0x02050058, 0x02048ed1,
|
||||
0x02050063, 0x0204e430, 0x05b50000, 0x05b43530,
|
||||
0x05750002, 0x05741400, 0x05b5000a, 0x05b45520,
|
||||
0x02050042, 0x020486cb, 0x0143b000, 0x01470700,
|
||||
0x02050036, 0x02042a6a, 0x02050008, 0x0204800b,
|
||||
0x02050007, 0x020403c3, 0x01470c02, 0x01470c02,
|
||||
0x00c37100, 0x01b3b000, 0x01b70700, 0x00b37417,
|
||||
0x0205001b, 0x02044002, 0x0205001b, 0x02044002,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204c000, 0x0205002b, 0x02040001,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204f20d,
|
||||
0x0205002b, 0x02040000, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204f212, 0x0205002b, 0x0204003e,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204c001,
|
||||
0x0205002b, 0x02040002, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204c003, 0x0205002b, 0x02040022,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204c004,
|
||||
0x0205002b, 0x02040044, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204c005, 0x0205002b, 0x02040044,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204c007,
|
||||
0x0205002b, 0x02040064, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204c00e, 0x0205002b, 0x020400e7,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204f223,
|
||||
0x0205002b, 0x0204007f, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204f224, 0x0205002b, 0x020400db,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204f225,
|
||||
0x0205002b, 0x020400ee, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204f226, 0x0205002b, 0x0204003f,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204f227,
|
||||
0x0205002b, 0x0204000f, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204f21a, 0x0205002b, 0x02040078,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204f242,
|
||||
0x0205002b, 0x0204003c, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204c120, 0x0205002b, 0x02040040,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204c125,
|
||||
0x0205002b, 0x02040003, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204c321, 0x0205002b, 0x0204000b,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204c200,
|
||||
0x0205002b, 0x020400d8, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204c201, 0x0205002b, 0x02040027,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204c202,
|
||||
0x0205002b, 0x0204000f, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204c400, 0x0205002b, 0x0204000e,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204c401,
|
||||
0x0205002b, 0x02040043, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204c402, 0x0205002b, 0x020400e0,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204c403,
|
||||
0x0205002b, 0x02040000, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204c404, 0x0205002b, 0x0204004c,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204c406,
|
||||
0x0205002b, 0x02040040, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204c407, 0x0205002b, 0x02040002,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204c408,
|
||||
0x0205002b, 0x0204003f, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204c300, 0x0205002b, 0x02040001,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204c125,
|
||||
0x0205002b, 0x02040003, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204df00, 0x0205002b, 0x02040010,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204df5f,
|
||||
0x0205002b, 0x02040001, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204df60, 0x0205002b, 0x020400a7,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204ea00,
|
||||
0x0205002b, 0x02040047, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204c203, 0x0205002b, 0x02040004,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204c206,
|
||||
0x0205002b, 0x02040078, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204f102, 0x0205002b, 0x02040000,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204f103,
|
||||
0x0205002b, 0x02040000, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204f104, 0x0205002b, 0x020400f4,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204f105,
|
||||
0x0205002b, 0x02040003, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204f109, 0x0205002b, 0x020400e0,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204f10a,
|
||||
0x0205002b, 0x0204000b, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204f10b, 0x0205002b, 0x0204004c,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204f10b,
|
||||
0x0205002b, 0x0204005c, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204f102, 0x0205002b, 0x02040000,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204f103,
|
||||
0x0205002b, 0x02040000, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204f104, 0x0205002b, 0x020400f4,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204f105,
|
||||
0x0205002b, 0x02040004, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204f109, 0x0205002b, 0x02040065,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204f10a,
|
||||
0x0205002b, 0x0204000b, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204f10b, 0x0205002b, 0x0204004c,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204f10b,
|
||||
0x0205002b, 0x0204005c, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204e706, 0x0205002b, 0x0204000f,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204e707,
|
||||
0x0205002b, 0x02040030, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204e806, 0x0205002b, 0x0204000f,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204e807,
|
||||
0x0205002b, 0x02040030, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204ce04, 0x0205002b, 0x02040002,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204ce05,
|
||||
0x0205002b, 0x02040087, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204ce06, 0x0205002b, 0x020400a2,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204ce07,
|
||||
0x0205002b, 0x0204006c, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204cf04, 0x0205002b, 0x02040002,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204cf05,
|
||||
0x0205002b, 0x02040087, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204cf06, 0x0205002b, 0x020400a2,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204cf07,
|
||||
0x0205002b, 0x0204006c, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204ce60, 0x0205002b, 0x020400e3,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204c130,
|
||||
0x0205002b, 0x02040051, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204e000, 0x0205002b, 0x020400a8,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204f102,
|
||||
0x0205002b, 0x02040000, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204f103, 0x0205002b, 0x02040000,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204f104,
|
||||
0x0205002b, 0x020400f5, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204f105, 0x0205002b, 0x02040023,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204f109,
|
||||
0x0205002b, 0x02040004, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204f10a, 0x0205002b, 0x0204000b,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204f10b,
|
||||
0x0205002b, 0x0204004c, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204f10b, 0x0205002b, 0x0204005c,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02044100, 0x02050029, 0x02041888,
|
||||
0x0205002b, 0x02040000, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204c121, 0x0205002b, 0x0204000b,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204f102,
|
||||
0x0205002b, 0x02040000, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204f103, 0x0205002b, 0x02040000,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204f104,
|
||||
0x0205002b, 0x020400f5, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204f105, 0x0205002b, 0x02040023,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204f109,
|
||||
0x0205002b, 0x02040000, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204f10a, 0x0205002b, 0x0204000b,
|
||||
0x0205002c, 0x0204b423, 0x02050027, 0x02040010,
|
||||
0x02050028, 0x02040000, 0x02050029, 0x0204f10b,
|
||||
0x0205002b, 0x0204004c, 0x0205002c, 0x0204b423,
|
||||
0x02050027, 0x02040010, 0x02050028, 0x02040000,
|
||||
0x02050029, 0x0204f10b, 0x0205002b, 0x0204005c,
|
||||
0x0205002c, 0x0204b423,
|
||||
|
||||
// XXX: Duplicate last 2 u32s to keep in 4-dword blocks
|
||||
0x0205002c, 0x0204b423,
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
111
src/mainboard/system76/rpl/variants/bonw15-b/overridetree.cb
Normal file
111
src/mainboard/system76/rpl/variants/bonw15-b/overridetree.cb
Normal file
@ -0,0 +1,111 @@
|
||||
chip soc/intel/alderlake
|
||||
# Support 5600 MT/s memory
|
||||
register "max_dram_speed_mts" = "5600"
|
||||
|
||||
device domain 0 on
|
||||
subsystemid 0x1558 0x3702 inherit
|
||||
|
||||
device ref xhci on
|
||||
register "usb2_ports" = "{
|
||||
[0] = USB2_PORT_MID(OC_SKIP), /* Type-A 3.2 Gen 2 (Left, Front) */
|
||||
[1] = USB2_PORT_MID(OC_SKIP), /* Type-A 3.2 Gen 2 (Left, Rear) */
|
||||
[5] = USB2_PORT_MID(OC_SKIP), /* Camera */
|
||||
[6] = USB2_PORT_MID(OC_SKIP), /* Per-key RGB */
|
||||
/* Port reset messaging cannot be used,
|
||||
* so do not use USB2_PORT_TYPE_C for these */
|
||||
[8] = USB2_PORT_MID(OC_SKIP), /* Type-C Thunderbolt (Right, Front) */
|
||||
[9] = USB2_PORT_MID(OC_SKIP), /* Type-C Thunderbolt with PD (Right, Rear) */
|
||||
[13] = USB2_PORT_MID(OC_SKIP), /* Bluetooth */
|
||||
}"
|
||||
register "usb3_ports" = "{
|
||||
[0] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A 3.2 Gen 2 (Left, Front) */
|
||||
[2] = USB3_PORT_DEFAULT(OC_SKIP), /* Type-A 3.2 Gen 2 (Left, Rear) */
|
||||
}"
|
||||
end
|
||||
|
||||
device ref i2c0 on
|
||||
# Touchpad I2C bus
|
||||
register "serial_io_i2c_mode[PchSerialIoIndexI2C0]" = "PchSerialIoPci"
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""ELAN0412""
|
||||
register "generic.desc" = ""ELAN Touchpad""
|
||||
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E7)"
|
||||
register "generic.detect" = "1"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 15 on end
|
||||
end
|
||||
chip drivers/i2c/hid
|
||||
register "generic.hid" = ""FTCS1000""
|
||||
register "generic.desc" = ""FocalTech Touchpad""
|
||||
register "generic.irq_gpio" = "ACPI_GPIO_IRQ_LEVEL_LOW(GPP_E7)"
|
||||
register "generic.detect" = "1"
|
||||
register "hid_desc_reg_offset" = "0x01"
|
||||
device i2c 38 on end
|
||||
end
|
||||
end
|
||||
|
||||
device ref pcie5_0 on
|
||||
# CPU PCIe RP#3 x4, CLKOUT 2, CLKREQ 11 (SSD2)
|
||||
register "cpu_pcie_rp[CPU_RP(2)]" = "{
|
||||
.clk_src = 2,
|
||||
.clk_req = 11,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
end
|
||||
|
||||
device ref pcie5_1 on
|
||||
# CPU PCIe RP#2 x8, Clock 14 (DGPU)
|
||||
register "cpu_pcie_rp[CPU_RP(3)]" = "{
|
||||
.clk_src = 14,
|
||||
.clk_req = 14,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
end
|
||||
|
||||
device ref pcie4_0 on
|
||||
# CPU PCIe RP#1 x4, Clock 12 (SSD3)
|
||||
register "cpu_pcie_rp[CPU_RP(1)]" = "{
|
||||
.clk_src = 12,
|
||||
.clk_req = 12,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
end
|
||||
|
||||
device ref pcie_rp7 on
|
||||
# PCH RP#7 x1, Clock 13 (GLAN)
|
||||
register "pch_pcie_rp[PCH_RP(7)]" = "{
|
||||
.clk_src = 15,
|
||||
.clk_req = 15,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
device pci 00.0 on end
|
||||
end
|
||||
|
||||
device ref pcie_rp8 on
|
||||
# PCH RP#8 x1, Clock 9 (WLAN)
|
||||
register "pch_pcie_rp[PCH_RP(8)]" = "{
|
||||
.clk_src = 9,
|
||||
.clk_req = 9,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
end
|
||||
|
||||
device ref pcie_rp9 on
|
||||
# PCH RP#9 x4, Clock 15 (TBT)
|
||||
register "pch_pcie_rp[PCH_RP(9)]" = "{
|
||||
.clk_src = 13,
|
||||
.clk_req = 13,
|
||||
.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR,
|
||||
}"
|
||||
end
|
||||
|
||||
device ref pcie_rp21 on
|
||||
# PCH RP#21 x4, Clock 10 (SSD1)
|
||||
register "pch_pcie_rp[PCH_RP(21)]" = "{
|
||||
.clk_src = 10,
|
||||
.clk_req = 10,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
end
|
||||
end
|
||||
end
|
||||
32
src/mainboard/system76/rpl/variants/bonw15-b/romstage.c
Normal file
32
src/mainboard/system76/rpl/variants/bonw15-b/romstage.c
Normal file
@ -0,0 +1,32 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <soc/meminit.h>
|
||||
#include <soc/romstage.h>
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
{
|
||||
const struct mb_cfg board_cfg = {
|
||||
.type = MEM_TYPE_DDR5,
|
||||
.ect = true,
|
||||
.LpDdrDqDqsReTraining = 1,
|
||||
.ddr_config = {
|
||||
.dq_pins_interleaved = true,
|
||||
},
|
||||
};
|
||||
const struct mem_spd spd_info = {
|
||||
.topo = MEM_TOPO_DIMM_MODULE,
|
||||
.smbus = {
|
||||
[0] = { .addr_dimm[0] = 0x50, },
|
||||
[1] = { .addr_dimm[0] = 0x52, },
|
||||
},
|
||||
};
|
||||
const bool half_populated = false;
|
||||
|
||||
// Set primary display to internal graphics
|
||||
mupd->FspmConfig.PrimaryDisplay = 0;
|
||||
|
||||
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
|
||||
mupd->FspmConfig.GpioOverride = 0;
|
||||
|
||||
memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
|
||||
}
|
||||
Loading…
x
Reference in New Issue
Block a user