soc/intel/xeon_sp: Add get_cxl_mode

Configuration variable implementation (VPD, et al) is regarded to
be mainboard specific and should not be bounded to SoC codes.

Add get_cxl_mode so that SoC codes do not need to get this
configuration from VPD any more.

TEST=Build and boot on intel/archercity CRB with no significant log
differences

Change-Id: I1e08e92ad769112d7e570ee12cf973451a3befc0
Signed-off-by: Shuo Liu <shuo.liu@intel.com>
Signed-off-by: Jincheng Li <jincheng.li@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82092
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Lean Sheng Tan <sheng.tan@9elements.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>

src/drivers/ocp/include/vpd.h

@@ -3,6 +3,8 @@
 #ifndef OCP_VPD_H
 #define OCP_VPD_H
 
+#include <include/types.h>
+
 /* VPD variable for enabling/disabling FRB2 timer. 1/0: Enable/disable */
 #define FRB2_TIMER "frb2_timer_enable"
 #define FRB2_TIMER_DEFAULT 1 /* Default value when the VPD variable is not found */

src/mainboard/intel/archercity_crb/Makefile.mk

@@ -2,5 +2,7 @@
 
 bootblock-y += bootblock.c
 romstage-y += romstage.c
+romstage-y += util.c
 ramstage-y += ramstage.c
+ramstage-y += util.c
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include

src/mainboard/intel/archercity_crb/util.c

@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/ocp/include/vpd.h>
+#include <soc/chip_common.h>
+#include <soc/util.h>
+
+#if CONFIG(SOC_INTEL_HAS_CXL)
+enum xeonsp_cxl_mode get_cxl_mode(void)
+{
+	int ocp_cxl_mode = get_cxl_mode_from_vpd();
+	switch (ocp_cxl_mode) {
+	case CXL_SYSTEM_MEMORY:
+		return XEONSP_CXL_SYS_MEM;
+	case CXL_SPM:
+		return XEONSP_CXL_SP_MEM;
+	default:
+		return XEONSP_CXL_DISABLED;
+	}
+}
+#endif

src/mainboard/inventec/transformers/Makefile.mk

@@ -2,5 +2,7 @@
 
 bootblock-y += bootblock.c
 romstage-y += romstage.c
+romstage-y += util.c
 romstage-$(CONFIG_IPMI_KCS_ROMSTAGE) += ipmi.c
+ramstage-y += util.c
 CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include

src/mainboard/inventec/transformers/util.c

@@ -0,0 +1,20 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#include <drivers/ocp/include/vpd.h>
+#include <soc/chip_common.h>
+#include <soc/util.h>
+
+#if CONFIG(SOC_INTEL_HAS_CXL)
+enum xeonsp_cxl_mode get_cxl_mode(void)
+{
+	int ocp_cxl_mode = get_cxl_mode_from_vpd();
+	switch (ocp_cxl_mode) {
+	case CXL_SYSTEM_MEMORY:
+		return XEONSP_CXL_SYS_MEM;
+	case CXL_SPM:
+		return XEONSP_CXL_SP_MEM;
+	default:
+		return XEONSP_CXL_DISABLED;
+	}
+}
+#endif

src/soc/intel/xeon_sp/include/soc/chip_common.h

@@ -33,6 +33,12 @@ static inline void init_xeon_domain_path(struct device_path *path, int socket,
 	path->domain.domain = dp.domain_path;
 };
 
+enum xeonsp_cxl_mode {
+	XEONSP_CXL_DISABLED = 0,
+	XEONSP_CXL_SYS_MEM,
+	XEONSP_CXL_SP_MEM,
+};
+
 /*
  * Every STACK can have multiple PCI domains with an unique domain type.
  * This is only of cosmetic nature and generates more readable ACPI code,

src/soc/intel/xeon_sp/include/soc/util.h

@@ -28,4 +28,6 @@ bool is_ioat_iio_stack_res(const xSTACK_RES *res);
 bool is_iio_cxl_stack_res(const xSTACK_RES *res);
 void bios_done_msr(void *unused);
 
+enum xeonsp_cxl_mode get_cxl_mode(void);
+
 #endif

src/soc/intel/xeon_sp/spr/romstage.c

@@ -13,12 +13,14 @@
 #include <fsp/util.h>
 #include <hob_iiouds.h>
 #include <hob_memmap.h>
+#include <soc/chip_common.h>
 #include <soc/romstage.h>
 #include <soc/pci_devs.h>
 #include <soc/soc_pch.h>
 #include <soc/intel/common/smbios.h>
 #include <string.h>
 #include <soc/soc_util.h>
+#include <soc/util.h>
 #include <soc/ddr.h>
 
 #include "chip.h"
@@ -39,7 +41,7 @@ void __weak mainboard_memory_init_params(FSPM_UPD *mupd)
 static void config_upd_from_vpd(FSPM_UPD *mupd)
 {
 	uint8_t val;
-	int val_int, cxl_mode;
+	int val_int;
 
 	/* Send FSP log message to SOL */
 	if (vpd_get_bool(FSP_LOG, VPD_RW_THEN_RO, &val))
@@ -97,8 +99,8 @@ static void config_upd_from_vpd(FSPM_UPD *mupd)
 		mupd->FspmConfig.DfxPmicSecureMode = FSP_PMIC_SECURE_MODE_DEFAULT;
 	}
 
-	cxl_mode = get_cxl_mode_from_vpd();
-	if (cxl_mode == CXL_SYSTEM_MEMORY || cxl_mode == CXL_SPM)
+	int cxl_mode = get_cxl_mode();
+	if (cxl_mode == XEONSP_CXL_SYS_MEM || cxl_mode == XEONSP_CXL_SP_MEM)
 		mupd->FspmConfig.DfxCxlType3LegacyEn = 1;
 	else /* Disable CXL */
 		mupd->FspmConfig.DfxCxlType3LegacyEn = 0;

src/soc/intel/xeon_sp/uncore.c

@@ -6,8 +6,8 @@
 #include <cpu/x86/lapic_def.h>
 #include <device/pci.h>
 #include <device/pci_ids.h>
-#include <drivers/ocp/include/vpd.h>
 #include <soc/acpi.h>
+#include <soc/chip_common.h>
 #include <soc/iomap.h>
 #include <soc/pci_devs.h>
 #include <soc/ramstage.h>
@@ -286,10 +286,9 @@ static void mc_add_dram_resources(struct device *dev, int *res_count)
 			if (pds.pds[i].pd_type == PD_TYPE_PROCESSOR)
 				continue;
 
-			if (CONFIG(OCP_VPD)) {
 			unsigned long flags = IORESOURCE_CACHEABLE;
-				int cxl_mode = get_cxl_mode_from_vpd();
-				if (cxl_mode == CXL_SPM)
+			int cxl_mode = get_cxl_mode();
+			if (cxl_mode == XEONSP_CXL_SP_MEM)
 				flags |= IORESOURCE_SOFT_RESERVE;
 			else
 				flags |= IORESOURCE_STORED;
@@ -297,12 +296,11 @@ static void mc_add_dram_resources(struct device *dev, int *res_count)
 			res = fixed_mem_range_flags(dev, index++,
 				(uint64_t)pds.pds[i].base << 26,
 				(uint64_t)pds.pds[i].size << 26, flags);
-				if (cxl_mode == CXL_SPM)
+			if (cxl_mode == XEONSP_CXL_SP_MEM)
 				LOG_RESOURCE("specific_purpose_memory", dev, res);
 			else
 				LOG_RESOURCE("CXL_memory", dev, res);
 		}
-		}
 	} else {
 		/* 4GiB -> TOHM */
 		res = upper_ram_end(dev, index++, mc_values[TOHM_REG] + 1);

src/soc/intel/xeon_sp/util.c

@@ -237,3 +237,8 @@ void set_bios_init_completion(void)
 	set_bios_init_completion_for_package(sbsp_socket_id);
 }
 #endif
+
+__weak enum xeonsp_cxl_mode get_cxl_mode(void)
+{
+	return XEONSP_CXL_DISABLED;
+}