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mb/google/cherry: configure GPIOs

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Configure Chromebook specific GPIOs, including EC_AP_INT,
SD_CD, EC_IN_RW, GSC_AP_INT and EN_SPK.

Change-Id: Id553f632412af440d21a3b51e017cb74cc27fd22
Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/52924
Reviewed-by: Yu-Ping Wu <yupingso@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Yu-Ping Wu
2021-04-01 16:11:25 +08:00
committed by Hung-Te Lin
parent ce6fdd458b
commit a21797a51e
3 changed files with 43 additions and 1 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/google/cherry/bootblock.c
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@@ -4,6 +4,8 @@
#include <device/mmio.h>
#include <soc/gpio.h>
#include "gpio.h"
struct pad_func {
u8 pin_id;
u8 func;
@@ -34,4 +36,5 @@ static void nor_set_gpio_pinmux(void)
void bootblock_mainboard_init(void)
{
nor_set_gpio_pinmux();
setup_chromeos_gpios();
}

23
src/mainboard/google/cherry/chromeos.c
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@@ -2,10 +2,31 @@
#include <bootmode.h>
#include <boot/coreboot_tables.h>
#include <gpio.h>
#include "gpio.h"
void setup_chromeos_gpios(void)
{
gpio_input(GPIO_WP);
gpio_input_pullup(GPIO_EC_AP_INT);
gpio_input_pullup(GPIO_SD_CD);
gpio_input_pullup(GPIO_EC_IN_RW);
gpio_input_pullup(GPIO_GSC_AP_INT);
gpio_output(GPIO_EN_SPK, 0);
gpio_output(GPIO_RESET, 0);
}
void fill_lb_gpios(struct lb_gpios *gpios)
{
struct lb_gpio chromeos_gpios[] = {
{GPIO_EC_AP_INT.id, ACTIVE_LOW, -1, "EC interrupt"},
{GPIO_SD_CD.id, ACTIVE_LOW, -1, "SD card detect"},
{GPIO_EC_IN_RW.id, ACTIVE_LOW, -1, "EC in RW"},
{GPIO_GSC_AP_INT.id, ACTIVE_LOW, -1, "TPM interrupt"},
{GPIO_EN_SPK.id, ACTIVE_HIGH, -1, "speaker enable"},
};
lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
}
int get_recovery_mode_switch(void)

18
src/mainboard/google/cherry/gpio.h Normal file
View File

@@ -0,0 +1,18 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef __MAINBOARD_GOOGLE_CHERRY_GPIO_H__
#define __MAINBOARD_GOOGLE_CHERRY_GPIO_H__
#include <soc/gpio.h>
#define GPIO_EC_AP_INT GPIO(GPIO_04)
#define GPIO_WP GPIO(GPIO_05)
#define GPIO_SD_CD GPIO(I2SO1_D1)
#define GPIO_EC_IN_RW GPIO(DGI_D10)
#define GPIO_GSC_AP_INT GPIO(DGI_D11)
#define GPIO_EN_SPK GPIO(UART1_RTS)
#define GPIO_RESET GPIO(UART1_CTS)
void setup_chromeos_gpios(void);
#endif