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mb/system76/adl-p: Remove CPU PCIe RP RTD3 config

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This has caused nothing but issues trying to get different drives to
behave correctly. Just remove it.

Change-Id: I5ed36c519fa7757034172f146fb5e03a15f40ede
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
2022-10-26 09:53:54 -06:00
committed by Tim Crawford
parent 509a5160a6
commit a3b0137431
5 changed files with 0 additions and 46 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/system76/adl-p/variants/darp8/overridetree.cb
View File

@@ -22,12 +22,6 @@ chip soc/intel/alderlake
.clk_req = 0,
.flags = PCIE_RP_LTR,
}"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD2_PWR_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_CPU_SSD2_RST#
register "srcclk_pin" = "0" # SSD2_CLKREQ#
device generic 0 on end
end
end
device ref tcss_xhci on
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"

6
src/mainboard/system76/adl-p/variants/galp6/overridetree.cb
View File

@@ -20,12 +20,6 @@ chip soc/intel/alderlake
.clk_req = 0,
.flags = PCIE_RP_LTR,
}"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD1_PWR_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_SSD1_RST#
register "srcclk_pin" = "0" # SSD1_CLKREQ#
device generic 0 on end
end
end
device ref tcss_xhci on
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"

6
src/mainboard/system76/adl-p/variants/lemp11/overridetree.cb
View File

@@ -20,12 +20,6 @@ chip soc/intel/alderlake
.clk_req = 0,
.flags = PCIE_RP_LTR,
}"
chip soc/intel/common/block/pcie/rtd3
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # SSD2_PWR_EN
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F20)" # M2_CPU_SSD2_RST#
register "srcclk_pin" = "0" # SSD0_CLKREQ#
device generic 0 on end
end
end
device ref tcss_xhci on
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"

14
src/mainboard/system76/adl-p/variants/oryp10/overridetree.cb
View File

@@ -41,13 +41,6 @@ chip soc/intel/alderlake
.clk_req = 0,
.flags = PCIE_RP_LTR,
}"
# FIXME: WD drives fail to suspend
#chip soc/intel/common/block/pcie/rtd3
# register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # M2_PWR_EN1
# register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
# register "srcclk_pin" = "0" # SSD0_CLKREQ#
# device generic 0 on end
#end
end
device ref pcie4_1 on
# CPU PCIe RP#3 x4, Clock 4 (SSD2)
@@ -56,13 +49,6 @@ chip soc/intel/alderlake
.clk_req = 4,
.flags = PCIE_RP_LTR,
}"
# FIXME: WD drives fail to suspend
#chip soc/intel/common/block/pcie/rtd3
# register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C2)" # M2_PWR_EN2
# register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
# register "srcclk_pin" = "4" # SSD1_CLKREQ#
# device generic 0 on end
#end
end
device ref tcss_xhci on
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"

14
src/mainboard/system76/adl-p/variants/oryp9/overridetree.cb
View File

@@ -41,13 +41,6 @@ chip soc/intel/alderlake
.clk_req = 0,
.flags = PCIE_RP_LTR,
}"
# FIXME: WD drives fail to suspend
#chip soc/intel/common/block/pcie/rtd3
# register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # M2_PWR_EN1
# register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
# register "srcclk_pin" = "0" # SSD0_CLKREQ#
# device generic 0 on end
#end
end
device ref pcie4_1 on
# CPU PCIe RP#3 x4, Clock 4 (SSD2)
@@ -56,13 +49,6 @@ chip soc/intel/alderlake
.clk_req = 4,
.flags = PCIE_RP_LTR,
}"
# FIXME: WD drives fail to suspend
#chip soc/intel/common/block/pcie/rtd3
# register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C2)" # M2_PWR_EN2
# register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
# register "srcclk_pin" = "4" # SSD1_CLKREQ#
# device generic 0 on end
#end
end
device ref tcss_xhci on
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"