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mb/google/brya: change NAU8825 config to fix headset button detection

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Brya/brask devices using NAU88L25 are not recognizing headset buttons
correctly. The reason is we are using wrong reference voltage of
MICBIAS. Use VDDA instead.

BUG=b:352215240
TEST=test with 3.5mm headset with buttons on volume up/down and pause

Change-Id: I0619021c6fd0a196c318aee58e07dc4149f1d64e
Signed-off-by: Terry Cheong <htcheong@chromium.org>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83470
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
This commit is contained in:
Terry Cheong 2024-07-15 19:08:47 +08:00 committed by Felix Held
parent bd51c60322
commit a3d5444b54
9 changed files with 9 additions and 9 deletions
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2
src/mainboard/google/brya/variants/aurash/overridetree.cb
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@ -147,7 +147,7 @@ chip soc/intel/alderlake
register "sar_threshold[2]" = "0x38"
register "sar_threshold[3]" = "0x60"
register "sar_hysteresis" = "1"
register "sar_voltage" = "6"
register "sar_voltage" = "0" # VDDA
register "sar_compare_time" = "0" # 500ns
register "sar_sampling_time" = "0" # 2us
register "short_key_debounce" = "2" # 100ms

2
src/mainboard/google/brya/variants/brask/overridetree.cb
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@ -124,7 +124,7 @@ chip soc/intel/alderlake
register "sar_threshold[2]" = "0x38"
register "sar_threshold[3]" = "0x60"
register "sar_hysteresis" = "1"
register "sar_voltage" = "6"
register "sar_voltage" = "0" # VDDA
register "sar_compare_time" = "0" # 500ns
register "sar_sampling_time" = "0" # 2us
register "short_key_debounce" = "2" # 100ms

2
src/mainboard/google/brya/variants/gaelin/overridetree.cb
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@ -184,7 +184,7 @@ chip soc/intel/alderlake
register "sar_threshold[2]" = "0x38"
register "sar_threshold[3]" = "0x60"
register "sar_hysteresis" = "1"
register "sar_voltage" = "6"
register "sar_voltage" = "0" # VDDA
register "sar_compare_time" = "0" # 500ns
register "sar_sampling_time" = "0" # 2us
register "short_key_debounce" = "2" # 100ms

2
src/mainboard/google/brya/variants/kano/overridetree.cb
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@ -278,7 +278,7 @@ chip soc/intel/alderlake
register "sar_threshold[2]" = "0x38"
register "sar_threshold[3]" = "0x60"
register "sar_hysteresis" = "1"
register "sar_voltage" = "6"
register "sar_voltage" = "0" # VDDA
register "sar_compare_time" = "0" # 500ns
register "sar_sampling_time" = "0" # 2us
register "short_key_debounce" = "2" # 100ms

2
src/mainboard/google/brya/variants/kuldax/overridetree.cb
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@ -187,7 +187,7 @@ chip soc/intel/alderlake
register "sar_threshold[2]" = "0x38"
register "sar_threshold[3]" = "0x60"
register "sar_hysteresis" = "1"
register "sar_voltage" = "6"
register "sar_voltage" = "0" # VDDA
register "sar_compare_time" = "0" # 500ns
register "sar_sampling_time" = "0" # 2us
register "short_key_debounce" = "2" # 100ms

2
src/mainboard/google/brya/variants/moli/overridetree.cb
View File

@ -148,7 +148,7 @@ chip soc/intel/alderlake
register "sar_threshold[2]" = "0x38"
register "sar_threshold[3]" = "0x60"
register "sar_hysteresis" = "1"
register "sar_voltage" = "6"
register "sar_voltage" = "0" # VDDA
register "sar_compare_time" = "0" # 500ns
register "sar_sampling_time" = "0" # 2us
register "short_key_debounce" = "2" # 100ms

2
src/mainboard/google/brya/variants/osiris/overridetree.cb
View File

@ -226,7 +226,7 @@ chip soc/intel/alderlake
register "sar_threshold[2]" = "0x38"
register "sar_threshold[3]" = "0x60"
register "sar_hysteresis" = "1"
register "sar_voltage" = "6"
register "sar_voltage" = "0" # VDDA
register "sar_compare_time" = "0" # 500ns
register "sar_sampling_time" = "0" # 2us
register "short_key_debounce" = "2" # 100ms

2
src/mainboard/google/brya/variants/volmar/overridetree.cb
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@ -240,7 +240,7 @@ chip soc/intel/alderlake
register "sar_threshold[2]" = "0x38"
register "sar_threshold[3]" = "0x60"
register "sar_hysteresis" = "1"
register "sar_voltage" = "6"
register "sar_voltage" = "0" # VDDA
register "sar_compare_time" = "0" # 500ns
register "sar_sampling_time" = "0" # 2us
register "short_key_debounce" = "2" # 100ms

2
src/mainboard/google/brya/variants/zydron/overridetree.cb
View File

@ -254,7 +254,7 @@ chip soc/intel/alderlake
register "sar_threshold[2]" = "0x38"
register "sar_threshold[3]" = "0x60"
register "sar_hysteresis" = "1"
register "sar_voltage" = "6"
register "sar_voltage" = "0" # VDDA
register "sar_compare_time" = "0" # 500ns
register "sar_sampling_time" = "0" # 2us
register "short_key_debounce" = "2" # 100ms