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soc/intel/alderlake: Correct PCH-S XHCI port information

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Change-Id: I405b4f73584f4391152941bbd32e828a2bd0e6aa
This commit is contained in:
Jeremy Soller
2023-03-21 13:39:23 -06:00
parent 20c9608c05
commit a55e829ae3
1 changed files with 7 additions and 0 deletions
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7
src/soc/intel/alderlake/xhci.c
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@@ -9,10 +9,17 @@
* as well as doc# 626817, ADL-P PCH EDS Vol. 1
*/
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_S)
#define PCH_XHCI_USB2_PORT_STATUS_REG 0x480
#define PCH_XHCI_USB3_PORT_STATUS_REG 0x580
#define PCH_XHCI_USB2_PORT_NUM 14
#define PCH_XHCI_USB3_PORT_NUM 10
#else
#define PCH_XHCI_USB2_PORT_STATUS_REG 0x480
#define PCH_XHCI_USB3_PORT_STATUS_REG 0x540
#define PCH_XHCI_USB2_PORT_NUM 10
#define PCH_XHCI_USB3_PORT_NUM 4
#endif
#define TCSS_XHCI_USB2_PORT_STATUS_REG 0x480
#define TCSS_XHCI_USB3_PORT_STATUS_REG 0x490