drivers/intel/fsp2_0: Make coreboot FSP stack 16-bytes aligned

- Stack alignment:

  1. FSP functions must be called with the stack 16-bytes aligned
     in x86_64 mode.This is already setup properly with the default
     value of the `mpreferred-stack-boundary' compiler option (4).

  2. The FSP heap buffer supplied by coreboot through the `StackBase'
     UPD must be 16-bytes aligned. This alignment is consistent for
     both x86_64 and x86_32 modes to simplify the implementation.

BUG=b:329034258
TEST=Verified on Meteor Lake board (Rex)

Change-Id: I86048c5d3623a29f17a5e492cd67568e4844589c
Signed-off-by: Appukuttan V K <appukuttan.vk@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81661
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>

src/drivers/intel/fsp2_0/memory_init.c

@@ -34,7 +34,7 @@ void __weak platform_fsp_memory_multi_phase_init_cb(uint32_t phase_index)
 	/* Leave for the SoC/Mainboard to implement if necessary. */
 }
 
-static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(sizeof(uint64_t));
+static uint8_t temp_ram[CONFIG_FSP_TEMP_RAM_SIZE] __aligned(16);
 
 /*
  * Helper function to store the MRC cache version into CBMEM