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mb/google/brya/var/xol: Add EC_IN_RW_OD config into early_gpio_table

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Add GPP_F18 configuration in early_gpio_table.
Without this, DUT cannot get the proper state of this signal on early
phase. It allowed DUT to attempt to enter into dev mode when EC is in RW
currently, it causes the failure of autotest/firmware_DevMode.

BUG=b:337365524
TEST=built and run autotest firmware_DevMode

Change-Id: I2179bb10b431547bc35f332c74915a63495b779d
Signed-off-by: Seunghwan Kim <sh_.kim@samsung.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/82099
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: YH Lin <yueherngl@google.com>
This commit is contained in:
Seunghwan Kim 2024-04-29 11:20:50 +09:00 committed by Nick Vaccaro
parent c7db3d0f08
commit 9493c2ece2
1 changed files with 2 additions and 0 deletions
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2
src/mainboard/google/brya/variants/xol/gpio.c
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@ -195,6 +195,8 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_GPI(GPP_E13, NONE, DEEP),
/* E15 : RSVD_TP ==> PCH_WP_OD */
PAD_CFG_GPI_GPIO_DRIVER(GPP_E15, NONE, DEEP),
/* F18 : EC_IN_RW_OD ==> EC_IN_RW_OD */
PAD_CFG_GPI(GPP_F18, NONE, DEEP),
/* H6 : I2C1_SDA ==> PCH_I2C_TPM_SDA */
PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1),
/* H7 : I2C1_SCL ==> PCH_I2C_TPM_SCL */