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nb/intel/i945: Define and use MMCONF_BUS_NUMBER

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Change-Id: I5c75409fd3b7b018e402c471cbd856eca20278b7
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49757
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Angel Pons
2021-01-20 13:00:02 +01:00
parent 1ac6f8b804
commit a6b0922aa1
6 changed files with 21 additions and 60 deletions
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16
src/northbridge/intel/i945/bootblock.c
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@@ -1,13 +1,23 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/bootblock.h>
#include <assert.h>
#include <device/pci_ops.h>
#include <types.h>
#include "i945.h"
static uint32_t encode_pciexbar_length(void)
{
switch (CONFIG_MMCONF_BUS_NUMBER) {
case 256: return 0 << 1;
case 128: return 1 << 1;
case 64: return 2 << 1;
default: return dead_code_t(uint32_t);
}
}
void bootblock_early_northbridge_init(void)
{
uint32_t reg;
/*
* The "io" variant of the config access is explicitly used to setup the PCIEXBAR
* because CONFIG(MMCONF_SUPPORT) is set to true. That way all subsequent non-explicit
@@ -17,6 +27,6 @@ void bootblock_early_northbridge_init(void)
*
* The PCIEXBAR is assumed to live in the memory mapped IO space under 4GiB.
*/
reg = CONFIG_MMCONF_BASE_ADDRESS | 4 | 1; /* 64MiB - 0-63 buses. */
const uint32_t reg = CONFIG_MMCONF_BASE_ADDRESS | encode_pciexbar_length() | 1;
pci_io_write_config32(HOST_BRIDGE, PCIEXBAR, reg);
}