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intel/gma: consolidate vbt code

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Change-Id: I80b7facfb9cc9f642dd1c766884dc23da1aab2c8
Signed-off-by: Vladimir Serbinenko <phcoder@gmail.com>
Reviewed-on: http://review.coreboot.org/6800
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
This commit is contained in:
Vladimir Serbinenko 2014-08-30 00:35:39 +02:00
parent 85620db107
commit a71bdc3181
25 changed files with 287 additions and 533 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
src/drivers/intel/gma/Makefile.inc
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@ -19,7 +19,7 @@
ramstage-$(CONFIG_INTEL_DP) += intel_dp.c drm_dp_helper.c display.c ramstage-$(CONFIG_INTEL_DP) += intel_dp.c drm_dp_helper.c display.c
ramstage-$(CONFIG_INTEL_DDI) += intel_ddi.c ramstage-$(CONFIG_INTEL_DDI) += intel_ddi.c
ramstage-$(CONFIG_INTEL_EDID) += edid.c ramstage-$(CONFIG_INTEL_EDID) += edid.c vbt.c
ifeq ($(CONFIG_VGA_ROM_RUN),y) ifeq ($(CONFIG_VGA_ROM_RUN),y)
ramstage-$(CONFIG_INTEL_INT15) += int15.c ramstage-$(CONFIG_INTEL_INT15) += int15.c
endif endif

19
src/drivers/intel/gma/i915.h
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@ -17,6 +17,9 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#ifndef INTEL_I915_H
#define INTEL_I915_H 1
#include <drivers/intel/gma/i915_reg.h> #include <drivers/intel/gma/i915_reg.h>
#include <drivers/intel/gma/drm_dp_helper.h> #include <drivers/intel/gma/drm_dp_helper.h>
#include <edid.h> #include <edid.h>
@ -282,6 +285,14 @@ int gtt_poll(u32 reg, u32 mask, u32 value);
void gtt_write(u32 reg, u32 data); void gtt_write(u32 reg, u32 data);
u32 gtt_read(u32 reg); u32 gtt_read(u32 reg);
struct i915_gpu_controller_info
{
int use_spread_spectrum_clock;
int lvds_dual_channel;
int link_frequency_270_mhz;
int lvds_num_lanes;
};
int i915lightup(unsigned int physbase, unsigned int mmio, int i915lightup(unsigned int physbase, unsigned int mmio,
unsigned int gfx, unsigned int init_fb); unsigned int gfx, unsigned int init_fb);
int panel_lightup(struct intel_dp *dp, unsigned int init_fb); int panel_lightup(struct intel_dp *dp, unsigned int init_fb);
@ -289,3 +300,11 @@ void *igd_make_opregion(void);
/* display.c */ /* display.c */
void compute_display_params(struct intel_dp *dp); void compute_display_params(struct intel_dp *dp);
/* vbt.c */
struct device;
void
generate_fake_intel_oprom(const struct i915_gpu_controller_info *conf,
struct device *dev, const char *idstr);
#endif

52
src/drivers/intel/gma/intel_bios.h
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@ -730,4 +730,56 @@ struct bdb_mipi {
u32 clk_lane_switch_cnt; u32 clk_lane_switch_cnt;
} __attribute__((packed)); } __attribute__((packed));
/* Intel Video BIOS (Option ROM) */
typedef struct {
u16 signature;
u8 size;
u8 reserved[21];
u16 pcir_offset;
u16 vbt_offset;
} __attribute__((packed)) optionrom_header_t;
#define OPROM_SIGNATURE 0xaa55
typedef struct {
u32 signature;
u16 vendor;
u16 device;
u16 reserved1;
u16 length;
u8 revision;
u8 classcode[3];
u16 imagelength;
u16 coderevision;
u8 codetype;
u8 indicator;
u16 reserved2;
} __attribute__((packed)) optionrom_pcir_t;
typedef struct {
u8 hdr_signature[20];
u16 hdr_version;
u16 hdr_size;
u16 hdr_vbt_size;
u8 hdr_vbt_checksum;
u8 hdr_reserved;
u32 hdr_vbt_datablock;
u32 hdr_aim[4];
u8 datahdr_signature[16];
u16 datahdr_version;
u16 datahdr_size;
u16 datahdr_datablocksize;
u8 coreblock_id;
u16 coreblock_size;
u16 coreblock_biossize;
u8 coreblock_biostype;
u8 coreblock_releasestatus;
u8 coreblock_hwsupported;
u8 coreblock_integratedhw;
u8 coreblock_biosbuild[4];
u8 coreblock_biossignon[155];
} __attribute__((packed)) optionrom_vbt_t;
#define VBT_SIGNATURE 0x54425624
#endif /* _I830_BIOS_H_ */ #endif /* _I830_BIOS_H_ */

110
src/drivers/intel/gma/vbt.c Normal file
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@ -0,0 +1,110 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013, 2014 Vladimir Serbinenko
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 or (at your option)
* any later version of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program; if not, write to the Free Software
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/
#include <arch/io.h>
#include <console/console.h>
#include <delay.h>
#include <device/device.h>
#include <string.h>
#include <device/pci_rom.h>
#include "i915.h"
#include "intel_bios.h"
static size_t generate_vbt(const struct i915_gpu_controller_info *conf,
void *vbt, const char *idstr)
{
struct vbt_header *head = vbt;
struct bdb_header *bdb_head;
struct bdb_general_features *genfeat;
u8 *ptr;
memset (head, 0, sizeof (*head));
memcpy (head->signature, idstr, 20);
head->version = 100;
head->header_size = sizeof (*head);
head->bdb_offset = sizeof (*head);
bdb_head = (struct bdb_header *) (head + 1);
memset (bdb_head, 0, sizeof (*bdb_head));
memcpy (bdb_head->signature, "BIOS_DATA_BLOCK ", 16);
bdb_head->version = 0xa8;
bdb_head->header_size = sizeof (*bdb_head);
ptr = (u8 *) (bdb_head + 1);
ptr[0] = BDB_GENERAL_FEATURES;
ptr[1] = sizeof (*genfeat);
ptr[2] = sizeof (*genfeat) >> 8;
ptr += 3;
genfeat = (struct bdb_general_features *) ptr;
memset (genfeat, 0, sizeof (*genfeat));
genfeat->panel_fitting = 3;
genfeat->flexaim = 1;
genfeat->download_ext_vbt = 1;
genfeat->enable_ssc = conf->use_spread_spectrum_clock;
genfeat->ssc_freq = !conf->link_frequency_270_mhz;
genfeat->rsvd10 = 0x4;
genfeat->legacy_monitor_detect = 1;
genfeat->int_crt_support = 1;
genfeat->dp_ssc_enb = 1;
ptr += sizeof (*genfeat);
bdb_head->bdb_size = ptr - (u8 *)bdb_head;
head->vbt_size = ptr - (u8 *)head;
head->vbt_checksum = 0;
return ptr - (u8 *)head;
}
void
generate_fake_intel_oprom(const struct i915_gpu_controller_info *conf,
struct device *dev, const char *idstr)
{
optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START;
optionrom_pcir_t *pcir;
size_t vbt_size;
size_t fake_oprom_size;
memset(oh, 0, 8192);
oh->signature = PCI_ROM_HDR;
oh->pcir_offset = 0x40;
oh->vbt_offset = 0x80;
pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40);
pcir->signature = 0x52494350; // PCIR
pcir->vendor = dev->vendor;
pcir->device = dev->device;
pcir->length = sizeof(*pcir);
pcir->revision = dev->class;
pcir->classcode[0] = dev->class >> 8;
pcir->classcode[1] = dev->class >> 16;
pcir->classcode[2] = dev->class >> 24;
pcir->indicator = 0x80;
vbt_size = generate_vbt (conf, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80), idstr);
fake_oprom_size = (0x80 + vbt_size + 511) / 512;
oh->size = fake_oprom_size;
pcir->imagelength = fake_oprom_size;
}

1
src/include/smbios.h
View File

@ -19,6 +19,7 @@ const char *smbios_mainboard_serial_number(void);
const char *smbios_mainboard_version(void); const char *smbios_mainboard_version(void);
void smbios_mainboard_set_uuid(u8 *uuid); void smbios_mainboard_set_uuid(u8 *uuid);
const char *smbios_mainboard_bios_version(void); const char *smbios_mainboard_bios_version(void);
u8 smbios_mainboard_enclosure_type(void);
#define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7) #define BIOS_CHARACTERISTICS_PCI_SUPPORTED (1 << 7)
#define BIOS_CHARACTERISTICS_PC_CARD (1 << 8) #define BIOS_CHARACTERISTICS_PC_CARD (1 << 8)

2
src/mainboard/google/link/i915.c
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@ -236,7 +236,7 @@ static int run(int index)
return i+1; return i+1;
} }
int i915lightup(const struct northbridge_intel_sandybridge_config *info, int i915lightup_sandy(const struct i915_gpu_controller_info *info,
u32 pphysbase, u16 piobase, u32 pmmio, u32 pgfx) u32 pphysbase, u16 piobase, u32 pmmio, u32 pgfx)
{ {
static struct edid edid; static struct edid edid;

1
src/mainboard/google/link/i915io.c
View File

@ -18,6 +18,7 @@
*/ */
#include <stdint.h> #include <stdint.h>
#include <stdlib.h>
#include "i915io.h" #include "i915io.h"
struct iodef iodefs[] = { struct iodef iodefs[] = {

8
src/mainboard/lenovo/t530/devicetree.cb
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@ -10,10 +10,10 @@ chip northbridge/intel/sandybridge
register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms
register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms
register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms
register "gpu_use_spread_spectrum_clock" = "1" register "gfx.use_spread_spectrum_clock" = "1"
register "gpu_lvds_dual_channel" = "1" register "gfx.lvds_dual_channel" = "1"
register "gpu_link_frequency_270_mhz" = "1" register "gfx.link_frequency_270_mhz" = "1"
register "gpu_lvds_num_lanes" = "1" register "gfx.lvds_num_lanes" = "1"
register "gpu_cpu_backlight" = "0x1155" register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x11551155" register "gpu_pch_backlight" = "0x11551155"

8
src/mainboard/lenovo/x200/devicetree.cb
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@ -1,9 +1,9 @@
chip northbridge/intel/gm45 chip northbridge/intel/gm45
register "gpu_use_spread_spectrum_clock" = "1" register "gfx.use_spread_spectrum_clock" = "1"
register "gpu_lvds_dual_channel" = "0" register "gfx.lvds_dual_channel" = "0"
register "gpu_link_frequency_270_mhz" = "1" register "gfx.link_frequency_270_mhz" = "1"
register "gpu_lvds_num_lanes" = "4" register "gfx.lvds_num_lanes" = "4"
device cpu_cluster 0 on device cpu_cluster 0 on
chip cpu/intel/socket_BGA956 chip cpu/intel/socket_BGA956

8
src/mainboard/lenovo/x201/devicetree.cb
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@ -35,10 +35,10 @@ chip northbridge/intel/nehalem
register "gpu_panel_power_backlight_off_delay" = "2500" register "gpu_panel_power_backlight_off_delay" = "2500"
register "gpu_cpu_backlight" = "0x58d" register "gpu_cpu_backlight" = "0x58d"
register "gpu_pch_backlight" = "0x061a061a" register "gpu_pch_backlight" = "0x061a061a"
register "gpu_use_spread_spectrum_clock" = "1" register "gfx.use_spread_spectrum_clock" = "1"
register "gpu_lvds_dual_channel" = "0" register "gfx.lvds_dual_channel" = "0"
register "gpu_link_frequency_270_mhz" = "1" register "gfx.link_frequency_270_mhz" = "1"
register "gpu_lvds_num_lanes" = "4" register "gfx.lvds_num_lanes" = "4"
chip ec/lenovo/pmh7 chip ec/lenovo/pmh7
device pnp ff.1 on # dummy device pnp ff.1 on # dummy

8
src/mainboard/lenovo/x220/devicetree.cb
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@ -10,10 +10,10 @@ chip northbridge/intel/sandybridge
register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms register "gpu_panel_power_down_delay" = "300" # T5+T6: 30ms
register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms register "gpu_panel_power_backlight_on_delay" = "2000" # T3: 200ms
register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms register "gpu_panel_power_backlight_off_delay" = "2000" # T4: 200ms
register "gpu_use_spread_spectrum_clock" = "1" register "gfx.use_spread_spectrum_clock" = "1"
register "gpu_lvds_dual_channel" = "0" register "gfx.lvds_dual_channel" = "0"
register "gpu_link_frequency_270_mhz" = "1" register "gfx.link_frequency_270_mhz" = "1"
register "gpu_lvds_num_lanes" = "4" register "gfx.lvds_num_lanes" = "4"
register "gpu_cpu_backlight" = "0x1155" register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x06100610" register "gpu_pch_backlight" = "0x06100610"

8
src/mainboard/lenovo/x230/devicetree.cb
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@ -10,10 +10,10 @@ chip northbridge/intel/sandybridge
register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms register "gpu_panel_power_down_delay" = "100" # T5+T6: 10ms
register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms register "gpu_panel_power_backlight_on_delay" = "2100" # T3: 210ms
register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms register "gpu_panel_power_backlight_off_delay" = "2100" # T4: 210ms
register "gpu_use_spread_spectrum_clock" = "1" register "gfx.use_spread_spectrum_clock" = "1"
register "gpu_lvds_dual_channel" = "0" register "gfx.lvds_dual_channel" = "0"
register "gpu_link_frequency_270_mhz" = "1" register "gfx.link_frequency_270_mhz" = "1"
register "gpu_lvds_num_lanes" = "1" register "gfx.lvds_num_lanes" = "1"
register "gpu_cpu_backlight" = "0x1155" register "gpu_cpu_backlight" = "0x1155"
register "gpu_pch_backlight" = "0x11551155" register "gpu_pch_backlight" = "0x11551155"

8
src/mainboard/packardbell/ms2290/devicetree.cb
View File

@ -35,10 +35,10 @@ chip northbridge/intel/nehalem
register "gpu_panel_power_backlight_off_delay" = "3000" register "gpu_panel_power_backlight_off_delay" = "3000"
register "gpu_cpu_backlight" = "0x58d" register "gpu_cpu_backlight" = "0x58d"
register "gpu_pch_backlight" = "0x061a061a" register "gpu_pch_backlight" = "0x061a061a"
register "gpu_use_spread_spectrum_clock" = "0" register "gfx.use_spread_spectrum_clock" = "0"
register "gpu_lvds_dual_channel" = "1" register "gfx.lvds_dual_channel" = "1"
register "gpu_link_frequency_270_mhz" = "1" register "gfx.link_frequency_270_mhz" = "1"
register "gpu_lvds_num_lanes" = "4" register "gfx.lvds_num_lanes" = "4"
device cpu_cluster 0 on device cpu_cluster 0 on
chip cpu/intel/model_2065x chip cpu/intel/model_2065x

7
src/northbridge/intel/gm45/chip.h
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@ -21,11 +21,10 @@
#ifndef NORTHBRIDGE_INTEL_GM45_CHIP_H #ifndef NORTHBRIDGE_INTEL_GM45_CHIP_H
#define NORTHBRIDGE_INTEL_GM45_CHIP_H #define NORTHBRIDGE_INTEL_GM45_CHIP_H
#include <drivers/intel/gma/i915.h>
struct northbridge_intel_gm45_config { struct northbridge_intel_gm45_config {
int gpu_use_spread_spectrum_clock; struct i915_gpu_controller_info gfx;
int gpu_lvds_dual_channel;
int gpu_link_frequency_270_mhz;
int gpu_lvds_num_lanes;
}; };
#endif /* NORTHBRIDGE_INTEL_GM45_CHIP_H */ #endif /* NORTHBRIDGE_INTEL_GM45_CHIP_H */

126
src/northbridge/intel/gm45/gma.c
View File

@ -39,31 +39,6 @@
#include <pc80/vga.h> #include <pc80/vga.h>
#include <pc80/vga_io.h> #include <pc80/vga_io.h>
typedef struct {
u16 signature;
u8 size;
u8 reserved[21];
u16 pcir_offset;
u16 vbt_offset;
} __attribute__((packed)) optionrom_header_t;
#define OPROM_SIGNATURE 0xaa55
typedef struct {
u32 signature;
u16 vendor;
u16 device;
u16 reserved1;
u16 length;
u8 revision;
u8 classcode[3];
u16 imagelength;
u16 coderevision;
u8 codetype;
u8 indicator;
u16 reserved2;
} __attribute__((packed)) optionrom_pcir_t;
static struct resource *gtt_res = NULL; static struct resource *gtt_res = NULL;
void gtt_write(u32 reg, u32 data) void gtt_write(u32 reg, u32 data)
@ -144,7 +119,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
u32 pixel_n = 1; u32 pixel_n = 1;
u32 pixel_m1 = 1; u32 pixel_m1 = 1;
u32 pixel_m2 = 1; u32 pixel_m2 = 1;
u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000; u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000;
u32 data_m1; u32 data_m1;
u32 data_n1 = 0x00800000; u32 data_n1 = 0x00800000;
u32 link_m1; u32 link_m1;
@ -197,7 +172,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
hfront_porch = edid.hso; hfront_porch = edid.hso;
vfront_porch = edid.vso; vfront_porch = edid.vso;
target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock target_frequency = info->gfx.lvds_dual_channel ? edid.pixel_clock
: (2 * edid.pixel_clock); : (2 * edid.pixel_clock);
#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
vga_textmode_init(); vga_textmode_init();
@ -267,7 +242,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency;
data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock)
/ (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 4)); / (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4));
printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
hactive, vactive); hactive, vactive);
@ -279,10 +254,10 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
hsync, vsync); hsync, vsync);
printk(BIOS_DEBUG, "Front porch %d x %d\n", printk(BIOS_DEBUG, "Front porch %d x %d\n",
hfront_porch, vfront_porch); hfront_porch, vfront_porch);
printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock
? "Spread spectrum clock\n" : "DREF clock\n")); ? "Spread spectrum clock\n" : "DREF clock\n"));
printk(BIOS_DEBUG, printk(BIOS_DEBUG,
info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); info->gfx.lvds_dual_channel ? "Dual channel\n" : "Single channel\n");
printk(BIOS_DEBUG, "Polarities %d, %d\n", printk(BIOS_DEBUG, "Polarities %d, %d\n",
hpolarity, vpolarity); hpolarity, vpolarity);
printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n",
@ -299,7 +274,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
write32(mmio + LVDS, write32(mmio + LVDS,
(hpolarity << 20) | (vpolarity << 21) (hpolarity << 20) | (vpolarity << 21)
| (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL);
mdelay(1); mdelay(1);
@ -310,18 +285,18 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
| ((pixel_m1 - 2) << 8) | pixel_m2); | ((pixel_m1 - 2) << 8) | pixel_m2);
write32(mmio + DPLL(0), write32(mmio + DPLL(0),
DPLL_VCO_ENABLE | DPLLB_MODE_LVDS DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
| (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
: DPLLB_LVDS_P2_CLOCK_DIV_14) : DPLLB_LVDS_P2_CLOCK_DIV_14)
| (0x10000 << (pixel_p1 - 1)) | (0x10000 << (pixel_p1 - 1))
| ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
| (0x1 << (pixel_p1 - 1))); | (0x1 << (pixel_p1 - 1)));
mdelay(1); mdelay(1);
write32(mmio + DPLL(0), write32(mmio + DPLL(0),
DPLL_VCO_ENABLE | DPLLB_MODE_LVDS DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
| (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
: DPLLB_LVDS_P2_CLOCK_DIV_14) : DPLLB_LVDS_P2_CLOCK_DIV_14)
| (0x10000 << (pixel_p1 - 1)) | (0x10000 << (pixel_p1 - 1))
| ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
| (0x1 << (pixel_p1 - 1))); | (0x1 << (pixel_p1 - 1)));
/* Re-lock the registers. */ /* Re-lock the registers. */
write32(mmio + PP_CONTROL, write32(mmio + PP_CONTROL,
@ -329,7 +304,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
write32(mmio + LVDS, write32(mmio + LVDS,
(hpolarity << 20) | (vpolarity << 21) (hpolarity << 20) | (vpolarity << 21)
| (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL);
@ -423,7 +398,7 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
write32(mmio + LVDS, write32(mmio + LVDS,
LVDS_PORT_ENABLE LVDS_PORT_ENABLE
| (hpolarity << 20) | (vpolarity << 21) | (hpolarity << 20) | (vpolarity << 21)
| (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL); | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL);
@ -457,54 +432,6 @@ static void intel_gma_init(const struct northbridge_intel_gm45_config *info,
#endif #endif
} }
static size_t generate_vbt(const struct northbridge_intel_gm45_config *conf,
void *vbt)
{
struct vbt_header *head = vbt;
struct bdb_header *bdb_head;
struct bdb_general_features *genfeat;
u8 *ptr;
memset (head, 0, sizeof (*head));
memcpy (head->signature, "$VBT IRONLAKE-MOBILE", 20);
head->version = 100;
head->header_size = sizeof (*head);
head->bdb_offset = sizeof (*head);
bdb_head = (struct bdb_header *) (head + 1);
memset (bdb_head, 0, sizeof (*bdb_head));
memcpy (bdb_head->signature, "BIOS_DATA_BLOCK ", 16);
bdb_head->version = 0xa8;
bdb_head->header_size = sizeof (*bdb_head);
ptr = (u8 *) (bdb_head + 1);
ptr[0] = BDB_GENERAL_FEATURES;
ptr[1] = sizeof (*genfeat);
ptr[2] = sizeof (*genfeat) >> 8;
ptr += 3;
genfeat = (struct bdb_general_features *) ptr;
memset (genfeat, 0, sizeof (*genfeat));
genfeat->panel_fitting = 3;
genfeat->flexaim = 1;
genfeat->download_ext_vbt = 1;
genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock;
genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz;
genfeat->rsvd10 = 0x4;
genfeat->legacy_monitor_detect = 1;
genfeat->int_crt_support = 1;
genfeat->dp_ssc_enb = 1;
ptr += sizeof (*genfeat);
bdb_head->bdb_size = ptr - (u8 *)bdb_head;
head->vbt_size = ptr - (u8 *)head;
head->vbt_checksum = 0;
return ptr - (u8 *)head;
}
#endif #endif
static void gma_func0_init(struct device *dev) static void gma_func0_init(struct device *dev)
@ -542,34 +469,7 @@ static void gma_func0_init(struct device *dev)
} }
/* Linux relies on VBT for panel info. */ /* Linux relies on VBT for panel info. */
if (read16(PCI_VGA_RAM_IMAGE_START) != PCI_ROM_HDR) { generate_fake_intel_oprom(&conf->gfx, dev, "$VBT IRONLAKE-MOBILE");
optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START;
optionrom_pcir_t *pcir;
size_t vbt_size;
size_t fake_oprom_size;
memset(oh, 0, 8192);
oh->signature = PCI_ROM_HDR;
oh->pcir_offset = 0x40;
oh->vbt_offset = 0x80;
pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40);
pcir->signature = 0x52494350; // PCIR
pcir->vendor = dev->vendor;
pcir->device = dev->device;
pcir->length = sizeof(*pcir);
pcir->revision = dev->class;
pcir->classcode[0] = dev->class >> 8;
pcir->classcode[1] = dev->class >> 16;
pcir->classcode[2] = dev->class >> 24;
pcir->indicator = 0x80;
vbt_size = generate_vbt (conf, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80));
fake_oprom_size = (0x80 + vbt_size + 511) / 512;
oh->size = fake_oprom_size;
pcir->imagelength = fake_oprom_size;
}
#endif #endif
/* Post VBIOS init */ /* Post VBIOS init */

1
src/northbridge/intel/nehalem/acpi.c
View File

@ -31,6 +31,7 @@
#include <device/device.h> #include <device/device.h>
#include <device/pci.h> #include <device/pci.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include <drivers/intel/gma/intel_bios.h>
#include <build.h> #include <build.h>
#include <arch/acpigen.h> #include <arch/acpigen.h>
#include <cpu/cpu.h> #include <cpu/cpu.h>

7
src/northbridge/intel/nehalem/chip.h
View File

@ -17,6 +17,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#include <drivers/intel/gma/i915.h>
/* /*
* Digital Port Hotplug Enable: * Digital Port Hotplug Enable:
* 0x04 = Enabled, 2ms short pulse * 0x04 = Enabled, 2ms short pulse
@ -39,8 +41,5 @@ struct northbridge_intel_nehalem_config {
u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ u32 gpu_cpu_backlight; /* CPU Backlight PWM value */
u32 gpu_pch_backlight; /* PCH Backlight PWM value */ u32 gpu_pch_backlight; /* PCH Backlight PWM value */
int gpu_use_spread_spectrum_clock; struct i915_gpu_controller_info gfx;
int gpu_lvds_dual_channel;
int gpu_link_frequency_270_mhz;
int gpu_lvds_num_lanes;
}; };

102
src/northbridge/intel/nehalem/gma.c
View File

@ -654,7 +654,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
u32 pixel_n = 1; u32 pixel_n = 1;
u32 pixel_m1 = 1; u32 pixel_m1 = 1;
u32 pixel_m2 = 1; u32 pixel_m2 = 1;
u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000; u32 link_frequency = info->gfx.link_frequency_270_mhz ? 270000 : 162000;
u32 data_m1; u32 data_m1;
u32 data_n1 = 0x00800000; u32 data_n1 = 0x00800000;
u32 link_m1; u32 link_m1;
@ -719,7 +719,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
hfront_porch = edid.hso; hfront_porch = edid.hso;
vfront_porch = edid.vso; vfront_porch = edid.vso;
target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock target_frequency = info->gfx.lvds_dual_channel ? edid.pixel_clock
: (2 * edid.pixel_clock); : (2 * edid.pixel_clock);
#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
vga_textmode_init(); vga_textmode_init();
@ -790,7 +790,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency;
data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock)
/ (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 4)); / (link_frequency * 8 * (info->gfx.lvds_num_lanes ? : 4));
printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
hactive, vactive); hactive, vactive);
@ -802,10 +802,10 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
hsync, vsync); hsync, vsync);
printk(BIOS_DEBUG, "Front porch %d x %d\n", printk(BIOS_DEBUG, "Front porch %d x %d\n",
hfront_porch, vfront_porch); hfront_porch, vfront_porch);
printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock printk(BIOS_DEBUG, (info->gfx.use_spread_spectrum_clock
? "Spread spectrum clock\n" : "DREF clock\n")); ? "Spread spectrum clock\n" : "DREF clock\n"));
printk(BIOS_DEBUG, printk(BIOS_DEBUG,
info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); info->gfx.lvds_dual_channel ? "Dual channel\n" : "Single channel\n");
printk(BIOS_DEBUG, "Polarities %d, %d\n", printk(BIOS_DEBUG, "Polarities %d, %d\n",
hpolarity, vpolarity); hpolarity, vpolarity);
printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n",
@ -822,12 +822,12 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
write32(mmio + PCH_LVDS, write32(mmio + PCH_LVDS,
(hpolarity << 20) | (vpolarity << 21) (hpolarity << 20) | (vpolarity << 21)
| (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
| LVDS_DETECTED); | LVDS_DETECTED);
write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31)); write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31));
write32(mmio + PCH_DREF_CONTROL, (info->gpu_use_spread_spectrum_clock write32(mmio + PCH_DREF_CONTROL, (info->gfx.use_spread_spectrum_clock
? 0x1002 : 0x400)); ? 0x1002 : 0x400));
mdelay(1); mdelay(1);
write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
@ -837,18 +837,18 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
| ((pixel_m1 - 2) << 8) | pixel_m2); | ((pixel_m1 - 2) << 8) | pixel_m2);
write32(mmio + _PCH_DPLL(0), write32(mmio + _PCH_DPLL(0),
DPLL_VCO_ENABLE | DPLLB_MODE_LVDS DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
| (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
: DPLLB_LVDS_P2_CLOCK_DIV_14) : DPLLB_LVDS_P2_CLOCK_DIV_14)
| (0x10000 << (pixel_p1 - 1)) | (0x10000 << (pixel_p1 - 1))
| ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
| (0x1 << (pixel_p1 - 1))); | (0x1 << (pixel_p1 - 1)));
mdelay(1); mdelay(1);
write32(mmio + _PCH_DPLL(0), write32(mmio + _PCH_DPLL(0),
DPLL_VCO_ENABLE | DPLLB_MODE_LVDS DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
| (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 | (info->gfx.lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
: DPLLB_LVDS_P2_CLOCK_DIV_14) : DPLLB_LVDS_P2_CLOCK_DIV_14)
| (0x10000 << (pixel_p1 - 1)) | (0x10000 << (pixel_p1 - 1))
| ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) | ((info->gfx.use_spread_spectrum_clock ? 3 : 0) << 13)
| (0x1 << (pixel_p1 - 1))); | (0x1 << (pixel_p1 - 1)));
/* Re-lock the registers. */ /* Re-lock the registers. */
write32(mmio + PCH_PP_CONTROL, write32(mmio + PCH_PP_CONTROL,
@ -856,7 +856,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
write32(mmio + PCH_LVDS, write32(mmio + PCH_LVDS,
(hpolarity << 20) | (vpolarity << 21) (hpolarity << 20) | (vpolarity << 21)
| (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
| LVDS_DETECTED); | LVDS_DETECTED);
@ -953,7 +953,7 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
write32(mmio + PCH_LVDS, write32(mmio + PCH_LVDS,
LVDS_PORT_ENABLE LVDS_PORT_ENABLE
| (hpolarity << 20) | (vpolarity << 21) | (hpolarity << 20) | (vpolarity << 21)
| (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | (info->gfx.lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
| LVDS_DETECTED); | LVDS_DETECTED);
@ -988,53 +988,6 @@ static void intel_gma_init(const struct northbridge_intel_nehalem_config *info,
#endif #endif
} }
static size_t generate_vbt(const struct northbridge_intel_nehalem_config *conf,
void *vbt)
{
struct vbt_header *head = vbt;
struct bdb_header *bdb_head;
struct bdb_general_features *genfeat;
u8 *ptr;
memset(head, 0, sizeof (*head));
memcpy (head->signature, "$VBT IRONLAKE-MOBILE", 20);
head->version = 100;
head->header_size = sizeof (*head);
head->bdb_offset = sizeof (*head);
bdb_head = (struct bdb_header *) (head + 1);
memset(bdb_head, 0, sizeof (*bdb_head));
memcpy(bdb_head->signature, "BIOS_DATA_BLOCK ", 16);
bdb_head->version = 0xa8;
bdb_head->header_size = sizeof (*bdb_head);
ptr = (u8 *) (bdb_head + 1);
ptr[0] = BDB_GENERAL_FEATURES;
ptr[1] = sizeof (*genfeat);
ptr[2] = sizeof (*genfeat) >> 8;
ptr += 3;
genfeat = (struct bdb_general_features *) ptr;
memset(genfeat, 0, sizeof (*genfeat));
genfeat->panel_fitting = 3;
genfeat->flexaim = 1;
genfeat->download_ext_vbt = 1;
genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock;
genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz;
genfeat->rsvd10 = 0x4;
genfeat->legacy_monitor_detect = 1;
genfeat->int_crt_support = 1;
genfeat->dp_ssc_enb = 1;
ptr += sizeof (*genfeat);
bdb_head->bdb_size = ptr - (u8 *)bdb_head;
head->vbt_size = ptr - (u8 *)head;
head->vbt_checksum = 0;
return ptr - (u8 *)head;
}
#endif #endif
static void gma_func0_init(struct device *dev) static void gma_func0_init(struct device *dev)
@ -1072,34 +1025,7 @@ static void gma_func0_init(struct device *dev)
} }
/* Linux relies on VBT for panel info. */ /* Linux relies on VBT for panel info. */
if (read16(PCI_VGA_RAM_IMAGE_START) != OPROM_SIGNATURE) { generate_fake_intel_oprom(&conf->gfx, dev, "$VBT IRONLAKE-MOBILE");
optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START;
optionrom_pcir_t *pcir;
size_t vbt_size;
size_t fake_oprom_size;
memset(oh, 0, 8192);
oh->signature = OPROM_SIGNATURE;
oh->pcir_offset = 0x40;
oh->vbt_offset = 0x80;
pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40);
pcir->signature = 0x52494350; // PCIR
pcir->vendor = dev->vendor;
pcir->device = dev->device;
pcir->length = sizeof(*pcir);
pcir->revision = dev->class;
pcir->classcode[0] = dev->class >> 8;
pcir->classcode[1] = dev->class >> 16;
pcir->classcode[2] = dev->class >> 24;
pcir->indicator = 0x80;
vbt_size = generate_vbt (conf, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80));
fake_oprom_size = (0x80 + vbt_size + 511) / 512;
oh->size = fake_oprom_size;
pcir->imagelength = fake_oprom_size;
}
#endif #endif

52
src/northbridge/intel/nehalem/gma.h
View File

@ -118,56 +118,4 @@ typedef struct {
opregion_vbt_t vbt; opregion_vbt_t vbt;
} __attribute__((packed)) igd_opregion_t; } __attribute__((packed)) igd_opregion_t;
/* Intel Video BIOS (Option ROM) */
typedef struct {
u16 signature;
u8 size;
u8 reserved[21];
u16 pcir_offset;
u16 vbt_offset;
} __attribute__((packed)) optionrom_header_t;
#define OPROM_SIGNATURE 0xaa55
typedef struct {
u32 signature;
u16 vendor;
u16 device;
u16 reserved1;
u16 length;
u8 revision;
u8 classcode[3];
u16 imagelength;
u16 coderevision;
u8 codetype;
u8 indicator;
u16 reserved2;
} __attribute__((packed)) optionrom_pcir_t;
typedef struct {
u8 hdr_signature[20];
u16 hdr_version;
u16 hdr_size;
u16 hdr_vbt_size;
u8 hdr_vbt_checksum;
u8 hdr_reserved;
u32 hdr_vbt_datablock;
u32 hdr_aim[4];
u8 datahdr_signature[16];
u16 datahdr_version;
u16 datahdr_size;
u16 datahdr_datablocksize;
u8 coreblock_id;
u16 coreblock_size;
u16 coreblock_biossize;
u8 coreblock_biostype;
u8 coreblock_releasestatus;
u8 coreblock_hwsupported;
u8 coreblock_integratedhw;
u8 coreblock_biosbuild[4];
u8 coreblock_biossignon[155];
} __attribute__((packed)) optionrom_vbt_t;
#define VBT_SIGNATURE 0x54425624
#endif #endif

1
src/northbridge/intel/sandybridge/acpi.c
View File

@ -33,6 +33,7 @@
#include <arch/acpigen.h> #include <arch/acpigen.h>
#include "sandybridge.h" #include "sandybridge.h"
#include <cbmem.h> #include <cbmem.h>
#include <drivers/intel/gma/intel_bios.h>
unsigned long acpi_fill_mcfg(unsigned long current) unsigned long acpi_fill_mcfg(unsigned long current)
{ {

7
src/northbridge/intel/sandybridge/chip.h
View File

@ -17,6 +17,8 @@
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
*/ */
#include <drivers/intel/gma/i915.h>
/* /*
* Digital Port Hotplug Enable: * Digital Port Hotplug Enable:
* 0x04 = Enabled, 2ms short pulse * 0x04 = Enabled, 2ms short pulse
@ -39,8 +41,5 @@ struct northbridge_intel_sandybridge_config {
u32 gpu_cpu_backlight; /* CPU Backlight PWM value */ u32 gpu_cpu_backlight; /* CPU Backlight PWM value */
u32 gpu_pch_backlight; /* PCH Backlight PWM value */ u32 gpu_pch_backlight; /* PCH Backlight PWM value */
int gpu_use_spread_spectrum_clock; struct i915_gpu_controller_info gfx;
int gpu_lvds_dual_channel;
int gpu_link_frequency_270_mhz;
int gpu_lvds_num_lanes;
}; };

8
src/northbridge/intel/sandybridge/gma.c
View File

@ -278,12 +278,12 @@ u32 map_oprom_vendev(u32 vendev)
static struct resource *gtt_res = NULL; static struct resource *gtt_res = NULL;
static inline u32 gtt_read(u32 reg) u32 gtt_read(u32 reg)
{ {
return read32(gtt_res->base + reg); return read32(gtt_res->base + reg);
} }
static inline void gtt_write(u32 reg, u32 data) void gtt_write(u32 reg, u32 data)
{ {
write32(gtt_res->base + reg, data); write32(gtt_res->base + reg, data);
} }
@ -295,7 +295,7 @@ static inline void gtt_write_powermeter(const struct gt_powermeter *pm)
} }
#define GTT_RETRY 1000 #define GTT_RETRY 1000
static int gtt_poll(u32 reg, u32 mask, u32 value) int gtt_poll(u32 reg, u32 mask, u32 value)
{ {
unsigned try = GTT_RETRY; unsigned try = GTT_RETRY;
u32 data; u32 data;
@ -595,7 +595,7 @@ static void gma_func0_init(struct device *dev)
physbase = pci_read_config32(dev, 0x5c) & ~0xf; physbase = pci_read_config32(dev, 0x5c) & ~0xf;
graphics_base = dev->resource_list[1].base; graphics_base = dev->resource_list[1].base;
int lightup_ok = i915lightup_sandy(conf, physbase, iobase, mmiobase, graphics_base); int lightup_ok = i915lightup_sandy(&conf->gfx, physbase, iobase, mmiobase, graphics_base);
if (lightup_ok) if (lightup_ok)
gfx_set_init_done(1); gfx_set_init_done(1);
#endif #endif

56
src/northbridge/intel/sandybridge/gma.h
View File

@ -114,59 +114,7 @@ typedef struct {
opregion_vbt_t vbt; opregion_vbt_t vbt;
} __attribute__((packed)) igd_opregion_t; } __attribute__((packed)) igd_opregion_t;
/* Intel Video BIOS (Option ROM) */ struct i915_gpu_controller_info;
typedef struct {
u16 signature;
u8 size;
u8 reserved[21];
u16 pcir_offset;
u16 vbt_offset;
} __attribute__((packed)) optionrom_header_t;
#define OPROM_SIGNATURE 0xaa55 int i915lightup_sandy(const struct i915_gpu_controller_info *info,
typedef struct {
u32 signature;
u16 vendor;
u16 device;
u16 reserved1;
u16 length;
u8 revision;
u8 classcode[3];
u16 imagelength;
u16 coderevision;
u8 codetype;
u8 indicator;
u16 reserved2;
} __attribute__((packed)) optionrom_pcir_t;
typedef struct {
u8 hdr_signature[20];
u16 hdr_version;
u16 hdr_size;
u16 hdr_vbt_size;
u8 hdr_vbt_checksum;
u8 hdr_reserved;
u32 hdr_vbt_datablock;
u32 hdr_aim[4];
u8 datahdr_signature[16];
u16 datahdr_version;
u16 datahdr_size;
u16 datahdr_datablocksize;
u8 coreblock_id;
u16 coreblock_size;
u16 coreblock_biossize;
u8 coreblock_biostype;
u8 coreblock_releasestatus;
u8 coreblock_hwsupported;
u8 coreblock_integratedhw;
u8 coreblock_biosbuild[4];
u8 coreblock_biossignon[155];
} __attribute__((packed)) optionrom_vbt_t;
#define VBT_SIGNATURE 0x54425624
struct northbridge_intel_sandybridge_config;
int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info,
u32 physbase, u16 pio, u32 mmio, u32 lfb); u32 physbase, u16 pio, u32 mmio, u32 lfb);

106
src/northbridge/intel/sandybridge/gma_ivybridge_lvds.c
View File

@ -36,54 +36,6 @@
#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) #if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
static size_t generate_vbt(const struct northbridge_intel_sandybridge_config *conf,
void *vbt)
{
struct vbt_header *head = vbt;
struct bdb_header *bdb_head;
struct bdb_general_features *genfeat;
u8 *ptr;
memset(head, 0, sizeof (*head));
memcpy(head->signature, "$VBT SNB/IVB-MOBILE ", 20);
head->version = 100;
head->header_size = sizeof (*head);
head->bdb_offset = sizeof (*head);
bdb_head = (struct bdb_header *) (head + 1);
memset(bdb_head, 0, sizeof (*bdb_head));
memcpy(bdb_head->signature, "BIOS_DATA_BLOCK ", 16);
bdb_head->version = 0xa8;
bdb_head->header_size = sizeof (*bdb_head);
ptr = (u8 *) (bdb_head + 1);
ptr[0] = BDB_GENERAL_FEATURES;
ptr[1] = sizeof (*genfeat);
ptr[2] = sizeof (*genfeat) >> 8;
ptr += 3;
genfeat = (struct bdb_general_features *) ptr;
memset(genfeat, 0, sizeof (*genfeat));
genfeat->panel_fitting = 3;
genfeat->flexaim = 1;
genfeat->download_ext_vbt = 1;
genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock;
genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz;
genfeat->rsvd10 = 0x4;
genfeat->legacy_monitor_detect = 1;
genfeat->int_crt_support = 1;
genfeat->dp_ssc_enb = 1;
ptr += sizeof (*genfeat);
bdb_head->bdb_size = ptr - (u8 *)bdb_head;
head->vbt_size = ptr - (u8 *)head;
head->vbt_checksum = 0;
return ptr - (u8 *)head;
}
static void link_train(u32 mmio) static void link_train(u32 mmio)
{ {
write32(mmio+0xf000c,0x40); write32(mmio+0xf000c,0x40);
@ -207,7 +159,7 @@ static void enable_port(u32 mmio)
read32(mmio + 0xc4000); read32(mmio + 0xc4000);
} }
int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, int i915lightup_sandy(const struct i915_gpu_controller_info *info,
u32 physbase, u16 piobase, u32 mmio, u32 lfb) u32 physbase, u16 piobase, u32 mmio, u32 lfb)
{ {
int i; int i;
@ -277,7 +229,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info,
u32 candp1, candn; u32 candp1, candn;
u32 best_delta = 0xffffffff; u32 best_delta = 0xffffffff;
u32 target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock u32 target_frequency = info->lvds_dual_channel ? edid.pixel_clock
: (2 * edid.pixel_clock); : (2 * edid.pixel_clock);
u32 pixel_p1 = 1; u32 pixel_p1 = 1;
u32 pixel_n = 1; u32 pixel_n = 1;
@ -350,7 +302,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info,
return 0; return 0;
} }
u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000; u32 link_frequency = info->link_frequency_270_mhz ? 270000 : 162000;
u32 data_m1; u32 data_m1;
u32 data_n1 = 0x00800000; u32 data_n1 = 0x00800000;
u32 link_m1; u32 link_m1;
@ -359,7 +311,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info,
link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency;
data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock)
/ (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 1)); / (link_frequency * 8 * (info->lvds_num_lanes ? : 1));
printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
hactive, vactive); hactive, vactive);
@ -371,10 +323,10 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info,
hsync, vsync); hsync, vsync);
printk(BIOS_DEBUG, "Front porch %d x %d\n", printk(BIOS_DEBUG, "Front porch %d x %d\n",
hfront_porch, vfront_porch); hfront_porch, vfront_porch);
printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock printk(BIOS_DEBUG, (info->use_spread_spectrum_clock
? "Spread spectrum clock\n" : "DREF clock\n")); ? "Spread spectrum clock\n" : "DREF clock\n"));
printk(BIOS_DEBUG, printk(BIOS_DEBUG,
info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); info->lvds_dual_channel ? "Dual channel\n" : "Single channel\n");
printk(BIOS_DEBUG, "Polarities %d, %d\n", printk(BIOS_DEBUG, "Polarities %d, %d\n",
hpolarity, vpolarity); hpolarity, vpolarity);
printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n",
@ -391,12 +343,12 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info,
write32(mmio + PCH_LVDS, write32(mmio + PCH_LVDS,
(hpolarity << 20) | (vpolarity << 21) (hpolarity << 20) | (vpolarity << 21)
| (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
| LVDS_DETECTED); | LVDS_DETECTED);
write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31)); write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31));
write32(mmio + PCH_DREF_CONTROL, (info->gpu_use_spread_spectrum_clock write32(mmio + PCH_DREF_CONTROL, (info->use_spread_spectrum_clock
? 0x1002 : 0x400)); ? 0x1002 : 0x400));
mdelay(1); mdelay(1);
write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
@ -406,10 +358,10 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info,
| ((pixel_m1 - 2) << 8) | pixel_m2); | ((pixel_m1 - 2) << 8) | pixel_m2);
write32(mmio + _PCH_DPLL(0), write32(mmio + _PCH_DPLL(0),
DPLL_VCO_ENABLE | DPLLB_MODE_LVDS DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
| (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
: DPLLB_LVDS_P2_CLOCK_DIV_14) : DPLLB_LVDS_P2_CLOCK_DIV_14)
| (0x10000 << (pixel_p1 - 1)) | (0x10000 << (pixel_p1 - 1))
| ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) | ((info->use_spread_spectrum_clock ? 3 : 0) << 13)
| (0x1 << (pixel_p1 - 1))); | (0x1 << (pixel_p1 - 1)));
mdelay(1); mdelay(1);
@ -418,10 +370,10 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info,
mdelay(1); mdelay(1);
write32(mmio + _PCH_DPLL(0), write32(mmio + _PCH_DPLL(0),
DPLL_VCO_ENABLE | DPLLB_MODE_LVDS DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
| (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
: DPLLB_LVDS_P2_CLOCK_DIV_14) : DPLLB_LVDS_P2_CLOCK_DIV_14)
| (0x10000 << (pixel_p1 - 1)) | (0x10000 << (pixel_p1 - 1))
| ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) | ((info->use_spread_spectrum_clock ? 3 : 0) << 13)
| (0x1 << (pixel_p1 - 1))); | (0x1 << (pixel_p1 - 1)));
/* Re-lock the registers. */ /* Re-lock the registers. */
write32(mmio + PCH_PP_CONTROL, write32(mmio + PCH_PP_CONTROL,
@ -429,7 +381,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info,
write32(mmio + PCH_LVDS, write32(mmio + PCH_LVDS,
(hpolarity << 20) | (vpolarity << 21) (hpolarity << 20) | (vpolarity << 21)
| (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
| LVDS_DETECTED); | LVDS_DETECTED);
@ -526,7 +478,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info,
write32(mmio + PCH_LVDS, write32(mmio + PCH_LVDS,
LVDS_PORT_ENABLE LVDS_PORT_ENABLE
| (hpolarity << 20) | (vpolarity << 21) | (hpolarity << 20) | (vpolarity << 21)
| (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
| LVDS_DETECTED); | LVDS_DETECTED);
@ -562,35 +514,9 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info,
#endif #endif
/* Linux relies on VBT for panel info. */ /* Linux relies on VBT for panel info. */
optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START; generate_fake_intel_oprom(info, dev_find_slot(0, PCI_DEVFN(2, 0)),
optionrom_pcir_t *pcir; "$VBT SNB/IVB-MOBILE ");
size_t vbt_size;
size_t fake_oprom_size;
struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(2, 0));
memset(oh, 0, 8192);
oh->signature = OPROM_SIGNATURE;
oh->pcir_offset = 0x40;
oh->vbt_offset = 0x80;
pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40);
pcir->signature = 0x52494350; // PCIR
pcir->vendor = dev->vendor;
pcir->device = dev->device;
pcir->length = sizeof(*pcir);
pcir->revision = dev->class;
pcir->classcode[0] = dev->class >> 8;
pcir->classcode[1] = dev->class >> 16;
pcir->classcode[2] = dev->class >> 24;
pcir->indicator = 0x80;
vbt_size = generate_vbt (info, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80));
fake_oprom_size = (0x80 + vbt_size + 511) / 512;
oh->size = fake_oprom_size;
pcir->imagelength = fake_oprom_size;
return 1; return 1;
} }

108
src/northbridge/intel/sandybridge/gma_sandybridge_lvds.c
View File

@ -26,7 +26,6 @@
#include <drivers/intel/gma/edid.h> #include <drivers/intel/gma/edid.h>
#include <drivers/intel/gma/i915.h> #include <drivers/intel/gma/i915.h>
#include <drivers/intel/gma/intel_bios.h>
#include "gma.h" #include "gma.h"
#include "chip.h" #include "chip.h"
#include <pc80/vga.h> #include <pc80/vga.h>
@ -36,54 +35,6 @@
#if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT) #if IS_ENABLED(CONFIG_MAINBOARD_DO_NATIVE_VGA_INIT)
static size_t generate_vbt(const struct northbridge_intel_sandybridge_config *conf,
void *vbt)
{
struct vbt_header *head = vbt;
struct bdb_header *bdb_head;
struct bdb_general_features *genfeat;
u8 *ptr;
memset(head, 0, sizeof (*head));
memcpy(head->signature, "$VBT SNB/IVB-MOBILE ", 20);
head->version = 100;
head->header_size = sizeof (*head);
head->bdb_offset = sizeof (*head);
bdb_head = (struct bdb_header *) (head + 1);
memset(bdb_head, 0, sizeof (*bdb_head));
memcpy(bdb_head->signature, "BIOS_DATA_BLOCK ", 16);
bdb_head->version = 0xa8;
bdb_head->header_size = sizeof (*bdb_head);
ptr = (u8 *) (bdb_head + 1);
ptr[0] = BDB_GENERAL_FEATURES;
ptr[1] = sizeof (*genfeat);
ptr[2] = sizeof (*genfeat) >> 8;
ptr += 3;
genfeat = (struct bdb_general_features *) ptr;
memset(genfeat, 0, sizeof (*genfeat));
genfeat->panel_fitting = 3;
genfeat->flexaim = 1;
genfeat->download_ext_vbt = 1;
genfeat->enable_ssc = conf->gpu_use_spread_spectrum_clock;
genfeat->ssc_freq = !conf->gpu_link_frequency_270_mhz;
genfeat->rsvd10 = 0x4;
genfeat->legacy_monitor_detect = 1;
genfeat->int_crt_support = 1;
genfeat->dp_ssc_enb = 1;
ptr += sizeof (*genfeat);
bdb_head->bdb_size = ptr - (u8 *)bdb_head;
head->vbt_size = ptr - (u8 *)head;
head->vbt_checksum = 0;
return ptr - (u8 *)head;
}
static void train_link(u32 mmio) static void train_link(u32 mmio)
{ {
/* Clear interrupts. */ /* Clear interrupts. */
@ -171,7 +122,7 @@ static void power_port(u32 mmio)
read32(mmio + 0x000e1180); // = 0x40000002 read32(mmio + 0x000e1180); // = 0x40000002
} }
int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info, int i915lightup_sandy(const struct i915_gpu_controller_info *info,
u32 physbase, u16 piobase, u32 mmio, u32 lfb) u32 physbase, u16 piobase, u32 mmio, u32 lfb)
{ {
int i; int i;
@ -187,7 +138,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info,
u32 pixel_n = 1; u32 pixel_n = 1;
u32 pixel_m1 = 1; u32 pixel_m1 = 1;
u32 pixel_m2 = 1; u32 pixel_m2 = 1;
u32 link_frequency = info->gpu_link_frequency_270_mhz ? 270000 : 162000; u32 link_frequency = info->link_frequency_270_mhz ? 270000 : 162000;
u32 data_m1; u32 data_m1;
u32 data_n1 = 0x00800000; u32 data_n1 = 0x00800000;
u32 link_m1; u32 link_m1;
@ -252,7 +203,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info,
hfront_porch = edid.hso; hfront_porch = edid.hso;
vfront_porch = edid.vso; vfront_porch = edid.vso;
target_frequency = info->gpu_lvds_dual_channel ? edid.pixel_clock target_frequency = info->lvds_dual_channel ? edid.pixel_clock
: (2 * edid.pixel_clock); : (2 * edid.pixel_clock);
#if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE) #if !IS_ENABLED(CONFIG_FRAMEBUFFER_KEEP_VESA_MODE)
vga_textmode_init(); vga_textmode_init();
@ -323,7 +274,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info,
link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency; link_m1 = ((uint64_t)link_n1 * edid.pixel_clock) / link_frequency;
data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock) data_m1 = ((uint64_t)data_n1 * 18 * edid.pixel_clock)
/ (link_frequency * 8 * (info->gpu_lvds_num_lanes ? : 4)); / (link_frequency * 8 * (info->lvds_num_lanes ? : 4));
printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n", printk(BIOS_INFO, "bringing up panel at resolution %d x %d\n",
hactive, vactive); hactive, vactive);
@ -335,10 +286,10 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info,
hsync, vsync); hsync, vsync);
printk(BIOS_DEBUG, "Front porch %d x %d\n", printk(BIOS_DEBUG, "Front porch %d x %d\n",
hfront_porch, vfront_porch); hfront_porch, vfront_porch);
printk(BIOS_DEBUG, (info->gpu_use_spread_spectrum_clock printk(BIOS_DEBUG, (info->use_spread_spectrum_clock
? "Spread spectrum clock\n" : "DREF clock\n")); ? "Spread spectrum clock\n" : "DREF clock\n"));
printk(BIOS_DEBUG, printk(BIOS_DEBUG,
info->gpu_lvds_dual_channel ? "Dual channel\n" : "Single channel\n"); info->lvds_dual_channel ? "Dual channel\n" : "Single channel\n");
printk(BIOS_DEBUG, "Polarities %d, %d\n", printk(BIOS_DEBUG, "Polarities %d, %d\n",
hpolarity, vpolarity); hpolarity, vpolarity);
printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n", printk(BIOS_DEBUG, "Data M1=%d, N1=%d\n",
@ -355,12 +306,12 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info,
write32(mmio + PCH_LVDS, write32(mmio + PCH_LVDS,
(hpolarity << 20) | (vpolarity << 21) (hpolarity << 20) | (vpolarity << 21)
| (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
| LVDS_DETECTED); | LVDS_DETECTED);
write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31)); write32(mmio + BLC_PWM_CPU_CTL2, (1 << 31));
write32(mmio + PCH_DREF_CONTROL, (info->gpu_use_spread_spectrum_clock write32(mmio + PCH_DREF_CONTROL, (info->use_spread_spectrum_clock
? 0x1002 : 0x400)); ? 0x1002 : 0x400));
mdelay(1); mdelay(1);
write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS write32(mmio + PCH_PP_CONTROL, PANEL_UNLOCK_REGS
@ -371,18 +322,18 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info,
write32(mmio + PCH_DPLL_SEL, 8); write32(mmio + PCH_DPLL_SEL, 8);
write32(mmio + _PCH_DPLL(0), write32(mmio + _PCH_DPLL(0),
DPLL_VCO_ENABLE | DPLLB_MODE_LVDS DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
| (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
: DPLLB_LVDS_P2_CLOCK_DIV_14) : DPLLB_LVDS_P2_CLOCK_DIV_14)
| (0x10000 << (pixel_p1 - 1)) | (0x10000 << (pixel_p1 - 1))
| ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) | ((info->use_spread_spectrum_clock ? 3 : 0) << 13)
| (0x1 << (pixel_p1 - 1))); | (0x1 << (pixel_p1 - 1)));
mdelay(1); mdelay(1);
write32(mmio + _PCH_DPLL(0), write32(mmio + _PCH_DPLL(0),
DPLL_VCO_ENABLE | DPLLB_MODE_LVDS DPLL_VCO_ENABLE | DPLLB_MODE_LVDS
| (info->gpu_lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7 | (info->lvds_dual_channel ? DPLLB_LVDS_P2_CLOCK_DIV_7
: DPLLB_LVDS_P2_CLOCK_DIV_14) : DPLLB_LVDS_P2_CLOCK_DIV_14)
| (0x10000 << (pixel_p1 - 1)) | (0x10000 << (pixel_p1 - 1))
| ((info->gpu_use_spread_spectrum_clock ? 3 : 0) << 13) | ((info->use_spread_spectrum_clock ? 3 : 0) << 13)
| (0x1 << (pixel_p1 - 1))); | (0x1 << (pixel_p1 - 1)));
/* Re-lock the registers. */ /* Re-lock the registers. */
write32(mmio + PCH_PP_CONTROL, write32(mmio + PCH_PP_CONTROL,
@ -390,7 +341,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info,
write32(mmio + PCH_LVDS, write32(mmio + PCH_LVDS,
(hpolarity << 20) | (vpolarity << 21) (hpolarity << 20) | (vpolarity << 21)
| (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
| LVDS_DETECTED); | LVDS_DETECTED);
@ -487,7 +438,7 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info,
write32(mmio + PCH_LVDS, write32(mmio + PCH_LVDS,
LVDS_PORT_ENABLE LVDS_PORT_ENABLE
| (hpolarity << 20) | (vpolarity << 21) | (hpolarity << 20) | (vpolarity << 21)
| (info->gpu_lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL | (info->lvds_dual_channel ? LVDS_CLOCK_B_POWERUP_ALL
| LVDS_CLOCK_BOTH_POWERUP_ALL : 0) | LVDS_CLOCK_BOTH_POWERUP_ALL : 0)
| LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL | LVDS_BORDER_ENABLE | LVDS_CLOCK_A_POWERUP_ALL
| LVDS_DETECTED); | LVDS_DETECTED);
@ -522,35 +473,8 @@ int i915lightup_sandy(const struct northbridge_intel_sandybridge_config *info,
#endif #endif
/* Linux relies on VBT for panel info. */ /* Linux relies on VBT for panel info. */
optionrom_header_t *oh = (void *)PCI_VGA_RAM_IMAGE_START; generate_fake_intel_oprom(info, dev_find_slot(0, PCI_DEVFN(2, 0)),
optionrom_pcir_t *pcir; "$VBT SNB/IVB-MOBILE ");
size_t vbt_size;
size_t fake_oprom_size;
struct device *dev;
dev = dev_find_slot(0, PCI_DEVFN(2, 0));
memset(oh, 0, 8192);
oh->signature = OPROM_SIGNATURE;
oh->pcir_offset = 0x40;
oh->vbt_offset = 0x80;
pcir = (void *)(PCI_VGA_RAM_IMAGE_START + 0x40);
pcir->signature = 0x52494350; // PCIR
pcir->vendor = dev->vendor;
pcir->device = dev->device;
pcir->length = sizeof(*pcir);
pcir->revision = dev->class;
pcir->classcode[0] = dev->class >> 8;
pcir->classcode[1] = dev->class >> 16;
pcir->classcode[2] = dev->class >> 24;
pcir->indicator = 0x80;
vbt_size = generate_vbt (info, (void *)(PCI_VGA_RAM_IMAGE_START + 0x80));
fake_oprom_size = (0x80 + vbt_size + 511) / 512;
oh->size = fake_oprom_size;
pcir->imagelength = fake_oprom_size;
return 1; return 1;
} }