mb/system76/adl-p: Add Oryx Pro 9 as a variant
Change-Id: I2018d5e75ffbcf78a94cca58bcfd6b5e41ac9864 Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
committed by
Tim Crawford
Tim Crawford
parent
a986888a74
commit
a7a7428a76
@ -1,14 +1,17 @@
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if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_LEMP11
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if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_LEMP11 || BOARD_SYSTEM76_ORYP9
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select BOARD_ROMSIZE_KB_32768
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select DRIVERS_GFX_NVIDIA if BOARD_SYSTEM76_ORYP9
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select DRIVERS_I2C_HID
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select DRIVERS_INTEL_PMC
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select DRIVERS_INTEL_USB4_RETIMER
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select DRIVERS_I2C_TAS5825M if BOARD_SYSTEM76_ORYP9
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select EC_SYSTEM76_EC
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select EC_SYSTEM76_EC_BAT_THRESHOLDS
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select EC_SYSTEM76_EC_COLOR_KEYBOARD if BOARD_SYSTEM76_DARP8
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select EC_SYSTEM76_EC_COLOR_KEYBOARD if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_ORYP9
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select EC_SYSTEM76_EC_DGPU if BOARD_SYSTEM76_ORYP9
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select HAVE_ACPI_TABLES
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select HAVE_CMOS_DEFAULT
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select HAVE_OPTION_TABLE
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@ -32,6 +35,7 @@ config MAINBOARD_DIR
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config VARIANT_DIR
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default "darp8" if BOARD_SYSTEM76_DARP8
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default "lemp11" if BOARD_SYSTEM76_LEMP11
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default "oryp9" if BOARD_SYSTEM76_ORYP9
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config OVERRIDE_DEVICETREE
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default "variants/\$(CONFIG_VARIANT_DIR)/overridetree.cb"
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@ -39,14 +43,17 @@ config OVERRIDE_DEVICETREE
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config MAINBOARD_PART_NUMBER
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default "darp8" if BOARD_SYSTEM76_DARP8
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default "lemp11" if BOARD_SYSTEM76_LEMP11
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default "oryp9" if BOARD_SYSTEM76_ORYP9
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config MAINBOARD_SMBIOS_PRODUCT_NAME
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default "Darter Pro" if BOARD_SYSTEM76_DARP8
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default "Lemur Pro" if BOARD_SYSTEM76_LEMP11
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default "Oryx Pro" if BOARD_SYSTEM76_ORYP9
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config MAINBOARD_VERSION
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default "darp8" if BOARD_SYSTEM76_DARP8
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default "lemp11" if BOARD_SYSTEM76_LEMP11
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default "oryp9" if BOARD_SYSTEM76_ORYP9
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config CBFS_SIZE
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default 0xA00000
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@ -57,6 +64,9 @@ config CONSOLE_POST
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config DIMM_SPD_SIZE
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default 512
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config ONBOARD_VGA_IS_PRIMARY
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default y
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config POST_DEVICE
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default n
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@ -3,3 +3,6 @@ config BOARD_SYSTEM76_DARP8
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config BOARD_SYSTEM76_LEMP11
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bool "lemp11"
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config BOARD_SYSTEM76_ORYP9
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bool "oryp9"
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@ -1,4 +1,5 @@
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
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CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
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bootblock-y += bootblock.c
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bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c
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@ -8,5 +9,6 @@ romstage-y += variants/$(VARIANT_DIR)/romstage.c
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ramstage-y += ramstage.c
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ramstage-y += variants/$(VARIANT_DIR)/hda_verb.c
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ramstage-y += variants/$(VARIANT_DIR)/gpio.c
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ramstage-$(CONFIG_DRIVERS_I2C_TAS5825M) += variants/$(VARIANT_DIR)/tas5825m.c
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SPD_SOURCES = samsung-P4AAF165WA-BCWDE
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@ -1,5 +1,9 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#if CONFIG(DRIVERS_GFX_NVIDIA)
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#include <variant/gpio.h>
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#endif
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#define EC_GPE_SCI 0x6E
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#define EC_GPE_SWI 0x6B
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#include <ec/system76/ec/acpi/ec.asl>
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@ -8,6 +12,11 @@ Scope (\_SB) {
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#include "sleep.asl"
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Scope (PCI0) {
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#include "backlight.asl"
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#if CONFIG(DRIVERS_GFX_NVIDIA)
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Scope (PEG2) {
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#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
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}
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#endif
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}
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}
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@ -0,0 +1,2 @@
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Board name: oryp9
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Release year: 2022
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BIN
src/mainboard/system76/adl-p/variants/oryp9/data.vbt
Normal file
BIN
src/mainboard/system76/adl-p/variants/oryp9/data.vbt
Normal file
Binary file not shown.
227
src/mainboard/system76/adl-p/variants/oryp9/gpio.c
Normal file
227
src/mainboard/system76/adl-p/variants/oryp9/gpio.c
Normal file
@ -0,0 +1,227 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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#include <mainboard/gpio.h>
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#include <soc/gpio.h>
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static const struct pad_config gpio_table[] = {
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/* ------- GPIO Group GPD ------- */
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PAD_CFG_NF(GPD0, UP_20K, PWROK, NF1), // PM_BATLOW#
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PAD_CFG_NF(GPD1, NATIVE, PWROK, NF1), // AC_PRESENT
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PAD_NC(GPD2, NONE),
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PAD_CFG_NF(GPD3, UP_20K, PWROK, NF1), // PWN_BTN#
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PAD_CFG_NF(GPD4, NONE, PWROK, NF1), // SUSB#_PCH
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PAD_CFG_NF(GPD5, NONE, PWROK, NF1), // SUSC#_PCH
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PAD_CFG_NF(GPD6, NONE, PWROK, NF1), // SLP_A#
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PAD_NC(GPD7, NONE),
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PAD_CFG_NF(GPD8, NONE, PWROK, NF1), // SUS_CLK
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PAD_CFG_GPO(GPD9, 0, PWROK), // SLP_WLAN#
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PAD_CFG_NF(GPD10, NONE, PWROK, NF1), // SLP_S5#
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PAD_NC(GPD11, NONE),
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/* ------- GPIO Group GPP_A ------- */
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PAD_CFG_NF(GPP_A0, UP_20K, DEEP, NF1), // ESPI_IO0_EC
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PAD_CFG_NF(GPP_A1, UP_20K, DEEP, NF1), // ESPI_IO1_EC
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PAD_CFG_NF(GPP_A2, UP_20K, DEEP, NF1), // ESPI_IO2_EC
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PAD_CFG_NF(GPP_A3, UP_20K, DEEP, NF1), // ESPI_IO3_EC
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PAD_CFG_NF(GPP_A4, UP_20K, DEEP, NF1), // ESPI_CS_EC#
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PAD_CFG_NF(GPP_A5, UP_20K, DEEP, NF1), // ESPI_ALRT0#
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_PAD_CFG_STRUCT(GPP_A6, 0x80100100, 0x0000), // INTP_8851
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PAD_CFG_GPI(GPP_A7, NONE, PLTRST), // GC6_FB_EN_PCH
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PAD_CFG_GPO(GPP_A8, 0, DEEP), // GPIO_LANRTD3
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PAD_CFG_NF(GPP_A9, DN_20K, DEEP, NF1), // ESPI_CLK_EC
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PAD_CFG_NF(GPP_A10, NONE, DEEP, NF1), // ESPI_RESET#
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PAD_NC(GPP_A11, NONE), // GPU_PROCHOT#
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PAD_NC(GPP_A12, NONE),
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PAD_CFG_GPO(GPP_A13, 1, PLTRST), // PCH_BT_EN
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//PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN
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_PAD_CFG_STRUCT(GPP_A15, 0x46880100, 0x0000), // G_DP_HDPD_E
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PAD_NC(GPP_A16, NONE), // USB_OC3#
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PAD_NC(GPP_A17, NONE),
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_PAD_CFG_STRUCT(GPP_A18, 0x46880100, 0x0000), // HDMI_HPD
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PAD_NC(GPP_A19, NONE),
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_PAD_CFG_STRUCT(GPP_A20, 0x46880100, 0x0000), // DP_F_HPD
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PAD_NC(GPP_A21, NONE),
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PAD_CFG_GPO(GPP_A22, 0, DEEP), // PCIE4_WAKE_N
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PAD_CFG_GPI(GPP_A23, UP_20K, DEEP), // GPIO4_NVVDD_EN
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/* ------- GPIO Group GPP_B ------- */
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PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), // VCCIN_AUX_VID0
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PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), // VCCIN_AUX_VID1
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//PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_CPU
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PAD_CFG_GPI(GPP_B3, NONE, DEEP), // SCI#
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PAD_CFG_GPI(GPP_B4, NONE, DEEP), // SWI#
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PAD_CFG_NF(GPP_B5, NONE, DEEP, NF1), // GPPB_I2C2_SDA (Pantone)
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PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), // GPPB_I2C2_SCL (Pantone)
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PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), // I2C3_SDA (IT8851)
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PAD_CFG_NF(GPP_B8, NONE, DEEP, NF1), // I2C3_SCL (IT8851)
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//PAD_NC(GPP_B9, NONE),
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//PAD_NC(GPP_B10, NONE),
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PAD_CFG_NF(GPP_B11, NONE, PWROK, NF1), // TBT_I2C_INT
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PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), // SLP_S0#
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PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1), // PLT_RST#
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PAD_NC(GPP_B14, NONE), // Top swap override
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PAD_CFG_GPI(GPP_B15, NONE, DEEP), // PS8461_SW
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PAD_NC(GPP_B16, NONE),
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PAD_NC(GPP_B17, NONE),
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PAD_CFG_GPI(GPP_B18, NONE, DEEP), // NO REBOOT strap
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//PAD_NC(GPP_B19, NONE),
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//PAD_NC(GPP_B20, NONE),
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//PAD_NC(GPP_B21, NONE),
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//PAD_NC(GPP_B22, NONE),
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PAD_CFG_GPO(GPP_B23, 0, DEEP), // CPUNSSC CLOCK FREQ strap
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/* ------- GPIO Group GPP_C ------- */
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PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), // SMB_CLK
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PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), // SMB_DATA
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PAD_CFG_GPO(GPP_C2, 1, PLTRST), // M2_PWR_EN2
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PAD_CFG_NF(GPP_C3, NONE, DEEP, NF1), // SML0_CLK
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PAD_CFG_NF(GPP_C4, NONE, DEEP, NF1), // SML0_DATA
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PAD_CFG_GPO(GPP_C5, 0, DEEP), // ESPI OR EC LESS strap
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PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), // TBT_I2C_SCL
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PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), // TBT_I2C_SDA
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//PAD_NC(GPP_C8, NONE),
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//PAD_NC(GPP_C9, NONE),
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//PAD_NC(GPP_C10, NONE),
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//PAD_NC(GPP_C11, NONE),
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//PAD_NC(GPP_C12, NONE),
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//PAD_NC(GPP_C13, NONE),
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//PAD_NC(GPP_C14, NONE),
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//PAD_NC(GPP_C15, NONE),
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//PAD_NC(GPP_C16, NONE),
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//PAD_NC(GPP_C17, NONE),
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//PAD_NC(GPP_C18, NONE),
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//PAD_NC(GPP_C19, NONE),
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//PAD_NC(GPP_C20, NONE),
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//PAD_NC(GPP_C21, NONE),
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//PAD_NC(GPP_C22, NONE),
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//PAD_NC(GPP_C23, NONE),
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/* ------- GPIO Group GPP_D ------- */
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PAD_CFG_GPO(GPP_D0, 1, DEEP), // SB_BLON
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PAD_CFG_GPI(GPP_D1, NONE, DEEP), // SB_KBCRST#
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PAD_CFG_GPO(GPP_D2, 0, DEEP), // ROM_I2C_EN
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PAD_NC(GPP_D3, NONE),
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PAD_CFG_GPO(GPP_D4, 1, PLTRST), // GPIO_LAN_EN
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//PAD_CFG_NF(GPP_D5, NONE, DEEP, NF1), // SSD0_CLKREQ#
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PAD_CFG_GPO(GPP_D6, 1, DEEP), // LAN_PLT_RST#
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//PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), // WLAN_CLKREQ#
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//PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1), // GPU_PCIE_CLKREQ#
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PAD_NC(GPP_D9, NONE),
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PAD_NC(GPP_D10, NONE),
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PAD_NC(GPP_D11, NONE),
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PAD_CFG_GPI(GPP_D12, NATIVE, DEEP), // DGPU_PWRGD_R
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PAD_CFG_GPI(GPP_D13, NONE, DEEP), // WLAN_WAKEUP#
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PAD_CFG_GPO(GPP_D14, 1, PLTRST), // M2_PWR_EN1
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PAD_NC(GPP_D15, NONE),
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PAD_NC(GPP_D16, NONE),
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PAD_NC(GPP_D17, NONE),
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PAD_NC(GPP_D18, NONE),
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PAD_CFG_GPO(GPP_D19, 1, PLTRST), // SATA_LED#
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/* ------- GPIO Group GPP_E ------- */
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PAD_CFG_GPI(GPP_E0, NONE, DEEP), // CNVI_WAKE#
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_PAD_CFG_STRUCT(GPP_E1, 0x40100100, 0x3000), // TPM_PIRQ#
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PAD_CFG_GPI(GPP_E2, NONE, DEEP), // BOARD_ID2
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PAD_CFG_GPO(GPP_E3, 1, PLTRST), // PCH_WLAN_EN
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PAD_CFG_GPO(GPP_E4, 0, PLTRST), // TC_RETIMER_FORCE_PWR
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PAD_NC(GPP_E5, NONE),
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PAD_CFG_GPI(GPP_E6, NONE, DEEP), // JTAG ODT DISABLE strap
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PAD_CFG_GPI(GPP_E7, NONE, DEEP), // SMI#
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PAD_CFG_GPI(GPP_E8, NONE, DEEP), // SLP_DRAM#
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PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), // USB_OC0#
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PAD_CFG_GPI(GPP_E10, NONE, DEEP), // BOARD_ID4
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PAD_CFG_GPI(GPP_E11, NONE, DEEP), // BOARD_ID1
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PAD_CFG_GPI_INT(GPP_E12, NONE, PLTRST, LEVEL), // TP_ATTN#
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PAD_CFG_GPI(GPP_E13, NONE, DEEP), // BOARD_ID3
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PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), // EDP_HPD
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PAD_NC(GPP_E15, NONE),
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PAD_NC(GPP_E16, NONE),
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PAD_CFG_GPI(GPP_E17, NONE, DEEP), // BOARD_ID5
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PAD_NC(GPP_E18, NATIVE), // TBTA_LSX2_TXD
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PAD_NC(GPP_E19, NATIVE), // TBTA_LSX2_RXD
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PAD_NC(GPP_E20, NONE),
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PAD_NC(GPP_E21, NONE), // Strap
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PAD_NC(GPP_E22, NONE),
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PAD_NC(GPP_E23, NONE),
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/* ------- GPIO Group GPP_F ------- */
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PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), // CNVI_BRI_DT
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PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), // CNVI_BRI_RSP
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PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), // CNVI_RGI_DT
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PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), // CNVI_RGI_RSP
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PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), // CNVI_RST#
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//PAD_CFG_NF(GPP_F5, NONE, DEEP, NF1), // CNVI_CLKREQ
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PAD_CFG_NF(GPP_F6, NONE, DEEP, NF1), // CNVI_GNSS_PA_BLANKING
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PAD_NC(GPP_F7, NONE), // MCRO LDO BYPASS strap
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//PAD_NC(GPP_F8, NONE),
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PAD_NC(GPP_F9, NONE),
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PAD_NC(GPP_F10, NONE), // RSMRSTB SAMPLING strap
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PAD_NC(GPP_F11, NONE),
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PAD_CFG_GPO(GPP_F12, 0, DEEP), // OVRM
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PAD_NC(GPP_F13, NONE),
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PAD_NC(GPP_F14, NONE),
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PAD_CFG_GPI(GPP_F15, NONE, DEEP), // BOARD_ID6
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PAD_CFG_GPI(GPP_F16, NONE, DEEP), // BOARD_ID7
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PAD_CFG_GPI(GPP_F17, NONE, DEEP), // PLVDD_RST_EC
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PAD_NC(GPP_F18, NONE),
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//PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1), // CARD_CLKREQ#
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PAD_CFG_GPO(GPP_F20, 1, PLTRST), // M.2_PLT_RST_CNTRL1#
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PAD_NC(GPP_F21, NONE),
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PAD_NC(GPP_F22, NONE),
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PAD_NC(GPP_F23, NONE),
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/* ------- GPIO Group GPP_H ------- */
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PAD_NC(GPP_H0, NONE),
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PAD_CFG_GPO(GPP_H1, 1, PLTRST), // M.2_PLT_RST_CNTRL2#
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PAD_CFG_GPO(GPP_H2, 1, PLTRST), // M.2_PLT_RST_CNTRL3#
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PAD_CFG_GPI(GPP_H3, NONE, DEEP), // TPM_DET
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PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), // I2C_SDA_TP (Touchpad)
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PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), // I2C_SCL_TP (Touchpad)
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PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), // PCH_I2C_SDA (Retimer)
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PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), // PCH_I2C_SCL (Retimer)
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PAD_CFG_NF(GPP_H8, NONE, DEEP, NF1), // CNVI_MFUART2_RXD
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PAD_CFG_NF(GPP_H9, NONE, DEEP, NF1), // CNVI_MFUART2_TXD
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//PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
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//PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
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PAD_NC(GPP_H12, NONE),
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PAD_NC(GPP_H13, NONE),
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//PAD_NC(GPP_H14, NONE),
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PAD_NC(GPP_H15, NONE),
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//PAD_NC(GPP_H16, NONE),
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PAD_NC(GPP_H17, NONE),
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PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), // CPU_C10_GATE#
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//PAD_CFG_NF(GPP_H19, NONE, DEEP, NF1), // SSD1_CLKREQ#
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PAD_NC(GPP_H20, NONE),
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PAD_NC(GPP_H21, NONE),
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PAD_NC(GPP_H22, NONE),
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//PAD_CFG_NF(GPP_H23, NONE, DEEP, NF1), // GLAN_CLKREQ#
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||||
/* ------- GPIO Group GPP_R ------- */
|
||||
PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), // HDA_BITCLK
|
||||
PAD_CFG_NF(GPP_R1, NATIVE, DEEP, NF1), // HDA_SYNC
|
||||
PAD_CFG_NF(GPP_R2, NATIVE, DEEP, NF1), // HDA_SDOUT
|
||||
PAD_CFG_NF(GPP_R3, NATIVE, DEEP, NF1), // HDA_SDIN0
|
||||
PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), // HDA_RST#
|
||||
PAD_CFG_GPO(GPP_R5, 1, DEEP), // PCH_MUTE#
|
||||
PAD_CFG_GPI(GPP_R6, NONE, DEEP), // GPPR_DMIC_CLK
|
||||
PAD_CFG_GPI(GPP_R7, NONE, DEEP), // GPPR_DMIC_DATA
|
||||
|
||||
/* ------- GPIO Group GPP_S ------- */
|
||||
PAD_NC(GPP_S0, NONE),
|
||||
PAD_NC(GPP_S1, NONE),
|
||||
PAD_NC(GPP_S2, NONE),
|
||||
PAD_NC(GPP_S3, NONE),
|
||||
PAD_NC(GPP_S4, NONE),
|
||||
PAD_NC(GPP_S5, NONE),
|
||||
PAD_NC(GPP_S6, NONE),
|
||||
PAD_NC(GPP_S7, NONE),
|
||||
|
||||
/* ------- GPIO Group GPP_T ------- */
|
||||
PAD_NC(GPP_T2, NONE),
|
||||
PAD_NC(GPP_T3, NONE),
|
||||
};
|
||||
|
||||
void mainboard_configure_gpios(void)
|
||||
{
|
||||
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||
}
|
||||
16
src/mainboard/system76/adl-p/variants/oryp9/gpio_early.c
Normal file
16
src/mainboard/system76/adl-p/variants/oryp9/gpio_early.c
Normal file
@ -0,0 +1,16 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <mainboard/gpio.h>
|
||||
#include <soc/gpio.h>
|
||||
|
||||
static const struct pad_config early_gpio_table[] = {
|
||||
PAD_CFG_GPO(GPP_A14, 0, DEEP), // DGPU_PWR_EN
|
||||
PAD_CFG_GPO(GPP_B2, 0, DEEP), // DGPU_RST#_CPU
|
||||
PAD_CFG_NF(GPP_H10, NONE, DEEP, NF1), // UART0_RX
|
||||
PAD_CFG_NF(GPP_H11, NONE, DEEP, NF1), // UART0_TX
|
||||
};
|
||||
|
||||
void mainboard_configure_early_gpios(void)
|
||||
{
|
||||
gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
|
||||
}
|
||||
30
src/mainboard/system76/adl-p/variants/oryp9/hda_verb.c
Normal file
30
src/mainboard/system76/adl-p/variants/oryp9/hda_verb.c
Normal file
@ -0,0 +1,30 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <device/azalia_device.h>
|
||||
|
||||
const u32 cim_verb_data[] = {
|
||||
/* Realtek, ALC1220 */
|
||||
0x10ec1220, /* Vendor ID */
|
||||
0x155867f5, /* Subsystem ID */
|
||||
12, /* Number of entries */
|
||||
AZALIA_SUBVENDOR(0, 0x155867f5),
|
||||
AZALIA_PIN_CFG(0, 0x12, 0x90a60130),
|
||||
AZALIA_PIN_CFG(0, 0x14, 0x0421101f),
|
||||
AZALIA_PIN_CFG(0, 0x15, 0x40000000),
|
||||
AZALIA_PIN_CFG(0, 0x16, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x17, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x18, 0x04a11040),
|
||||
AZALIA_PIN_CFG(0, 0x19, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1a, 0x411111f0),
|
||||
AZALIA_PIN_CFG(0, 0x1b, 0x90170110),
|
||||
AZALIA_PIN_CFG(0, 0x1d, 0x40b7952d),
|
||||
AZALIA_PIN_CFG(0, 0x1e, 0x04451150),
|
||||
};
|
||||
|
||||
const u32 pc_beep_verbs[] = {
|
||||
// Enable DMIC microphone on ALC1220
|
||||
0x02050036,
|
||||
0x02042a6a,
|
||||
};
|
||||
|
||||
AZALIA_ARRAY_SIZES;
|
||||
@ -0,0 +1,13 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#ifndef VARIANT_GPIO_H
|
||||
#define VARIANT_GPIO_H
|
||||
|
||||
#include <soc/gpio.h>
|
||||
|
||||
#define DGPU_RST_N GPP_B2
|
||||
#define DGPU_PWR_EN GPP_A14
|
||||
#define DGPU_GC6 GPP_A7
|
||||
#define DGPU_SSID 0x65f51558
|
||||
|
||||
#endif
|
||||
221
src/mainboard/system76/adl-p/variants/oryp9/overridetree.cb
Normal file
221
src/mainboard/system76/adl-p/variants/oryp9/overridetree.cb
Normal file
@ -0,0 +1,221 @@
|
||||
chip soc/intel/alderlake
|
||||
register "power_limits_config[ADL_P_642_682_45W_CORE]" = "{
|
||||
.tdp_pl1_override = 45,
|
||||
.tdp_pl2_override = 115,
|
||||
.tdp_pl4 = 180,
|
||||
}"
|
||||
|
||||
# Thermal
|
||||
register "tcc_offset" = "10"
|
||||
|
||||
# GPE configuration
|
||||
register "pmc_gpe0_dw0" = "PMC_GPP_A"
|
||||
register "pmc_gpe0_dw1" = "PMC_GPP_R"
|
||||
register "pmc_gpe0_dw2" = "PMC_GPD"
|
||||
|
||||
device domain 0 on
|
||||
subsystemid 0x1558 0x65f5 inherit
|
||||
|
||||
device ref pcie5 on
|
||||
# CPU PCIe RP#2 x8, Clock 3 (DGPU)
|
||||
register "cpu_pcie_rp[CPU_RP(2)]" = "{
|
||||
.clk_src = 3,
|
||||
.clk_req = 3,
|
||||
.flags = PCIE_RP_LTR,
|
||||
}"
|
||||
chip drivers/gfx/nvidia
|
||||
device pci 00.0 on end # VGA controller
|
||||
device pci 00.1 on end # Audio device
|
||||
end
|
||||
end
|
||||
device ref igpu on
|
||||
register "ddi_portA_config" = "1"
|
||||
register "ddi_ports_config[DDI_PORT_A]" = "DDI_ENABLE_HPD"
|
||||
end
|
||||
device ref pcie4_0 on
|
||||
# CPU PCIe RP#1 x4, Clock 0 (SSD1)
|
||||
register "cpu_pcie_rp[CPU_RP(1)]" = "{
|
||||
.clk_src = 0,
|
||||
.clk_req = 0,
|
||||
.flags = PCIE_RP_LTR,
|
||||
}"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D14)" # M2_PWR_EN1
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
|
||||
register "srcclk_pin" = "0" # SSD0_CLKREQ#
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref pcie4_1 on
|
||||
# CPU PCIe RP#3 x4, Clock 4 (SSD2)
|
||||
register "cpu_pcie_rp[CPU_RP(3)]" = "{
|
||||
.clk_src = 4,
|
||||
.clk_req = 4,
|
||||
.flags = PCIE_RP_LTR,
|
||||
}"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C2)" # M2_PWR_EN2
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
|
||||
register "srcclk_pin" = "4" # SSD1_CLKREQ#
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref tcss_xhci on
|
||||
register "tcss_ports[0]" = "TCSS_PORT_DEFAULT(OC_SKIP)"
|
||||
chip drivers/usb/acpi
|
||||
device ref tcss_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 TYPEC2""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
device ref tcss_usb3_port1 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref tcss_dma0 on
|
||||
chip drivers/intel/usb4/retimer
|
||||
register "dfp[0].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E4)"
|
||||
use tcss_usb3_port1 as dfp[0].typec_port
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref xhci on
|
||||
# USB2
|
||||
register "usb2_ports[0]" = "USB2_PORT_TYPE_C(OC_SKIP)" # TYPEC1 (USB 3.2 Gen2)
|
||||
register "usb2_ports[1]" = "USB2_PORT_MID(OC_SKIP)" # J_USB2
|
||||
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # J_USB1
|
||||
register "usb2_ports[5]" = "USB2_PORT_MID(OC_SKIP)" # Per-KB
|
||||
register "usb2_ports[6]" = "USB2_PORT_MID(OC_SKIP)" # Fingerprint
|
||||
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Camera
|
||||
register "usb2_ports[8]" = "USB2_PORT_TYPE_C(OC_SKIP)" # TYPEC2 (Thunderbolt)
|
||||
register "usb2_ports[9]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
|
||||
# USB3
|
||||
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC_SKIP)" # TYPEC1 (USB 3.2 Gen2)
|
||||
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB2
|
||||
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # J_USB1
|
||||
# ACPI
|
||||
chip drivers/usb/acpi
|
||||
device ref xhci_root_hub on
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 TYPEC1""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
device ref usb2_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 J_USB2""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
device ref usb2_port2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 J_USB1""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
device ref usb2_port3 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Per-KB""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port6 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Fingerprint""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port7 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Camera""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port8 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 TYPEC2""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
device ref usb2_port9 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB2 Bluetooth""
|
||||
register "type" = "UPC_TYPE_INTERNAL"
|
||||
device ref usb2_port10 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 TYPEC1""
|
||||
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
|
||||
device ref usb3_port1 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 J_USB2""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
device ref usb3_port2 on end
|
||||
end
|
||||
chip drivers/usb/acpi
|
||||
register "desc" = ""USB3 J_USB2""
|
||||
register "type" = "UPC_TYPE_A"
|
||||
device ref usb3_port3 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref sata off end
|
||||
device ref pcie_rp5 on
|
||||
# PCIe RP#5 x1, Clock 2 (WLAN)
|
||||
register "pch_pcie_rp[PCH_RP(5)]" = "{
|
||||
.clk_src = 2,
|
||||
.clk_req = 2,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E3)" # PCH_WLAN_EN
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
|
||||
register "srcclk_pin" = "2" # WLAN_CLKREQ#
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref pcie_rp6 on
|
||||
# PCIe RP#6 x1, Clock 6 (CARD)
|
||||
register "pch_pcie_rp[PCH_RP(6)]" = "{
|
||||
.clk_src = 6,
|
||||
.clk_req = 6,
|
||||
.flags = PCIE_RP_HOTPLUG | PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
# XXX: Enable connected directly to 3.3VS?
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
|
||||
register "srcclk_pin" = "6" # CARD_CLKREQ#
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
device ref pcie_rp8 on
|
||||
# PCIe RP#8 x1, Clock 5 (GLAN)
|
||||
register "pch_pcie_rp[PCH_RP(8)]" = "{
|
||||
.clk_src = 5,
|
||||
.clk_req = 5,
|
||||
.flags = PCIE_RP_LTR | PCIE_RP_AER,
|
||||
}"
|
||||
chip soc/intel/common/block/pcie/rtd3
|
||||
# XXX: Enable connected directly to VDD3?
|
||||
#register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_D4)" # GPIO_LAN_EN
|
||||
register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_B13)" # BUF_PLT_RST#
|
||||
register "srcclk_pin" = "5" # GLAN_CLKREQ#
|
||||
device generic 0 on end
|
||||
end
|
||||
end
|
||||
|
||||
device ref pmc hidden
|
||||
chip drivers/intel/pmc_mux
|
||||
device generic 0 on
|
||||
chip drivers/intel/pmc_mux/conn
|
||||
# TYPEC2
|
||||
use usb2_port9 as usb2_port
|
||||
use tcss_usb3_port1 as usb3_port
|
||||
device generic 0 alias conn0 on end
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
device ref smbus on
|
||||
chip drivers/i2c/tas5825m
|
||||
register "id" = "0"
|
||||
device i2c 4e on end # (8bit address: 0x9c)
|
||||
end
|
||||
end
|
||||
end
|
||||
end
|
||||
39
src/mainboard/system76/adl-p/variants/oryp9/romstage.c
Normal file
39
src/mainboard/system76/adl-p/variants/oryp9/romstage.c
Normal file
@ -0,0 +1,39 @@
|
||||
/* SPDX-License-Identifier: GPL-2.0-only */
|
||||
|
||||
#include <variant/gpio.h>
|
||||
#include <drivers/gfx/nvidia/gpu.h>
|
||||
#include <soc/meminit.h>
|
||||
#include <soc/romstage.h>
|
||||
|
||||
void mainboard_memory_init_params(FSPM_UPD *mupd)
|
||||
{
|
||||
const struct mb_cfg board_cfg = {
|
||||
.type = MEM_TYPE_DDR4,
|
||||
.rcomp = { .resistor = 100, },
|
||||
};
|
||||
const struct mem_spd spd_info = {
|
||||
.topo = MEM_TOPO_DIMM_MODULE,
|
||||
.smbus = {
|
||||
[0] = { .addr_dimm[0] = 0x50, },
|
||||
[1] = { .addr_dimm[0] = 0x52, },
|
||||
},
|
||||
};
|
||||
const bool half_populated = false;
|
||||
|
||||
const struct nvidia_gpu_config config = {
|
||||
.power_gpio = DGPU_PWR_EN,
|
||||
.reset_gpio = DGPU_RST_N,
|
||||
.enable = true,
|
||||
};
|
||||
// Enable dGPU power
|
||||
nvidia_set_power(&config);
|
||||
|
||||
// Set primary display to internal graphics
|
||||
mupd->FspmConfig.PrimaryDisplay = 0;
|
||||
|
||||
mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
|
||||
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
|
||||
mupd->FspmConfig.GpioOverride = 0;
|
||||
|
||||
memcfg_init(mupd, &board_cfg, &spd_info, half_populated);
|
||||
}
|
||||
1770
src/mainboard/system76/adl-p/variants/oryp9/tas5825m.c
Normal file
1770
src/mainboard/system76/adl-p/variants/oryp9/tas5825m.c
Normal file
File diff suppressed because it is too large
Load Diff
Reference in New Issue
Block a user