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soc/mediatek: Move memmory macros into MediaTek common directory

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To reduce duplicate memmory macros of MediaTek SoCs,
move the header file to a common directory.

TEST=Build geralt pass
BUG=b:317009620

Change-Id: Iea4add8fe3735085c13438a2e177bec177913191
Signed-off-by: Jarried Lin <jarried.lin@mediatek.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83571
Reviewed-by: Yidi Lin <yidilin@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Jarried Lin 2024-07-16 18:26:23 +08:00 committed by Felix Held
parent ae37d6158e
commit a87649cee3
6 changed files with 28 additions and 88 deletions
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22
src/soc/mediatek/common/include/soc/memlayout.h Normal file
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@ -0,0 +1,22 @@
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
#include <memlayout.h>
#include <arch/header.ld>
/*
* SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM.
* It will be returned before starting the ramstage.
* SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able.
*/
#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr)
#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr)
#define DRAM_INIT_CODE(addr, size) \
REGION(dram_init_code, addr, size, 64K)
#define DRAM_DMA(addr, size) \
REGION(dram_dma, addr, size, 4K) \
_ = ASSERT(size % 4K == 0, \
"DRAM DMA buffer should be multiple of smallest page size (4K)!");
#define EARLY_INIT(addr, size) \
REGION(early_init_data, addr, size, 4)

17
src/soc/mediatek/mt8173/memlayout.ld
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@ -1,21 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <memlayout.h>
#include <arch/header.ld>
/*
* SRAM_L2C is the half part of L2 cache that we borrow it to be used as SRAM.
* It will be returned before starting the ramstage.
* SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able.
*/
#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr)
#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr)
#define DRAM_DMA(addr, size) \
REGION(dram_dma, addr, size, 4K) \
_ = ASSERT(size % 4K == 0, \
"DRAM DMA buffer should be multiple of smallest page size (4K)!");
#include <soc/memlayout.h>
SECTIONS
{

19
src/soc/mediatek/mt8183/memlayout.ld
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@ -1,23 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <memlayout.h>
#include <arch/header.ld>
/*
* SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM.
* It will be returned before starting the ramstage.
* SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able.
*/
#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr)
#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr)
#define DRAM_INIT_CODE(addr, size) \
REGION(dram_init_code, addr, size, 4)
#define DRAM_DMA(addr, size) \
REGION(dram_dma, addr, size, 4K) \
_ = ASSERT(size % 4K == 0, \
"DRAM DMA buffer should be multiple of smallest page size (4K)!");
#include <soc/memlayout.h>
SECTIONS
{

19
src/soc/mediatek/mt8186/include/soc/memlayout.ld
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@ -1,23 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <memlayout.h>
#include <arch/header.ld>
/*
* SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM.
* It will be returned before starting the ramstage.
* SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able.
*/
#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr)
#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr)
#define DRAM_INIT_CODE(addr, size) \
REGION(dram_init_code, addr, size, 64K)
#define DRAM_DMA(addr, size) \
REGION(dram_dma, addr, size, 4K) \
_ = ASSERT(size % 4K == 0, \
"DRAM DMA buffer should be multiple of smallest page size (4K)!");
#include <soc/memlayout.h>
SECTIONS
{

17
src/soc/mediatek/mt8188/include/soc/memlayout.ld
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@ -1,19 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
#include <memlayout.h>
#include <arch/header.ld>
/*
* SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM.
* It will be returned before starting the ramstage.
* SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able.
*/
#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr)
#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr)
#define DRAM_INIT_CODE(addr, size) \
REGION(dram_init_code, addr, size, 64K)
#define DRAM_DMA(addr, size) \
REGION(dram_dma, addr, size, 4K) \
_ = ASSERT(size % 4K == 0, \
"DRAM DMA buffer should be multiple of smallest page size (4K)!");
#include <soc/memlayout.h>
SECTIONS
{
/* MT8188 has 192KB SRAM in total. */

22
src/soc/mediatek/mt8195/include/soc/memlayout.ld
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@ -1,26 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only OR MIT */
#include <memlayout.h>
#include <arch/header.ld>
/*
* SRAM_L2C is the half part of L2 cache that we borrow to be used as SRAM.
* It will be returned before starting the ramstage.
* SRAM_L2C and SRAM can be cached, but only SRAM is DMA-able.
*/
#define SRAM_L2C_START(addr) REGION_START(sram_l2c, addr)
#define SRAM_L2C_END(addr) REGION_END(sram_l2c, addr)
#define DRAM_INIT_CODE(addr, size) \
REGION(dram_init_code, addr, size, 64K)
#define DRAM_DMA(addr, size) \
REGION(dram_dma, addr, size, 4K) \
_ = ASSERT(size % 4K == 0, \
"DRAM DMA buffer should be multiple of smallest page size (4K)!");
#define EARLY_INIT(addr, size) \
REGION(early_init_data, addr, size, 4)
#include <soc/memlayout.h>
SECTIONS
{