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siemens/mc_apl5: Change PTN interface settings

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Switch the default clock output for single LVDS mode to odd bus only.

Change-Id: I278e761566a112d95cbd6c79e09c076d70b93e8f
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33196
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Mario Scheithauer
2019-06-04 13:43:32 +02:00
committed by Patrick Georgi
parent 37fedc0414
commit aa5e8e099e
1 changed files with 2 additions and 1 deletions
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3
src/mainboard/siemens/mc_apl1/variants/mc_apl5/ptn3460.c
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@ -76,7 +76,8 @@ int ptn3460_init(const char *hwi_block)
return (PTN_BUS_ERROR | status);
/* Set up configuration data according to the hwinfo block we get. */
cfg.dp_interface_ctrl = 0;
cfg.lvds_interface_ctrl1 = 0x00;
/* Drive LVDS clock for single mode on odd bus per default. */
cfg.lvds_interface_ctrl1 = 0x01;
if (disp_con == PF_DISPLCON_LVDS_DUAL)
/* Turn on dual LVDS lane and clock. */
cfg.lvds_interface_ctrl1 |= 0x0b;