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soc/intel/tgl: Replace dt HeciEnabled by HECI1 disable config

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List of changes:
1. Drop `HeciEnabled` from dt and dt chip configuration.
2. Replace all logic that disables HECI1 based on the `HeciEnabled`
chip config with `DISABLE_HECI1_AT_PRE_BOOT` config.

Mainboards that choose to make HECI1 enable during boot don't override
`heci1 disable` config.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I4a81fd58df468e2711108a3243bf116e02986316
Reviewed-on: https://review.coreboot.org/c/coreboot/+/60730
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Subrata Banik 2022-01-03 19:12:55 +00:00 committed by Paul Fagerburg
parent a2f51f2225
commit ad50b40eed
11 changed files with 6 additions and 34 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

3
src/mainboard/google/volteer/variants/baseboard/devicetree.cb
View File

@ -87,9 +87,6 @@ chip soc/intel/tigerlake
register "pmc_gpe0_dw1" = "GPP_D"
register "pmc_gpe0_dw2" = "GPP_E"
# Enable heci communication
register "HeciEnabled" = "1"
# FSP configuration
register "SaGv" = "SaGv_Enabled"

3
src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
View File

@ -8,9 +8,6 @@ chip soc/intel/tigerlake
register "pmc_gpe0_dw1" = "GPP_C"
register "pmc_gpe0_dw2" = "GPP_D"
# Enable heci1 communication
register "HeciEnabled" = "1"
# FSP configuration
register "SaGv" = "SaGv_Enabled"

3
src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
View File

@ -8,9 +8,6 @@ chip soc/intel/tigerlake
register "pmc_gpe0_dw1" = "GPP_C"
register "pmc_gpe0_dw2" = "GPP_D"
# Enable heci1 communication
register "HeciEnabled" = "1"
# FSP configuration
register "SaGv" = "SaGv_Disabled"

1
src/mainboard/starlabs/labtop/variants/tgl/devicetree.cb
View File

@ -18,7 +18,6 @@ chip soc/intel/tigerlake
register "CnviBtCore" = "true"
register "CnviBtAudioOffload" = "1"
register "enable_c6dram" = "1"
register "HeciEnabled" = "1"
register "SaGv" = "SaGv_Enabled"
register "TcssD3ColdDisable" = "1"

4
src/mainboard/system76/darp7/devicetree.cb
View File

@ -242,9 +242,7 @@ chip soc/intel/tigerlake
# TODO: USB-PD?
register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
end
device ref heci1 on
register "HeciEnabled" = "1"
end
device ref heci1 on end
device ref uart2 on
# Debug console
register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"

4
src/mainboard/system76/galp5/devicetree.cb
View File

@ -253,9 +253,7 @@ chip soc/intel/tigerlake
# TODO: Pantone ROM?
register "SerialIoI2cMode[PchSerialIoIndexI2C2]" = "PchSerialIoPci"
end
device ref heci1 on
register "HeciEnabled" = "1"
end
device ref heci1 on end
device ref uart2 on
# Debug console
register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"

4
src/mainboard/system76/gaze16/devicetree.cb
View File

@ -123,9 +123,7 @@ chip soc/intel/tigerlake
device i2c 15 on end
end
end
device ref heci1 on
register "HeciEnabled" = "1"
end
device ref heci1 on end
device ref uart2 on
# Debug console
register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"

4
src/mainboard/system76/lemp10/devicetree.cb
View File

@ -223,9 +223,7 @@ chip soc/intel/tigerlake
# TODO: USB-PD?
register "SerialIoI2cMode[PchSerialIoIndexI2C1]" = "PchSerialIoPci"
end
device ref heci1 on
register "HeciEnabled" = "1"
end
device ref heci1 on end
device ref uart2 on
# Debug console
register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"

4
src/mainboard/system76/oryp8/devicetree.cb
View File

@ -158,9 +158,7 @@ chip soc/intel/tigerlake
device i2c 2c on end
end
end
device ref heci1 on
register "HeciEnabled" = "1"
end
device ref heci1 on end
device ref uart2 on
# Debug console
register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"

4
src/soc/intel/tigerlake/chip.h
View File

@ -276,10 +276,6 @@ struct soc_intel_tigerlake_config {
/* Gfx related */
uint8_t SkipExtGfxScan;
/* HeciEnabled decides the state of Heci1 at end of boot
* Setting to 0 (default) disables Heci1 and hides the device from OS */
uint8_t HeciEnabled;
/* Enable/Disable EIST. 1b:Enabled, 0b:Disabled */
uint8_t eist_enable;

6
src/soc/intel/tigerlake/smihandler.c
View File

@ -16,11 +16,7 @@
*/
void smihandler_soc_at_finalize(void)
{
const struct soc_intel_tigerlake_config *config;
config = config_of_soc();
if (!config->HeciEnabled && CONFIG(HECI_DISABLE_USING_SMM))
if (CONFIG(DISABLE_HECI1_AT_PRE_BOOT) && CONFIG(HECI_DISABLE_USING_SMM))
heci_disable();
}