chromeos / broadwell / jecht: Make save_chromeos_gpios() jecht-specific
This callback was only required for a single mainboard, and it can easily be moved to mainboard-specific code. This patch removes it from the global namespace and isolates it to the Jecht board. (This makes it easier to separate vboot and chromeos code in a later patch.) Change-Id: I9cf67a75a052d1c86eda0393b6a9fbbe255fedf8 Signed-off-by: Julius Werner <jwerner@chromium.org> Reviewed-on: https://review.coreboot.org/18981 Reviewed-by: Aaron Durbin <adurbin@chromium.org> Tested-by: build bot (Jenkins)
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@ -22,6 +22,7 @@
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#include <ec/google/chromeec/ec.h>
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#include <ec/google/chromeec/ec.h>
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#include <soc/gpio.h>
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#include <soc/gpio.h>
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#include <soc/sata.h>
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#include <soc/sata.h>
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#include "onboard.h"
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#define GPIO_SPI_WP 58
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#define GPIO_SPI_WP 58
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#define GPIO_REC_MODE 12
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#define GPIO_REC_MODE 12
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@ -19,6 +19,8 @@
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#ifndef __ACPI__
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#ifndef __ACPI__
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void lan_init(void);
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void lan_init(void);
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void save_chromeos_gpios(void);
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void set_power_led(int state);
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void set_power_led(int state);
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enum {
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enum {
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@ -46,6 +46,9 @@ void mainboard_romstage_entry(struct romstage_params *rp)
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/* Call into the real romstage main with this board's attributes. */
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/* Call into the real romstage main with this board's attributes. */
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romstage_common(rp);
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romstage_common(rp);
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if (IS_ENABLED(CONFIG_CHROMEOS))
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save_chromeos_gpios();
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}
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}
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void mainboard_pre_console_init(void)
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void mainboard_pre_console_init(void)
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@ -19,6 +19,7 @@
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#include <arch/io.h>
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#include <arch/io.h>
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#include <arch/cbfs.h>
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#include <arch/cbfs.h>
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#include <arch/early_variables.h>
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#include <arch/early_variables.h>
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#include <bootmode.h>
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#include <console/console.h>
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#include <console/console.h>
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#include <cbfs.h>
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#include <cbfs.h>
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#include <cbmem.h>
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#include <cbmem.h>
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@ -35,7 +36,6 @@
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#include <soc/reset.h>
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#include <soc/reset.h>
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#include <soc/romstage.h>
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#include <soc/romstage.h>
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#include <soc/spi.h>
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#include <soc/spi.h>
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#include <vendorcode/google/chromeos/chromeos.h>
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/* Entry from cache-as-ram.inc. */
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/* Entry from cache-as-ram.inc. */
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asmlinkage void *romstage_main(unsigned long bist,
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asmlinkage void *romstage_main(unsigned long bist,
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@ -79,10 +79,6 @@ asmlinkage void *romstage_main(unsigned long bist,
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/* Call into mainboard. */
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/* Call into mainboard. */
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mainboard_romstage_entry(&rp);
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mainboard_romstage_entry(&rp);
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#if CONFIG_CHROMEOS
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save_chromeos_gpios();
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#endif
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return setup_stack_and_mttrs();
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return setup_stack_and_mttrs();
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}
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}
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@ -23,11 +23,6 @@ int __attribute__((weak)) clear_recovery_mode_switch(void)
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return 0;
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return 0;
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}
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}
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void __attribute__((weak)) save_chromeos_gpios(void)
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{
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// Can be implemented by a mainboard
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}
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int __attribute__((weak)) get_sw_write_protect_state(void)
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int __attribute__((weak)) get_sw_write_protect_state(void)
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{
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{
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// Can be implemented by a platform / mainboard
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// Can be implemented by a platform / mainboard
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@ -24,8 +24,6 @@
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#include <vboot/misc.h>
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#include <vboot/misc.h>
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#include <vboot/vboot_common.h>
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#include <vboot/vboot_common.h>
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void save_chromeos_gpios(void);
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#if CONFIG_CHROMEOS
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#if CONFIG_CHROMEOS
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/* functions implemented in watchdog.c */
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/* functions implemented in watchdog.c */
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void mark_watchdog_tombstone(void);
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void mark_watchdog_tombstone(void);
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