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Add AMD Family 12 cpu Agesa code

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This is the addition of the AMD Family 12 cpu code.

Change-Id: I3febc81e192b4e86bbd3e8d6e1da62a28598fa8c
Signed-off-by: Frank Vibrans<frank.vibrans@amd.com>
Signed-off-by: efdesign98 <efdesign98@gmail.com>
Reviewed-on: http://review.coreboot.org/40
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marcj303@gmail.com>
This commit is contained in:
efdesign98 2011-06-16 16:35:54 -07:00 committed by Marc Jones
parent d1cb0eecd1
commit b0969d65e6
1045 changed files with 320885 additions and 0 deletions
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src/vendorcode/amd/agesa/f12/AGESA.h Executable file
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/* $NoKeywords:$ */
/**
* @file
*
* Agesa structures and definitions
*
* Contains AMD AGESA core interface
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Include
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _AMD_H_
#define _AMD_H_
#define AGESA_REVISION "Arch2008"
#define AGESA_ID "AGESA"
#define Int16FromChar(a,b) ((a) << 0 | (b) << 8)
#define Int32FromChar(a,b,c,d) ((a) << 0 | (b) << 8 | (c) << 16 | (d) << 24)
//
//
// AGESA Types and Definitions
//
//
#define LAST_ENTRY 0xFFFFFFFF
#define IMAGE_SIGNATURE Int32FromChar ('$', 'A', 'M', 'D')
#define IOCF8 0xCF8
#define IOCFC 0xCFC
/// The return status for all AGESA public services.
///
/// Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
/// will have log entries with more detail.
///
typedef enum {
AGESA_SUCCESS = 0, ///< The service completed normally. Info may be logged.
AGESA_UNSUPPORTED, ///< The dispatcher or create struct had an unimplemented function requested.
///< Not logged.
AGESA_BOUNDS_CHK, ///< A dynamic parameter was out of range and the service was not provided.
///< Example, memory address not installed, heap buffer handle not found.
///< Not Logged.
// AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
AGESA_ALERT, ///< An observed condition, but no loss of function.
///< See log. Example, HT CRC.
AGESA_WARNING, ///< Possible or minor loss of function. See Log.
AGESA_ERROR, ///< Significant loss of function, boot may be possible. See Log.
AGESA_CRITICAL, ///< Continue boot only to notify user. See Log.
AGESA_FATAL, ///< Halt booting. See Log, however Fatal errors pertaining to heap problems
///< may not be able to reliably produce log events.
AgesaStatusMax ///< Not a status, for limit checking.
} AGESA_STATUS;
/// For checking whether a status is at or above the mandatory log level.
#define AGESA_STATUS_LOG_LEVEL AGESA_ALERT
/**
* Callout method to the host environment.
*
* Callout using a dispatch with appropriate thunk layer, which is determined by the host environment.
*
* @param[in] Function The specific callout function being invoked.
* @param[in] FcnData Function specific data item.
* @param[in,out] ConfigPtr Reference to Callout params.
*/
typedef AGESA_STATUS (*CALLOUT_ENTRY) (
IN UINT32 Function,
IN UINTN FcnData,
IN OUT VOID *ConfigPtr
);
typedef AGESA_STATUS (*IMAGE_ENTRY) (VOID *ConfigPtr);
typedef AGESA_STATUS (*MODULE_ENTRY) (VOID *ConfigPtr);
///This allocation type is used by the AmdCreateStruct entry point
typedef enum {
PreMemHeap = 0, ///< Create heap in cache.
PostMemDram, ///< Create heap in memory.
ByHost ///< Create heap by Host.
} ALLOCATION_METHOD;
/// These width descriptors are used by the library function, and others, to specify the data size
typedef enum ACCESS_WIDTH {
AccessWidth8 = 1, ///< Access width is 8 bits.
AccessWidth16, ///< Access width is 16 bits.
AccessWidth32, ///< Access width is 32 bits.
AccessWidth64, ///< Access width is 64 bits.
AccessS3SaveWidth8 = 0x81, ///< Save 8 bits data.
AccessS3SaveWidth16, ///< Save 16 bits data.
AccessS3SaveWidth32, ///< Save 32 bits data.
AccessS3SaveWidth64, ///< Save 64 bits data.
} ACCESS_WIDTH;
/// AGESA struct name
typedef enum {
// AGESA BASIC FUNCTIONS
AMD_INIT_RECOVERY = 0x00020000, ///< AmdInitRecovery entry point handle
AMD_CREATE_STRUCT, ///< AmdCreateStruct handle
AMD_INIT_EARLY, ///< AmdInitEarly entry point handle
AMD_INIT_ENV, ///< AmdInitEnv entry point handle
AMD_INIT_LATE, ///< AmdInitLate entry point handle
AMD_INIT_MID, ///< AmdInitMid entry point handle
AMD_INIT_POST, ///< AmdInitPost entry point handle
AMD_INIT_RESET, ///< AmdInitReset entry point handle
AMD_INIT_RESUME, ///< AmdInitResume entry point handle
AMD_RELEASE_STRUCT, ///< AmdReleaseStruct handle
AMD_S3LATE_RESTORE, ///< AmdS3LateRestore entry point handle
AMD_S3_SAVE, ///< AmdS3Save entry point handle
AMD_GET_APIC_ID, ///< AmdGetApicId entry point handle
AMD_GET_PCI_ADDRESS, ///< AmdGetPciAddress entry point handle
AMD_IDENTIFY_CORE, ///< AmdIdentifyCore general service handle
AMD_READ_EVENT_LOG, ///< AmdReadEventLog general service handle
AMD_GET_EXECACHE_SIZE, ///< AmdGetAvailableExeCacheSize general service handle
AMD_LATE_RUN_AP_TASK, ///< AmdLateRunApTask entry point handle
AMD_IDENTIFY_DIMMS ///< AmdIdentifyDimm general service handle
} AGESA_STRUCT_NAME;
/* ResetType constant values */
#define WARM_RESET_WHENEVER 1
#define COLD_RESET_WHENEVER 2
#define WARM_RESET_IMMEDIATELY 3
#define COLD_RESET_IMMEDIATELY 4
// AGESA Structures
/// The standard header for all AGESA services.
/// For internal AGESA naming conventions, see @ref amdconfigparamname .
typedef struct {
IN UINT32 ImageBasePtr; ///< The AGESA Image base address.
IN UINT32 Func; ///< The service desired
IN UINT32 AltImageBasePtr; ///< Alternate Image location
IN CALLOUT_ENTRY CalloutPtr; ///< For Callout from AGESA
IN UINT8 HeapStatus; ///< For heap status from boot time slide.
IN UINT64 HeapBasePtr; ///< Location of the heap
IN OUT UINT8 Reserved[7]; ///< This space is reserved for future use.
} AMD_CONFIG_PARAMS;
/// Create Struct Interface.
typedef struct {
IN AMD_CONFIG_PARAMS StdHeader; ///< Standard configuration header
IN AGESA_STRUCT_NAME AgesaFunctionName; ///< The service to init
IN ALLOCATION_METHOD AllocationMethod; ///< How to handle buffer allocation
IN OUT UINT32 NewStructSize; ///< The size of the allocated data, in for ByHost, else out only.
IN OUT VOID *NewStructPtr; ///< The struct for the service.
///< The struct to init for ByHost allocation,
///< the initialized struct on return.
} AMD_INTERFACE_PARAMS;
#define FUNC_0 0 // bit-placed for PCI address creation
#define FUNC_1 1
#define FUNC_2 2
#define FUNC_3 3
#define FUNC_4 4
#define FUNC_5 5
#define FUNC_6 6
#define FUNC_7 7
/// AGESA Binary module header structure
typedef struct {
IN UINT32 Signature; ///< Binary Signature
IN CHAR8 CreatorID[8]; ///< 8 characters ID
IN CHAR8 Version[12]; ///< 12 characters version
IN UINT32 ModuleInfoOffset; ///< Offset of module
IN UINT32 EntryPointAddress; ///< Entry address
IN UINT32 ImageBase; ///< Image base
IN UINT32 RelocTableOffset; ///< Relocate Table offset
IN UINT32 ImageSize; ///< Size
IN UINT16 Checksum; ///< Checksum
IN UINT8 ImageType; ///< Type
IN UINT8 V_Reserved; ///< Reserved
} AMD_IMAGE_HEADER;
/// AGESA Binary module header structure
typedef struct _AMD_MODULE_HEADER {
IN UINT32 ModuleHeaderSignature; ///< Module signature
IN CHAR8 ModuleIdentifier[8]; ///< 8 characters ID
IN CHAR8 ModuleVersion[12]; ///< 12 characters version
IN VOID *ModuleDispatcher; ///< A pointer point to dispatcher
IN struct _AMD_MODULE_HEADER *NextBlock; ///< Next module header link
} AMD_MODULE_HEADER;
// AMD_CODE_HEADER Signatures.
#define AGESA_CODE_SIGNATURE {'!', '!', 'A', 'G', 'E', 'S', 'A', ' '}
#define CIMXNB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'}
#define CIMXSB_CODE_SIGNATURE {'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'}
/// AGESA_CODE_SIGNATURE
typedef struct {
IN CHAR8 Signature[8]; ///< code header Signature
IN CHAR8 ComponentName[8]; ///< 8 character name of the code module
IN CHAR8 Version[12]; ///< 12 character version string
IN CHAR8 TerminatorNull; ///< null terminated string
IN CHAR8 VerReserved[7]; ///< reserved space
} AMD_CODE_HEADER;
/// Extended PCI address format
typedef struct {
IN OUT UINT32 Register:12; ///< Register offset
IN OUT UINT32 Function:3; ///< Function number
IN OUT UINT32 Device:5; ///< Device number
IN OUT UINT32 Bus:8; ///< Bus number
IN OUT UINT32 Segment:4; ///< Segment
} EXT_PCI_ADDR;
/// Union type for PCI address
typedef union _PCI_ADDR {
IN UINT32 AddressValue; ///< Formal address
IN EXT_PCI_ADDR Address; ///< Extended address
} PCI_ADDR;
// SBDFO - Segment Bus Device Function Offset
// 31:28 Segment (4-bits)
// 27:20 Bus (8-bits)
// 19:15 Device (5-bits)
// 14:12 Function(3-bits)
// 11:00 Offset (12-bits)
#define MAKE_SBDFO(Seg, Bus, Dev, Fun, Off) ((((UINT32) (Seg)) << 28) | (((UINT32) (Bus)) << 20) | \
(((UINT32)(Dev)) << 15) | (((UINT32)(Fun)) << 12) | ((UINT32)(Off)))
#define ILLEGAL_SBDFO 0xFFFFFFFF
/// CPUID data received registers format
typedef struct {
OUT UINT32 EAX_Reg; ///< CPUID instruction result in EAX
OUT UINT32 EBX_Reg; ///< CPUID instruction result in EBX
OUT UINT32 ECX_Reg; ///< CPUID instruction result in ECX
OUT UINT32 EDX_Reg; ///< CPUID instruction result in EDX
} CPUID_DATA;
/// HT frequency for external callbacks
typedef enum {
HT_FREQUENCY_200M = 0, ///< HT speed 200 for external callbacks
HT_FREQUENCY_400M = 2, ///< HT speed 400 for external callbacks
HT_FREQUENCY_600M = 4, ///< HT speed 600 for external callbacks
HT_FREQUENCY_800M = 5, ///< HT speed 800 for external callbacks
HT_FREQUENCY_1000M = 6, ///< HT speed 1000 for external callbacks
HT_FREQUENCY_1200M = 7, ///< HT speed 1200 for external callbacks
HT_FREQUENCY_1400M = 8, ///< HT speed 1400 for external callbacks
HT_FREQUENCY_1600M = 9, ///< HT speed 1600 for external callbacks
HT_FREQUENCY_1800M = 10, ///< HT speed 1800 for external callbacks
HT_FREQUENCY_2000M = 11, ///< HT speed 2000 for external callbacks
HT_FREQUENCY_2200M = 12, ///< HT speed 2200 for external callbacks
HT_FREQUENCY_2400M = 13, ///< HT speed 2400 for external callbacks
HT_FREQUENCY_2600M = 14, ///< HT speed 2600 for external callbacks
HT_FREQUENCY_2800M = 17, ///< HT speed 2800 for external callbacks
HT_FREQUENCY_3000M = 18, ///< HT speed 3000 for external callbacks
HT_FREQUENCY_3200M = 19, ///< HT speed 3200 for external callbacks
HT_FREQUENCY_MAX ///< Limit check.
} HT_FREQUENCIES;
// The minimum HT3 frequency
#define HT3_FREQUENCY_MIN HT_FREQUENCY_1200M
#ifndef BIT0
#define BIT0 0x0000000000000001ull
#endif
#ifndef BIT1
#define BIT1 0x0000000000000002ull
#endif
#ifndef BIT2
#define BIT2 0x0000000000000004ull
#endif
#ifndef BIT3
#define BIT3 0x0000000000000008ull
#endif
#ifndef BIT4
#define BIT4 0x0000000000000010ull
#endif
#ifndef BIT5
#define BIT5 0x0000000000000020ull
#endif
#ifndef BIT6
#define BIT6 0x0000000000000040ull
#endif
#ifndef BIT7
#define BIT7 0x0000000000000080ull
#endif
#ifndef BIT8
#define BIT8 0x0000000000000100ull
#endif
#ifndef BIT9
#define BIT9 0x0000000000000200ull
#endif
#ifndef BIT10
#define BIT10 0x0000000000000400ull
#endif
#ifndef BIT11
#define BIT11 0x0000000000000800ull
#endif
#ifndef BIT12
#define BIT12 0x0000000000001000ull
#endif
#ifndef BIT13
#define BIT13 0x0000000000002000ull
#endif
#ifndef BIT14
#define BIT14 0x0000000000004000ull
#endif
#ifndef BIT15
#define BIT15 0x0000000000008000ull
#endif
#ifndef BIT16
#define BIT16 0x0000000000010000ull
#endif
#ifndef BIT17
#define BIT17 0x0000000000020000ull
#endif
#ifndef BIT18
#define BIT18 0x0000000000040000ull
#endif
#ifndef BIT19
#define BIT19 0x0000000000080000ull
#endif
#ifndef BIT20
#define BIT20 0x0000000000100000ull
#endif
#ifndef BIT21
#define BIT21 0x0000000000200000ull
#endif
#ifndef BIT22
#define BIT22 0x0000000000400000ull
#endif
#ifndef BIT23
#define BIT23 0x0000000000800000ull
#endif
#ifndef BIT24
#define BIT24 0x0000000001000000ull
#endif
#ifndef BIT25
#define BIT25 0x0000000002000000ull
#endif
#ifndef BIT26
#define BIT26 0x0000000004000000ull
#endif
#ifndef BIT27
#define BIT27 0x0000000008000000ull
#endif
#ifndef BIT28
#define BIT28 0x0000000010000000ull
#endif
#ifndef BIT29
#define BIT29 0x0000000020000000ull
#endif
#ifndef BIT30
#define BIT30 0x0000000040000000ull
#endif
#ifndef BIT31
#define BIT31 0x0000000080000000ull
#endif
#ifndef BIT32
#define BIT32 0x0000000100000000ull
#endif
#ifndef BIT33
#define BIT33 0x0000000200000000ull
#endif
#ifndef BIT34
#define BIT34 0x0000000400000000ull
#endif
#ifndef BIT35
#define BIT35 0x0000000800000000ull
#endif
#ifndef BIT36
#define BIT36 0x0000001000000000ull
#endif
#ifndef BIT37
#define BIT37 0x0000002000000000ull
#endif
#ifndef BIT38
#define BIT38 0x0000004000000000ull
#endif
#ifndef BIT39
#define BIT39 0x0000008000000000ull
#endif
#ifndef BIT40
#define BIT40 0x0000010000000000ull
#endif
#ifndef BIT41
#define BIT41 0x0000020000000000ull
#endif
#ifndef BIT42
#define BIT42 0x0000040000000000ull
#endif
#ifndef BIT43
#define BIT43 0x0000080000000000ull
#endif
#ifndef BIT44
#define BIT44 0x0000100000000000ull
#endif
#ifndef BIT45
#define BIT45 0x0000200000000000ull
#endif
#ifndef BIT46
#define BIT46 0x0000400000000000ull
#endif
#ifndef BIT47
#define BIT47 0x0000800000000000ull
#endif
#ifndef BIT48
#define BIT48 0x0001000000000000ull
#endif
#ifndef BIT49
#define BIT49 0x0002000000000000ull
#endif
#ifndef BIT50
#define BIT50 0x0004000000000000ull
#endif
#ifndef BIT51
#define BIT51 0x0008000000000000ull
#endif
#ifndef BIT52
#define BIT52 0x0010000000000000ull
#endif
#ifndef BIT53
#define BIT53 0x0020000000000000ull
#endif
#ifndef BIT54
#define BIT54 0x0040000000000000ull
#endif
#ifndef BIT55
#define BIT55 0x0080000000000000ull
#endif
#ifndef BIT56
#define BIT56 0x0100000000000000ull
#endif
#ifndef BIT57
#define BIT57 0x0200000000000000ull
#endif
#ifndef BIT58
#define BIT58 0x0400000000000000ull
#endif
#ifndef BIT59
#define BIT59 0x0800000000000000ull
#endif
#ifndef BIT60
#define BIT60 0x1000000000000000ull
#endif
#ifndef BIT61
#define BIT61 0x2000000000000000ull
#endif
#ifndef BIT62
#define BIT62 0x4000000000000000ull
#endif
#ifndef BIT63
#define BIT63 0x8000000000000000ull
#endif
#endif // _AMD_H_

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src/vendorcode/amd/agesa/f12/Dispatcher.h Executable file
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/* $NoKeywords:$ */
/**
* @file
*
* AMD Pushhigh Interface
*
* Contains interface to Pushhigh entry
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Legacy
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ***************************************************************************
*/
#ifndef _DISPATCHER_H_
#define _DISPATCHER_H_
// AGESA function prototypes
AGESA_STATUS CALLCONV AmdAgesaDispatcher ( IN OUT VOID *ConfigPtr );
AGESA_STATUS CALLCONV AmdAgesaCallout ( IN UINT32 Func, IN UINT32 Data, IN OUT VOID *ConfigPtr );
#endif // _DISPATCHER_H_

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src/vendorcode/amd/agesa/f12/Include/AdvancedApi.h Executable file
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/* $NoKeywords:$ */
/**
* @file
*
* Advanced API Interface for HT, Memory and CPU
*
* Contains additional declarations need to use HT, Memory and CPU Advanced interface, such as
* would be required by the basic interface implementations.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Include
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _ADVANCED_API_H_
#define _ADVANCED_API_H_
/*----------------------------------------------------------------------------
* HT FUNCTIONS PROTOTYPE
*
*----------------------------------------------------------------------------
*/
/**
* A constructor for the HyperTransport input structure.
*
* Sets inputs to valid, basic level, defaults.
*
* @param[in] StdHeader Opaque handle to standard config header
* @param[in] AmdHtInterface HT Interface structure to initialize.
*
* @retval AGESA_SUCCESS Constructors are not allowed to fail
*/
AGESA_STATUS
AmdHtInterfaceConstructor (
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_HT_INTERFACE *AmdHtInterface
);
/**
* The top level external interface for Hypertransport Initialization.
*
* Create our initial internal state, initialize the coherent fabric,
* initialize the non-coherent chains, and perform any required fabric tuning or
* optimization.
*
* @param[in] StdHeader Opaque handle to standard config header
* @param[in] PlatformConfiguration The platform configuration options.
* @param[in] AmdHtInterface HT Interface structure.
*
* @retval AGESA_SUCCESS Only information events logged.
* @retval AGESA_ALERT Sync Flood or CRC error logged.
* @retval AGESA_WARNING Example: expected capability not found
* @retval AGESA_ERROR logged events indicating some devices may not be available
* @retval AGESA_FATAL Mixed Family or MP capability mismatch
*
*/
AGESA_STATUS
AmdHtInitialize (
IN AMD_CONFIG_PARAMS *StdHeader,
IN PLATFORM_CONFIGURATION *PlatformConfiguration,
IN AMD_HT_INTERFACE *AmdHtInterface
);
/*----------------------------------------------------------------------------
* HT Recovery FUNCTIONS PROTOTYPE
*
*----------------------------------------------------------------------------
*/
/**
* A constructor for the HyperTransport input structure.
*
*/
AGESA_STATUS
AmdHtResetConstructor (
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
);
/**
* Initialize HT at Reset for both Normal and Recovery.
*
*/
AGESA_STATUS
AmdHtInitReset (
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
);
/**
* Initialize the Node and Socket maps for an AP Core.
*
*/
AGESA_STATUS
AmdHtInitRecovery (
IN AMD_CONFIG_PARAMS *StdHeader
);
///----------------------------------------------------------------------------
/// MEMORY FUNCTIONS PROTOTYPE
///
///----------------------------------------------------------------------------
AGESA_STATUS
AmdMemRecovery (
IN OUT MEM_DATA_STRUCT *MemPtr
);
AGESA_STATUS
AmdMemAuto (
IN OUT MEM_DATA_STRUCT *MemPtr
);
VOID
AmdMemInitDataStructDef (
IN OUT MEM_DATA_STRUCT *MemPtr,
IN OUT PLATFORM_CONFIGURATION *PlatFormConfig
);
VOID
memDefRet (
VOID
);
BOOLEAN
memDefTrue (
VOID
);
BOOLEAN
memDefFalse (
VOID
);
VOID
MemRecDefRet (VOID);
BOOLEAN
MemRecDefTrue (VOID);
#endif // _ADVANCED_API_H_

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src/vendorcode/amd/agesa/f12/Include/BrazosInstall.h Executable file
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/* $NoKeywords:$ */
/**
* @file
*
* Install of build options for a Brazos platform solution
*
* This file generates the defaults tables for the "Brazos" platform solution
* set of processors. The documented build options are imported from a user
* controlled file for processing.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#include "cpuRegisters.h"
#include "cpuFamRegisters.h"
#include "cpuFamilyTranslation.h"
#include "AdvancedApi.h"
#include "heapManager.h"
#include "CreateStruct.h"
#include "cpuFeatures.h"
#include "Table.h"
#include "CommonReturns.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "GnbInterface.h"
/*****************************************************************************
* Define the RELEASE VERSION string
*
* The Release Version string should identify the next planned release.
* When a branch is made in preparation for a release, the release manager
* should change/confirm that the branch version of this file contains the
* string matching the desired version for the release. The trunk version of
* the file should always contain a trailing 'X'. This will make sure that a
* development build from trunk will not be confused for a released version.
* The release manager will need to remove the trailing 'X' and update the
* version string as appropriate for the release. The trunk copy of this file
* should also be updated/incremented for the next expected version, + trailing 'X'
****************************************************************************/
// This is the delivery package title, "BrazosPI"
// This string MUST be exactly 8 characters long
#define AGESA_PACKAGE_STRING {'O', 'n', 't', 'a', 'r', 'o', 'P', 'I'}
// This is the release version number of the AGESA component
// This string MUST be exactly 12 characters long
#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '7', '.', '2', 'X', ' ', ' ', ' '}
// The Brazos solution is defined to be family 0x14 in the FT1 socket.
#define INSTALL_FT1_SOCKET_SUPPORT TRUE
#define INSTALL_FAMILY_14_SUPPORT TRUE
// The following definitions specify the default values for various parameters in which there are
// no clearly defined defaults to be used in the common file. The values below are based on product
// and BKDG content, please consult the AGESA Memory team for consultation.
#define DFLT_SCRUB_DRAM_RATE (0)
#define DFLT_SCRUB_L2_RATE (0)
#define DFLT_SCRUB_L3_RATE (0)
#define DFLT_SCRUB_IC_RATE (0)
#define DFLT_SCRUB_DC_RATE (0)
#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
#define DFLT_VRM_SLEW_RATE (5000)
// Instantiate all solution relevant data.
#include "PlatformInstall.h"

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build options for a Comal platform solution
*
* This file generates the defaults tables for the "Comal" platform solution
* set of processors. The documented build options are imported from a user
* controlled file for processing.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 49803 $ @e \$Date: 2011-03-29 15:20:04 +0800 (Tue, 29 Mar 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#include "cpuRegisters.h"
#include "cpuFamRegisters.h"
#include "cpuFamilyTranslation.h"
#include "AdvancedApi.h"
#include "heapManager.h"
#include "CreateStruct.h"
#include "cpuFeatures.h"
#include "Table.h"
#include "CommonReturns.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "GnbInterface.h"
/*****************************************************************************
* Define the RELEASE VERSION string
*
* The Release Version string should identify the next planned release.
* When a branch is made in preparation for a release, the release manager
* should change/confirm that the branch version of this file contains the
* string matching the desired version for the release. The trunk version of
* the file should always contain a trailing 'X'. This will make sure that a
* development build from trunk will not be confused for a released version.
* The release manager will need to remove the trailing 'X' and update the
* version string as appropriate for the release. The trunk copy of this file
* should also be updated/incremented for the next expected version, + trailing 'X'
****************************************************************************/
// This is the delivery package title, "TrinyPI "
// This string MUST be exactly 8 characters long
#define AGESA_PACKAGE_STRING {'T', 'r', 'i', 'n', 'y', 'P', 'I', ' '}
// This is the release version number of the AGESA component
// This string MUST be exactly 12 characters long
#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '6', '.', '0', 'X', ' ', ' ', ' '}
// The Comal solution is defined to be family 0x15 in the FS1 and FP2 sockets.
#define INSTALL_FS1_SOCKET_SUPPORT TRUE
#define INSTALL_FP2_SOCKET_SUPPORT TRUE
#define INSTALL_FAMILY_15_SUPPORT TRUE
#ifdef BLDOPT_REMOVE_FS1_SOCKET_SUPPORT
#if BLDOPT_REMOVE_FS1_SOCKET_SUPPORT == TRUE
#undef INSTALL_FS1_SOCKET_SUPPORT
#define INSTALL_FS1_SOCKET_SUPPORT FALSE
#endif
#endif
#ifdef BLDOPT_REMOVE_FP2_SOCKET_SUPPORT
#if BLDOPT_REMOVE_FP2_SOCKET_SUPPORT == TRUE
#undef INSTALL_FP2_SOCKET_SUPPORT
#define INSTALL_FP2_SOCKET_SUPPORT FALSE
#endif
#endif
// The following definitions specify the default values for various parameters in which there are
// no clearly defined defaults to be used in the common file. The values below are based on product
// and BKDG content, please consult the AGESA Memory team for consultation.
#define DFLT_SCRUB_DRAM_RATE (0)
#define DFLT_SCRUB_L2_RATE (0)
#define DFLT_SCRUB_L3_RATE (0)
#define DFLT_SCRUB_IC_RATE (0)
#define DFLT_SCRUB_DC_RATE (0)
#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
#define DFLT_VRM_SLEW_RATE (5000)
#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x420
#define DFLT_SPI_BASE_ADDRESS 0xFEC10000
#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC00000
#define DFLT_HPET_BASE_ADDRESS 0xFED00000
#define DFLT_SMI_CMD_PORT 0xB0
#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
#define DFLT_GEC_BASE_ADDRESS 0xFED61000
#define DFLT_AZALIA_SSID 0x780D1022
#define DFLT_SMBUS_SSID 0x780B1022
#define DFLT_IDE_SSID 0x780C1022
#define DFLT_SATA_AHCI_SSID 0x78011022
#define DFLT_SATA_IDE_SSID 0x78001022
#define DFLT_SATA_RAID5_SSID 0x78031022
#define DFLT_SATA_RAID_SSID 0x78021022
#define DFLT_EHCI_SSID 0x78081022
#define DFLT_OHCI_SSID 0x78071022
#define DFLT_LPC_SSID 0x780E1022
#define DFLT_FCH_GPP_LINK_CONFIG PortA4
#define DFLT_FCH_GPP_PORT0_PRESENT FALSE
#define DFLT_FCH_GPP_PORT1_PRESENT FALSE
#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
// Instantiate all solution relevant data.
#include "PlatformInstall.h"

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/* $NoKeywords:$ */
/**
* @file
*
* Common Return routines.
*
* Routines which do nothing, returning a result (preferably some version of zero) which
* is consistent with "do nothing" or "default". Useful for function pointer tables.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Common
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ***************************************************************************
*
*/
#ifndef _COMMON_RETURNS_H_
#define _COMMON_RETURNS_H_
/**
* Return True
*
* @retval True Default case, no special action
*/
BOOLEAN
CommonReturnTrue (void);
/**
* Return False.
*
* @retval FALSE Default case, no special action
*/
BOOLEAN
CommonReturnFalse (void);
/**
* Return (UINT8)zero.
*
*
* @retval zero None, or only case zero.
*/
UINT8
CommonReturnZero8 (void);
/**
* Return (UINT32)zero.
*
*
* @retval zero None, or only case zero.
*/
UINT32
CommonReturnZero32 (void);
/**
* Return (UINT64)zero.
*
*
* @retval zero None, or only case zero.
*/
UINT64
CommonReturnZero64 (void);
/**
* Return NULL
*
* @retval NULL pointer to nothing
*/
VOID *
CommonReturnNULL (void);
/**
* Return AGESA_SUCCESS.
*
* @retval AGESA_SUCCESS Success.
*/
AGESA_STATUS
CommonReturnAgesaSuccess (void);
/**
* Do Nothing.
*
*/
VOID
CommonVoid (void);
/**
* ASSERT if this routine is called.
*
*/
VOID
CommonAssert (void);
#endif // _COMMON_RETURNS_H_

114
src/vendorcode/amd/agesa/f12/Include/DanNiInstall.h Executable file
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/* $NoKeywords:$ */
/**
* @file
*
* Install of build options for a Danube + Nile platform solution
*
* This file generates the defaults tables for the "DanNi" platform solution
* set of processors. The documented build options are imported from a user
* controlled file for processing.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#include "cpuRegisters.h"
#include "cpuFamRegisters.h"
#include "cpuFamilyTranslation.h"
#include "AdvancedApi.h"
#include "heapManager.h"
#include "CreateStruct.h"
#include "cpuFeatures.h"
#include "Table.h"
#include "CommonReturns.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "GnbInterfaceStub.h"
/*****************************************************************************
* Define the RELEASE VERSION string
*
* The Release Version string should identify the next planned release.
* When a branch is made in preparation for a release, the release manager
* should change/confirm that the branch version of this file contains the
* string matching the desired version for the release. The trunk version of
* the file should always contain a trailing 'X'. This will make sure that a
* development build from trunk will not be confused for a released version.
* The release manager will need to remove the trailing 'X' and update the
* version string as appropriate for the release. The trunk copy of this file
* should also be updated/incremented for the next expected version, + trailing 'X'
****************************************************************************/
// This is the delivery package title, "DanNiPI "
// This string MUST be exactly 8 characters long
#define AGESA_PACKAGE_STRING {'D', 'a', 'n', 'N', 'i', 'P', 'I', ' '}
// This is the release version number of the AGESA component
// This string MUST be exactly 12 characters long
#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '5', '.', '0', 'X', ' ', ' ', ' '}
// The DanNi solution is defined to be family 0x10 in the S1g4 and ASB2 sockets.
#define INSTALL_S1G4_SOCKET_SUPPORT TRUE
#define INSTALL_ASB2_SOCKET_SUPPORT TRUE
#define INSTALL_FAMILY_10_SUPPORT TRUE
#ifdef BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT
#if BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT == TRUE
#undef INSTALL_S1G4_SOCKET_SUPPORT
#define INSTALL_S1G4_SOCKET_SUPPORT FALSE
#endif
#endif
#ifdef BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT
#if BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT == TRUE
#undef INSTALL_ASB2_SOCKET_SUPPORT
#define INSTALL_ASB2_SOCKET_SUPPORT FALSE
#endif
#endif
// The following definitions specify the default values for various parameters in which there are
// no clearly defined defaults to be used in the common file. The values below are based on product
// and BKDG content, please consult the AGESA Memory team for consultation.
#define DFLT_SCRUB_DRAM_RATE (0)
#define DFLT_SCRUB_L2_RATE (0x10)
#define DFLT_SCRUB_L3_RATE (0x10)
#define DFLT_SCRUB_IC_RATE (0)
#define DFLT_SCRUB_DC_RATE (0x12)
#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
#define DFLT_VRM_SLEW_RATE (5000)
// Instantiate all solution relevant data.
#include "PlatformInstall.h"

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build options for a Danube platform solution
*
* This file generates the defaults tables for the "Danube" platform solution
* set of processors. The documented build options are imported from a user
* controlled file for processing.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#include "cpuRegisters.h"
#include "cpuFamRegisters.h"
#include "cpuFamilyTranslation.h"
#include "AdvancedApi.h"
#include "heapManager.h"
#include "CreateStruct.h"
#include "cpuFeatures.h"
#include "Table.h"
#include "CommonReturns.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "GnbInterfaceStub.h"
/*****************************************************************************
* Define the RELEASE VERSION string
*
* The Release Version string should identify the next planned release.
* When a branch is made in preparation for a release, the release manager
* should change/confirm that the branch version of this file contains the
* string matching the desired version for the release. The trunk version of
* the file should always contain a trailing 'X'. This will make sure that a
* development build from trunk will not be confused for a released version.
* The release manager will need to remove the trailing 'X' and update the
* version string as appropriate for the release. The trunk copy of this file
* should also be updated/incremented for the next expected version, + trailing 'X'
****************************************************************************/
// This is the delivery package title, "DanNiPI "
// This string MUST be exactly 8 characters long
#define AGESA_PACKAGE_STRING {'D', 'a', 'n', 'N', 'i', 'P', 'I', ' '}
// This is the release version number of the AGESA component
// This string MUST be exactly 12 characters long
#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '5', '.', '0', 'X', ' ', ' ', ' '}
// The Danube solution is defined to be family 0x10 in the S1g4 socket.
#define INSTALL_S1G4_SOCKET_SUPPORT TRUE
#define INSTALL_FAMILY_10_SUPPORT TRUE
// The following definitions specify the default values for various parameters in which there are
// no clearly defined defaults to be used in the common file. The values below are based on product
// and BKDG content, please consult the AGESA Memory team for consultation.
#define DFLT_SCRUB_DRAM_RATE (0)
#define DFLT_SCRUB_L2_RATE (0x10)
#define DFLT_SCRUB_L3_RATE (0)
#define DFLT_SCRUB_IC_RATE (0)
#define DFLT_SCRUB_DC_RATE (0x12)
#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
#define DFLT_VRM_SLEW_RATE (5000)
// Instantiate all solution relevant data.
#include "PlatformInstall.h"

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build options for a Deccan platform solution
*
* This file generates the defaults tables for the "Deccan" platform solution
* set of processors. The documented build options are imported from a user
* controlled file for processing.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 35276 $ @e \$Date: 2010-07-19 10:47:05 -0700 (Mon, 19 Jul 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#include "cpuRegisters.h"
#include "cpuFamRegisters.h"
#include "cpuFamilyTranslation.h"
#include "AdvancedApi.h"
#include "heapManager.h"
#include "CreateStruct.h"
#include "cpuFeatures.h"
#include "Table.h"
#include "CommonReturns.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "GnbInterface.h"
/*****************************************************************************
* Define the RELEASE VERSION string
*
* The Release Version string should identify the next planned release.
* When a branch is made in preparation for a release, the release manager
* should change/confirm that the branch version of this file contains the
* string matching the desired version for the release. The trunk version of
* the file should always contain a trailing 'X'. This will make sure that a
* development build from trunk will not be confused for a released version.
* The release manager will need to remove the trailing 'X' and update the
* version string as appropriate for the release. The trunk copy of this file
* should also be updated/incremented for the next expected version, + trailing 'X'
****************************************************************************/
// This is the delivery package title, "KrishaPI"
// This string MUST be exactly 8 characters long
#define AGESA_PACKAGE_STRING {'K', 'r', 'i', 's', 'h', 'a', 'P', 'I'}
// This is the release version number of the AGESA component
// This string MUST be exactly 12 characters long
#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '3', '.', '0', 'X', ' ', ' ', ' '}
// The Deccan solution is defined to be family 0x14, models 10h-1fh in the FT2 socket.
#define INSTALL_FT2_SOCKET_SUPPORT TRUE
#define INSTALL_FAMILY_14_SUPPORT TRUE
// The following definitions specify the default values for various parameters in which there are
// no clearly defined defaults to be used in the common file. The values below are based on product
// and BKDG content, please consult the AGESA Memory team for consultation.
#define DFLT_SCRUB_DRAM_RATE (0)
#define DFLT_SCRUB_L2_RATE (0)
#define DFLT_SCRUB_L3_RATE (0)
#define DFLT_SCRUB_IC_RATE (0)
#define DFLT_SCRUB_DC_RATE (0)
#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
#define DFLT_VRM_SLEW_RATE (5000)
#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x420
#define DFLT_SPI_BASE_ADDRESS 0xFEC10000
#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC00000
#define DFLT_HPET_BASE_ADDRESS 0xFED00000
#define DFLT_SMI_CMD_PORT 0xB0
#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
#define DFLT_GEC_BASE_ADDRESS 0xFED61000
#define DFLT_AZALIA_SSID 0x780D1022
#define DFLT_SMBUS_SSID 0x780B1022
#define DFLT_IDE_SSID 0x780C1022
#define DFLT_SATA_AHCI_SSID 0x78011022
#define DFLT_SATA_IDE_SSID 0x78001022
#define DFLT_SATA_RAID5_SSID 0x78031022
#define DFLT_SATA_RAID_SSID 0x78021022
#define DFLT_EHCI_SSID 0x78081022
#define DFLT_OHCI_SSID 0x78071022
#define DFLT_LPC_SSID 0x780E1022
#define DFLT_FCH_GPP_LINK_CONFIG PortA4
#define DFLT_FCH_GPP_PORT0_PRESENT FALSE
#define DFLT_FCH_GPP_PORT1_PRESENT FALSE
#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
// Instantiate all solution relevant data.
#include "PlatformInstall.h"

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build options for a DevTest platform solution
*
* This file generates the defaults tables for the "DevTest" platform solution
* set of processors. The documented build options are imported from a user
* controlled file for processing.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 49633 $ @e \$Date: 2011-03-26 06:52:29 +0800 (Sat, 26 Mar 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#include "cpuRegisters.h"
#include "cpuFamRegisters.h"
#include "cpuFamilyTranslation.h"
#include "AdvancedApi.h"
#include "heapManager.h"
#include "CreateStruct.h"
#include "cpuFeatures.h"
#include "Table.h"
#include "CommonReturns.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "GnbInterfaceStub.h"
/*****************************************************************************
* Define the RELEASE VERSION string
*
* The Release Version string should identify the next planned release.
* When a branch is made in preparation for a release, the release manager
* should change/confirm that the branch version of this file contains the
* string matching the desired version for the release. The trunk version of
* the file should always contain a trailing 'X'. This will make sure that a
* development build from trunk will not be confused for a released version.
* The release manager will need to remove the trailing 'X' and update the
* version string as appropriate for the release. The trunk copy of this file
* should also be updated/incremented for the next expected version, + trailing 'X'
****************************************************************************/
// This is the delivery package title, "DevTest "
// This string MUST be exactly 8 characters long
#define AGESA_PACKAGE_STRING {'D', 'e', 'v', 'T', 'e', 's', 't', ' '}
// This is the release version number of the AGESA component
// This string MUST be exactly 12 characters long
#define AGESA_VERSION_STRING {'V', '0', '.', '1', '.', '2', '.', '3', 'X', ' ', ' ', ' '}
// The DevTest solution is defined to be everything that AGESA supports.
#define INSTALL_C32_SOCKET_SUPPORT TRUE
#define INSTALL_G34_SOCKET_SUPPORT TRUE
#define INSTALL_S1G4_SOCKET_SUPPORT TRUE
#define INSTALL_ASB2_SOCKET_SUPPORT TRUE
#define INSTALL_AM3_SOCKET_SUPPORT TRUE
#define INSTALL_FS1_SOCKET_SUPPORT TRUE
#define INSTALL_FM1_SOCKET_SUPPORT TRUE
#define INSTALL_FM2_SOCKET_SUPPORT TRUE
#define INSTALL_FT1_SOCKET_SUPPORT TRUE
#define INSTALL_FT2_SOCKET_SUPPORT TRUE
#define INSTALL_FP2_SOCKET_SUPPORT TRUE
#define INSTALL_FAMILY_10_SUPPORT TRUE
#define INSTALL_FAMILY_12_SUPPORT TRUE
#define INSTALL_FAMILY_14_SUPPORT TRUE
#define INSTALL_FAMILY_15_SUPPORT TRUE
// The following definitions specify the default values for various parameters in which there are
// no clearly defined defaults to be used in the common file. The values below are based on product
// and BKDG content, please consult the AGESA Memory team for consultation.
#define DFLT_SCRUB_DRAM_RATE (0xFF)
#define DFLT_SCRUB_L2_RATE (0x10)
#define DFLT_SCRUB_L3_RATE (0x10)
#define DFLT_SCRUB_IC_RATE (0)
#define DFLT_SCRUB_DC_RATE (0x12)
#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
#define DFLT_VRM_SLEW_RATE (2500)
#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x420
#define DFLT_SPI_BASE_ADDRESS 0xFEC10000
#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC00000
#define DFLT_HPET_BASE_ADDRESS 0xFED00000
#define DFLT_SMI_CMD_PORT 0xB0
#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
#define DFLT_GEC_BASE_ADDRESS 0xFED61000
#define DFLT_AZALIA_SSID 0x780D1022
#define DFLT_SMBUS_SSID 0x780B1022
#define DFLT_IDE_SSID 0x780C1022
#define DFLT_SATA_AHCI_SSID 0x78011022
#define DFLT_SATA_IDE_SSID 0x78001022
#define DFLT_SATA_RAID5_SSID 0x78031022
#define DFLT_SATA_RAID_SSID 0x78021022
#define DFLT_EHCI_SSID 0x78081022
#define DFLT_OHCI_SSID 0x78071022
#define DFLT_LPC_SSID 0x780E1022
#define DFLT_FCH_GPP_LINK_CONFIG PortA4
#define DFLT_FCH_GPP_PORT0_PRESENT FALSE
#define DFLT_FCH_GPP_PORT1_PRESENT FALSE
#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
// Instantiate all solution relevant data.
#include "PlatformInstall.h"

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build options for a Dragon platform solution
*
* This file generates the defaults tables for the "Dragon" platform solution
* set of processors. The documented build options are imported from a user
* controlled file for processing.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#include "cpuRegisters.h"
#include "cpuFamRegisters.h"
#include "cpuFamilyTranslation.h"
#include "AdvancedApi.h"
#include "heapManager.h"
#include "CreateStruct.h"
#include "cpuFeatures.h"
#include "Table.h"
#include "CommonReturns.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "GnbInterfaceStub.h"
/*****************************************************************************
* Define the RELEASE VERSION string
*
* The Release Version string should identify the next planned release.
* When a branch is made in preparation for a release, the release manager
* should change/confirm that the branch version of this file contains the
* string matching the desired version for the release. The trunk version of
* the file should always contain a trailing 'X'. This will make sure that a
* development build from trunk will not be confused for a released version.
* The release manager will need to remove the trailing 'X' and update the
* version string as appropriate for the release. The trunk copy of this file
* should also be updated/incremented for the next expected version, + trailing 'X'
****************************************************************************/
// This is the delivery package title, "DragonPI"
// This string MUST be exactly 8 characters long
#define AGESA_PACKAGE_STRING {'D', 'r', 'a', 'g', 'o', 'n', 'P', 'I'}
// This is the release version number of the AGESA component
// This string MUST be exactly 12 characters long
#define AGESA_VERSION_STRING {'V', '0', '.', '1', '.', '2', '.', '3', 'X', ' ', ' ', ' '}
// The Danube solution is defined to be family 0x10 in the AM3 socket.
#define INSTALL_AM3_SOCKET_SUPPORT TRUE
#define INSTALL_FAMILY_10_SUPPORT TRUE
// The following definitions specify the default values for various parameters in which there are
// no clearly defined defaults to be used in the common file. The values below are based on product
// and BKDG content, please consult the AGESA Memory team for consultation.
#define DFLT_SCRUB_DRAM_RATE (0)
#define DFLT_SCRUB_L2_RATE (0)
#define DFLT_SCRUB_L3_RATE (0)
#define DFLT_SCRUB_IC_RATE (0)
#define DFLT_SCRUB_DC_RATE (0)
#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
#define DFLT_VRM_SLEW_RATE (2500)
// Instantiate all solution relevant data.
#include "PlatformInstall.h"

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/* $NoKeywords:$ */
/**
* @file
*
* General Services
*
* Provides Services similar to the external General Services API, except
* suited to use within AGESA components. Socket, Core and PCI identification.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Common
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _GENERAL_SERVICES_H_
#define _GENERAL_SERVICES_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
#define NUMBER_OF_EVENT_DATA_PARAMS 4
/**
* AMD Device id for MMIO check.
*/
#define AMD_DEV_VEN_ID 0x1022
#define AMD_DEV_VEN_ID_ADDRESS 0
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/**
* An AGESA Event Log entry.
*/
typedef struct {
AGESA_STATUS EventClass; ///< The severity of the event, its associated AGESA_STATUS.
UINT32 EventInfo; ///< Uniquely identifies the event.
UINT32 DataParam1; ///< Event specific additional data
UINT32 DataParam2; ///< Event specific additional data
UINT32 DataParam3; ///< Event specific additional data
UINT32 DataParam4; ///< Event specific additional data
} AGESA_EVENT;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
/**
* Get a specified Core's APIC ID.
*
* @param[in] StdHeader Header for library and services.
* @param[in] Socket The Core's Socket.
* @param[in] Core The Core id.
* @param[out] ApicAddress The Core's APIC ID.
* @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
*
* @retval TRUE The core is present, APIC Id valid
* @retval FALSE The core is not present, APIC Id not valid.
*/
BOOLEAN
GetApicId (
IN AMD_CONFIG_PARAMS *StdHeader,
IN UINT32 Socket,
IN UINT32 Core,
OUT UINT8 *ApicAddress,
OUT AGESA_STATUS *AgesaStatus
);
/**
* Get Processor Module's PCI Config Space address.
*
* @param[in] StdHeader Header for library and services.
* @param[in] Socket The Core's Socket.
* @param[in] Module The Module in that Processor
* @param[out] PciAddress The Processor's PCI Config Space address (Function 0, Register 0)
* @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
*
* @retval TRUE The core is present, PCI Address valid
* @retval FALSE The core is not present, PCI Address not valid.
*/
BOOLEAN
GetPciAddress (
IN AMD_CONFIG_PARAMS *StdHeader,
IN UINT32 Socket,
IN UINT32 Module,
OUT PCI_ADDR *PciAddress,
OUT AGESA_STATUS *AgesaStatus
);
/**
* "Who am I" for the current running core.
*
* @param[in] StdHeader Header for library and services.
* @param[out] Socket The current Core's Socket
* @param[out] Module The current Core's Processor Module
* @param[out] Core The current Core's core id.
* @param[out] AgesaStatus Aggregates AGESA_STATUS for external interface, Always Succeeds.
*
*/
VOID
IdentifyCore (
IN AMD_CONFIG_PARAMS *StdHeader,
OUT UINT32 *Socket,
OUT UINT32 *Module,
OUT UINT32 *Core,
OUT AGESA_STATUS *AgesaStatus
);
/**
* A boolean function determine executed CPU is BSP core.
*/
BOOLEAN
IsBsp (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
OUT AGESA_STATUS *AgesaStatus
);
/**
* This function logs AGESA events into the event log.
*/
VOID
PutEventLog (
IN AGESA_STATUS EventClass,
IN UINT32 EventInfo,
IN UINT32 DataParam1,
IN UINT32 DataParam2,
IN UINT32 DataParam3,
IN UINT32 DataParam4,
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function gets event logs from the circular buffer.
*/
AGESA_STATUS
GetEventLog (
OUT AGESA_EVENT *EventRecord,
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function gets event logs from the circular buffer without flushing the entry.
*/
BOOLEAN
PeekEventLog (
OUT AGESA_EVENT *EventRecord,
IN UINT16 Index,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*---------------------------------------------------------------------------------------*/
/**
* This routine programs the registers necessary to get the PCI MMIO mechanism
* up and functioning.
*/
VOID
InitializePciMmio (
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _GENERAL_SERVICES_H_

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/* $NoKeywords:$ */
/**
* @file
*
* GNB API definition.
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ***************************************************************************
*
*/
#ifndef _GNBINTERFACE_H_
#define _GNBINTERFACE_H_
AGESA_STATUS
GnbInitAtReset (
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
GnbInitAtEarly (
IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr
);
AGESA_STATUS
GnbInitAtPost (
IN OUT AMD_POST_PARAMS *PostParamsPtr
);
VOID
GnbInitDataStructAtEnvDef (
IN OUT GNB_ENV_CONFIGURATION *GnbEnvConfigPtr,
IN AMD_ENV_PARAMS *EnvParamsPtr
);
AGESA_STATUS
GnbInitAtEnv (
IN AMD_ENV_PARAMS *EnvParamsPtr
);
AGESA_STATUS
GnbInitAtMid (
IN OUT AMD_MID_PARAMS *MidParamsPtr
);
AGESA_STATUS
GnbInitAtLate (
IN OUT AMD_LATE_PARAMS *LateParamsPtr
);
AGESA_STATUS
GnbInitAtPostAfterDram (
IN OUT AMD_POST_PARAMS *PostParamsPtr
);
AGESA_STATUS
AmdGnbRecovery (
IN AMD_CONFIG_PARAMS *StdHeader
);
AGESA_STATUS
GnbInitAtEarlier (
IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr
);
#endif

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/* $NoKeywords:$ */
/**
* @file
*
*
*
*
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: GNB
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ***************************************************************************
*
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Reset Stub
*
*
*
* @param[in] StdHeader Standard configuration header
* @retval AGESA_SUCCESS Always succeeds
*/
AGESA_STATUS
GnbInitAtReset (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Early Stub
*
*
*
* @param[in,out] EarlyParamsPtr Pointer to early configuration params.
* @retval AGESA_SUCCESS Always succeeds
*/
AGESA_STATUS
GnbInitAtEarly (
IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* Default constructor of GNB configuration at Env
*
*
*
* @param[in] GnbEnvConfigPtr Pointer to gnb env configuration params.
* @param[in] EnvParamsPtr Pointer to env configuration params.
*/
VOID
GnbInitDataStructAtEnvDef (
IN OUT GNB_ENV_CONFIGURATION *GnbEnvConfigPtr,
IN AMD_ENV_PARAMS *EnvParamsPtr
)
{
}
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Env
*
*
*
* @param[in] EnvParamsPtr Pointer to env configuration params.
* @retval AGESA_SUCCESS Always succeeds
*/
AGESA_STATUS
GnbInitAtEnv (
IN AMD_ENV_PARAMS *EnvParamsPtr
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Post
*
*
*
* @param[in,out] PostParamsPtr Pointer to Post configuration params.
* @retval AGESA_SUCCESS Always succeeds
*/
AGESA_STATUS
GnbInitAtPost (
IN OUT AMD_POST_PARAMS *PostParamsPtr
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Mid post
*
*
*
* @param[in,out] MidParamsPtr Pointer to mid configuration params.
* @retval AGESA_SUCCESS Always succeeds
*/
AGESA_STATUS
GnbInitAtMid (
IN OUT AMD_MID_PARAMS *MidParamsPtr
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Late post
*
*
*
* @param[in,out] LateParamsPtr Pointer to late configuration params.
* @retval AGESA_SUCCESS Always succeeds
*/
AGESA_STATUS
GnbInitAtLate (
IN OUT AMD_LATE_PARAMS *LateParamsPtr
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* AmdGnbRecovery
*
*
*
* @param[in] StdHeader Standard configuration header
* @retval AGESA_SUCCESS Always succeeds
*/
AGESA_STATUS
AmdGnbRecovery (
IN AMD_CONFIG_PARAMS *StdHeader
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Post after DRAM init
*
*
*
* @param[in] PostParamsPtr Pointer to post configuration parameters
* @retval AGESA_SUCCESS Always succeeds
*/
AGESA_STATUS
GnbInitAtPostAfterDram (
IN OUT AMD_POST_PARAMS *PostParamsPtr
)
{
return AGESA_SUCCESS;
}
/*----------------------------------------------------------------------------------------*/
/**
* Init GNB at Early Before CPU Stub
*
*
*
* @param[in,out] EarlyParamsPtr Pointer to early configuration params.
* @retval AGESA_SUCCESS Always succeeds
*/
AGESA_STATUS
GnbInitAtEarlier (
IN OUT AMD_EARLY_PARAMS *EarlyParamsPtr
)
{
return AGESA_SUCCESS;
}

960
src/vendorcode/amd/agesa/f12/Include/Ids.h Executable file
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@ -0,0 +1,960 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD IDS Routines
*
* Contains AMD AGESA Integrated Debug Macros
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: IDS
* @e \$Revision: 49994 $ @e \$Date: 2011-03-31 15:44:04 +0800 (Thu, 31 Mar 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
/* Macros to aid debugging */
/* These definitions expand to zero (0) bytes of code when disabled */
#ifndef _IDS_H_
#define _IDS_H_
#undef FALSE
#undef TRUE
#define FALSE 0
#define TRUE 1
// Proto type for optionsids.h
typedef UINT32 IDS_STATUS; ///< Status of IDS function.
#define IDS_SUCCESS ((IDS_STATUS) 0x00000000) ///< IDS Function is Successful.
#define IDS_UNSUPPORTED ((IDS_STATUS) 0xFFFFFFFF) ///< IDS Function is not existed.
#define IDS_STRINGIZE(a) #a ///< for define stringize macro
/**
* IDS Option Hook Points
*
* These are the values to indicate hook point in AGESA for IDS Options.
*
*/
typedef enum { //vv- for debug reference only
IDS_INIT_EARLY_BEFORE, ///< 00 Option Hook Point before AGESA function AMD_INIT_EARLY.
///< IDS Object is initialized.
///< Override CPU Core Leveling Mode.
///< Set P-State in Post
IDS_INIT_EARLY_AFTER, ///< 01 Option Hook Point after AGESA function AMD_INIT_EARLY.
IDS_INIT_LATE_BEFORE, ///< 02 Option Hook Point before AGESA function AMD_INIT_LATE.
///< It will be used to control the following tables.
///< ACPI P-State Table (_PSS, XPSS, _PCT, _PSD, _PPC)
///< ACPI SRAT Table
///< ACPI SLIT Table
///< ACPI WHEA Table
///< DMI Table
IDS_INIT_LATE_AFTER, ///< 03 Option Hook Point after AGESA function AMD_INIT_LATE.
IDS_INIT_MID_BEFORE, ///< 04 Option Hook Point before AGESA function AMD_INIT_MID.
IDS_INIT_MID_AFTER, ///< 05 Option Hook Point after AGESA function AMD_INIT_MID.
IDS_INIT_POST_BEFORE, ///< 06 Option Hook Point before AGESA function AMD_INIT_POST.
///< Control Interleaving and DRAM memory hole
///< Override the setting of ECC Control
///< Override the setting of Online Spare Rank
IDS_INIT_POST_AFTER, ///< 07 Option Hook Point after AGESA function AMD_INIT_POST.
IDS_INIT_RESET_BEFORE, ///< 08 Option Hook Point before AGESA function AMD_INIT_RESET.
IDS_INIT_RESET_AFTER, ///< 09 Option Hook Point after AGESA function AMD_INIT_RESET.
IDS_INIT_POST_MID, ///< 0a Option Hook Point after AGESA function AMD_INIT_POST.
IDS_BEFORE_S3_SAVE, ///< 0b override any settings before S3 save.
IDS_BEFORE_S3_RESTORE, ///< 0c override any settings before S3 restore
IDS_AFTER_S3_SAVE, ///< 0d Override any settings after S3 save
IDS_AFTER_S3_RESTORE, ///< 0e Override any settings after S3 restore
IDS_BEFORE_DQS_TRAINING, ///< 0f override any settings before DQS training
IDS_BEFORE_DRAM_INIT, ///< 10 override any settings before Dram initialization
IDS_BEFORE_MEM_FREQ_CHG, ///< 11 override settings before MemClk frequency change
IDS_BEFORE_WARM_RESET , ///< 12 Override PCI or MSR Registers Before Warm Reset
IDS_BEFORE_MEM_INIT, ///< 13 Override PCI or MSR Registers Before Memory Init
IDS_BEFORE_PCI_INIT, ///< 14 Override PCI or MSR Registers Before PCI Init
IDS_BEFORE_OS, ///< 15 Override PCI or MSR Registers Before booting to OS
IDS_UCODE, ///< 16 Enable or Disable microcode patching
IDS_BEFORE_AP_EARLY_HALT, ///< 17 Option Hook Point before AP early halt
IDS_BEFORE_S3_RESUME, ///< 18 Option Hook Point before s3 resume
IDS_AFTER_S3_RESUME, ///< 19 Option Hook Point after s3 resume
IDS_BEFORE_PM_INIT, ///< 20 Option Hook Point Before Pm Init
IDS_PLATFORM_RSVD1 = 0x38, ///< from 0x38 to 0x3f will reserved for platform used
IDS_PLATFORM_RSVD2 = 0x39, ///< from 0x38 to 0x3f will reserved for platform used
IDS_PLATFORM_RSVD3 = 0x3a, ///< from 0x38 to 0x3f will reserved for platform used
IDS_PLATFORM_RSVD4 = 0x3b, ///< from 0x38 to 0x3f will reserved for platform used
IDS_PLATFORM_RSVD5 = 0x3c, ///< from 0x38 to 0x3f will reserved for platform used
IDS_PLATFORM_RSVD6 = 0x3d, ///< from 0x38 to 0x3f will reserved for platform used
IDS_PLATFORM_RSVD7 = 0x3e, ///< from 0x38 to 0x3f will reserved for platform used
IDS_PLATFORM_RSVD8 = 0x3f, ///< from 0x38 to 0x3f will reserved for platform used
// All the above timing point is used by BVM, their value should never be changed
IDS_HT_CONTROL, ///< 40 Override the setting of HT Link Control
IDS_HT_TRISTATE, ///< 41 Enable or Disable HT Tri-state during an LDTSTP#
IDS_INIT_DRAM_TABLE, ///< 42 Generate override table for Dram Timing
///< Dram Controller, Drive Strength and DQS Timing
IDS_GET_DRAM_TABLE, ///< 43 Generate override table for Dram Timing
IDS_GANGING_MODE, ///< 44 override Memory Mode Unganged
IDS_POWERDOWN_MODE, ///< 45 override Power Down Mode
IDS_BURST_LENGTH32, ///< 46 override Burst Length32
IDS_ALL_MEMORY_CLOCK, ///< 47 override All Memory Clks Enable
IDS_ECC, ///< 48 override ECC parameter
IDS_ECCSYMBOLSIZE, ///< 49 override ECC symbol size
IDS_CPU_Early_Override, ///< 4a override CPU early parameter
IDS_CACHE_FLUSH_HLT, ///< 4b override Cache Flush Hlt
IDS_CHANNEL_INTERLEAVE, ///< 4c override Channel Interleave
IDS_MEM_ERROR_RECOVERY, ///< 4d override memory error recovery
IDS_MEM_RETRAIN_TIMES, ///< 4e override memory retrain times
IDS_MEM_SIZE_OVERLAY, ///< 4f Override the syslimit
IDS_HT_ASSIST, ///< 50 Override Probe Filter
IDS_CHECK_NEGATIVE_WL, ///< 51 Check for negative write leveling result
IDS_DLL_SHUT_DOWN, ///< 52 Check for Dll Shut Down
IDS_POR_MEM_FREQ, ///< 53 Entry to enable/disable MemClk frequency enforcement
IDS_PHY_DLL_STANDBY_CTRL, ///< 54 Enable/Disable Phy DLL standby feature
IDS_PLATFORMCFG_OVERRIDE, ///< 55 Hook for Override PlatformConfig structure
IDS_LOADCARD_ERROR_RECOVERY, ///< 56 Special error handling for load card support
IDS_MEM_IGNORE_ERROR, ///< 57 Ignore error and do not do fatal exit in memory
IDS_GNB_SMU_SERVICE_CONFIG, ///< 58 Config GNB SMU service
IDS_GNB_ORBDYNAMIC_WAKE, ///< 59 config GNB dynamic wake
IDS_GNB_PLATFORMCFG_OVERRIDE, ///< 5a override ids gnb platform config
IDS_GNB_LCLK_DPM_EN, ///< 5b override GNB LCLK DPM configuration
IDS_GNB_LCLK_DEEP_SLEEP, ///< 5c override GNB LCLK DPM deep sleep
IDS_GNB_CLOCK_GATING, ///< 5d Override GNB Clock gating config
IDS_NB_PSTATE_DIDVID, ///< 5e Override NB P-state settings
IDS_CPB_CTRL, ///< 5f Config the Core peformance boost feature
IDS_HTC_CTRL, ///< 60 Hook for Hardware Thermal Control
IDS_CC6_WORKAROUND, ///< 61 Hook for skip CC6 work around
IDS_MEM_MR0, ///< 62 Hook for override Memory Mr0 register
IDS_REG_TABLE, ///< 63 Hook for add IDS register table to the loop
IDS_NBBUFFERALLOCATIONATEARLY, ///< 64 Hook for override North bridge bufer allocation
IDS_BEFORE_S3_SPECIAL, ///< 65 Hook to bypass S3 special functions
IDS_SET_PCI_REGISTER_ENTRY, ///< 66 Hook to SetRegisterForPciEntry
IDS_ERRATUM463_WORKAROUND, ///< 67 Hook to Erratum 463 workaround
IDS_BEFORE_MEMCLR, ///< 68 Hook before set Memclr bit
IDS_OVERRIDE_IO_CSTATE, ///< 69 Hook for override io C-state setting
IDS_NBPSDIS_OVERRIDE, ///< 6a Hook for override NB pstate disable setting
IDS_NBPS_REG_OVERRIDE, ///< 6b Hook for override Memory NBps reg
IDS_LOW_POWER_PSTATE, ///< 6c Hook for disalbe Low power_Pstates feature
IDS_CST_CREATE, ///< 6d Hook for create _CST
IDS_CST_SIZE, ///< 6e Hook for get _CST size
IDS_ENFORCE_VDDIO, ///< 6f Hook to override VDDIO
IDS_SKIP_PERFORMANCE_OPT, ///< 70 Hook to skip performance optimization
IDS_INIT_MEM_REG_TABLE, ///< 71 Hook for init memory register table
IDS_SKIP_FUSED_MAX_RATE, ///< 72 Hook to skip fused max rate cap
IDS_FCH_INIT_AT_RESET, ///< 73 Hook for FCH reset parameter
IDS_FCH_INIT_AT_ENV, ///< 74 Hook for FCH ENV parameter
IDS_ENFORCE_PLAT_TABLES, ///< 75 Hook to enforce platform specific tables
IDS_NBPS_MIN_FREQ, ///< 76 Hook for override MIN nb ps freq
IDS_GNB_FORCE_CABLESAFE, ///< 77 Hook for override Force Cable Safe
IDS_SKIP_PM_TRANSITION_STEP, ///< 78 Hook for provide IDS ability to skip this PM step
IDS_GNB_PROPERTY, ///< 79 Hook for GNB Property
IDS_GNB_PCIE_POWER_GATING, ///< 7A Hook for GNB PCIe Power Gating
IDS_MEM_DYN_DRAM_TERM, ///< 7B Hook for Override Dynamic Dram Term
IDS_MEM_DRAM_TERM, ///< 7C Hook for Override Dram Term
IDS_TRACE_MODE, ///< 7D Trace Mode
IDS_GNB_ALTVDDNB, ///< 7E Hook for Override AltVddNB
} AGESA_IDS_OPTION;
#include "OptionsIds.h"
#include "Filecode.h"
/* Initialize IDS controls */
#ifndef IDSOPT_IDS_ENABLED
#define IDSOPT_IDS_ENABLED FALSE
#endif
#ifndef IDSOPT_CONTROL_ENABLED
#define IDSOPT_CONTROL_ENABLED FALSE
#endif
#ifndef IDSOPT_CONTROL_NV_TO_CMOS
#define IDSOPT_CONTROL_NV_TO_CMOS FALSE
#endif
#ifndef IDSOPT_TRACING_ENABLED
#define IDSOPT_TRACING_ENABLED FALSE
#endif
#ifndef IDSOPT_TRACE_USER_OPTIONS
#define IDSOPT_TRACE_USER_OPTIONS TRUE
#endif
#ifndef IDSOPT_PERF_ANALYSIS
#define IDSOPT_PERF_ANALYSIS FALSE
#endif
#ifndef IDSOPT_HEAP_CHECKING
#define IDSOPT_HEAP_CHECKING FALSE
#endif
#ifndef IDSOPT_ASSERT_ENABLED
#define IDSOPT_ASSERT_ENABLED FALSE
#endif
#ifndef IDSOPT_ERROR_TRAP_ENABLED
#define IDSOPT_ERROR_TRAP_ENABLED FALSE
#endif
#ifndef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
#define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE
#endif
#ifndef IDSOPT_DEBUG_CODE_ENABLED
#define IDSOPT_DEBUG_CODE_ENABLED FALSE
#endif
#ifndef IDSOPT_IDT_EXCEPTION_TRAP
#define IDSOPT_IDT_EXCEPTION_TRAP FALSE
#endif
#ifndef IDSOPT_C_OPTIMIZATION_DISABLED
#define IDSOPT_C_OPTIMIZATION_DISABLED FALSE
#endif
#if IDSOPT_IDS_ENABLED == FALSE
#undef IDSOPT_CONTROL_ENABLED
#undef IDSOPT_TRACING_ENABLED
#undef IDSOPT_PERF_ANALYSIS
#undef IDSOPT_HEAP_CHECKING
#undef IDSOPT_ASSERT_ENABLED
#undef IDSOPT_ERROR_TRAP_ENABLED
#undef IDSOPT_CAR_CORRUPTION_CHECK_ENABLED
#undef IDSOPT_DEBUG_CODE_ENABLED
#undef IDSOPT_TRACE_USER_OPTIONS
#define IDSOPT_CONTROL_ENABLED FALSE
#define IDSOPT_TRACING_ENABLED FALSE
#define IDSOPT_PERF_ANALYSIS FALSE
#define IDSOPT_HEAP_CHECKING FALSE
#define IDSOPT_ASSERT_ENABLED FALSE
#define IDSOPT_ERROR_TRAP_ENABLED FALSE
#define IDSOPT_CAR_CORRUPTION_CHECK_ENABLED FALSE
#define IDSOPT_DEBUG_CODE_ENABLED FALSE
#define IDSOPT_TRACE_USER_OPTIONS FALSE
#endif
/**
* Make a Progress Report to the User.
*
* This Macro is always enabled. The default action is to write the TestPoint value
* to an I/O port. The I/O port is 8 bits in size and the default address is 0x80.
* IBVs can change AGESA's default port by defining IDS_DEBUG_PORT to desired port
* in OptionsIds.h in their build tip.
*
* @param[in] TestPoint The value for display indicating progress
* @param[in,out] StdHeader Pointer of AMD_CONFIG_PARAMS
*
**/
#define AGESA_TESTPOINT(TestPoint, StdHeader)
#ifndef IDS_DEBUG_PORT
#define IDS_DEBUG_PORT 0x80
#endif
/**
* @def STOP_HERE
* (macro) - Causes program to halt. This is @b only for use during active debugging .
*
* Causes the program to halt and display the file number of the source of the
* halt (displayed in decimal).
*
**/
#if IDSOPT_IDS_ENABLED == TRUE
#ifdef STOP_CODE
#undef STOP_CODE
#endif
#define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
(((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
#define STOP_HERE
#else
#define STOP_HERE
#endif
/**
* @def ASSERT
* Test an assertion that the given statement is True.
*
* The statement is evaluated to a boolean value. If the statement is True,
* then no action is taken (no error). If the statement is False, a error stop
* is generated to halt the program. Used for testing for fatal errors that
* must be resolved before production. This is used to do parameter checks,
* bounds checking, range checks and 'sanity' checks.
*
* @param[in] conditional Assert that evaluating this conditional results in TRUE.
*
**/
#ifndef ASSERT
#if IDSOPT_ASSERT_ENABLED == TRUE
#ifdef STOP_CODE
#undef STOP_CODE
#endif
#define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
(((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
#define ASSERT(conditional)
#else
#define ASSERT(conditional)
#endif
#endif
#if IDSOPT_CAR_CORRUPTION_CHECK_ENABLED == TRUE
#undef IDSOPT_ERROR_TRAP_ENABLED
#define IDSOPT_ERROR_TRAP_ENABLED TRUE
#define IDS_CAR_CORRUPTION_CHECK(StdHeader)
#else
#define IDS_CAR_CORRUPTION_CHECK(StdHeader)
#endif
/**
* @def DEBUG_CODE
* Make the code active when IDSOPT_DEBUG_CODE_ENABLED enable
*
*/
#ifndef DEBUG_CODE
#if IDSOPT_DEBUG_CODE_ENABLED == TRUE
#define DEBUG_CODE(Code)
#else
#define DEBUG_CODE(Code)
#endif
#endif
/**
* @def IDS_ERROR_TRAP
* Trap AGESA Error events with stop code display.
*
* Works similarly to use of "ASSERT (FALSE);"
*
*/
#if IDSOPT_ERROR_TRAP_ENABLED == TRUE
#ifdef STOP_CODE
#undef STOP_CODE
#endif
#define STOP_CODE (((UINT32)FILECODE)*0x10000 + \
((__LINE__) % 10) + (((__LINE__ / 10) % 10)*0x10) + \
(((__LINE__ / 100) % 10)*0x100) + (((__LINE__ / 1000) % 10)*0x1000))
#define IDS_ERROR_TRAP
#else
#define IDS_ERROR_TRAP
#endif
///give the extended Macro default value
#ifndef __IDS_EXTENDED__
#define IDS_EXTENDED_HOOK(idsoption, dataptr, idsnvptr, stdheader) IDS_SUCCESS
#define IDS_INITIAL_F10_PM_STEP
#define IDS_INITIAL_F12_PM_STEP
#define IDS_INITIAL_F14_PM_STEP
#define IDS_INITIAL_F15_PM_STEP
#define IDS_EXTENDED_GET_DATA_EARLY(data, StdHeader)
#define IDS_EXTENDED_GET_DATA_LATE(data, StdHeader)
#define IDS_EXTENDED_HEAP_SIZE 0
#define IDS_EXT_INCLUDE_F10(file)
#define IDS_EXT_INCLUDE_F12(file)
#define IDS_EXT_INCLUDE_F14(file)
#define IDS_EXT_INCLUDE_F15(file)
#define IDS_EXT_INCLUDE(file)
#endif
#ifndef IDS_NUM_NV_ITEM
#define IDS_NUM_NV_ITEM (IDS_NUM_EXT_NV_ITEM)
#endif
#if IDSOPT_CONTROL_ENABLED == TRUE
#define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader)
#define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader)
#else
#define IDS_OPTION_HOOK(IdsOption, DataPtr, StdHeader)
#define IDS_OPTION_CALLOUT(CallOutId, DataPtr, StdHeader)
#endif
/**
* Macro to add a *skip* hook for IDS options
*
* The default minimal action is to do nothing and there is no any code to increase.
* For debug environments, IDS dispatcher function will be called to perform
* the detailed action and to skip AGESA code if necessary.
*
* @param[in] IdsOption IDS Option ID for this hook point
* @param[in, out] DataPtr Data Pointer to override
* @param[in, out] StdHeader Pointer of AMD_CONFIG_PARAMS
*
*
**/
#if IDSOPT_CONTROL_ENABLED == TRUE
#define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader)
#else
#define IDS_SKIP_HOOK(IdsOption, DataPtr, StdHeader)
#endif
/**
* Macro to add a heap manager routine
*
* when memory is allocated the heap manager actually allocates two extra dwords of data,
* one dword buffer before the actual memory, and one dword afterwards.
* a complete heap walk and check to be performed at any time.
* it would ASSERT if the heap is corrupt
*
* @param[in] StdHeader Pointer of AMD_CONFIG_PARAMS
*
*
**/
// Heap debug feature
#define SENTINEL_BEFORE_VALUE 0x64616548 // "Head"
#define SENTINEL_AFTER_VALUE 0x6C696154 // "Tail"
#if IDSOPT_IDS_ENABLED == TRUE
#if IDSOPT_HEAP_CHECKING == TRUE
#define SIZE_OF_SENTINEL 0
#define NUM_OF_SENTINEL 0
#define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
#define SET_SENTINEL_AFTER(NodePtr)
#define Heap_Check(stdheader)
#else
#define SIZE_OF_SENTINEL 0
#define NUM_OF_SENTINEL 0
#define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
#define SET_SENTINEL_AFTER(NodePtr)
#define Heap_Check(stdheader)
#endif
#else
#define SIZE_OF_SENTINEL 0
#define NUM_OF_SENTINEL 0
#define SET_SENTINEL_BEFORE(NodePtr, AlignTo16Byte)
#define SET_SENTINEL_AFTER(NodePtr)
#define Heap_Check(stdheader)
#endif
//Note a is from 0 to 63
#define DEBUG_PRINT_SHIFT(a) ((UINT64)1 << a)
//If you change the Bitmap definition below, please change the Hash in ParseFilter of hdtout2008.pl accordingly
//Memory Masks
#define MEM_SETREG DEBUG_PRINT_SHIFT (0)
#define MEM_GETREG DEBUG_PRINT_SHIFT (1)
#define MEM_FLOW DEBUG_PRINT_SHIFT (2)
#define MEM_STATUS DEBUG_PRINT_SHIFT (3)
#define MEMORY_TRACE_RSV1 DEBUG_PRINT_SHIFT (4)
#define MEMORY_TRACE_RSV2 DEBUG_PRINT_SHIFT (5)
#define MEMORY_TRACE_RSV3 DEBUG_PRINT_SHIFT (6)
#define MEMORY_TRACE_RSV4 DEBUG_PRINT_SHIFT (7)
#define MEMORY_TRACE_RSV5 DEBUG_PRINT_SHIFT (8)
#define MEMORY_TRACE_RSV6 DEBUG_PRINT_SHIFT (9)
//CPU Masks
#define CPU_TRACE DEBUG_PRINT_SHIFT (10)
#define CPU_TRACE_RSV1 DEBUG_PRINT_SHIFT (11)
#define CPU_TRACE_RSV2 DEBUG_PRINT_SHIFT (12)
#define CPU_TRACE_RSV3 DEBUG_PRINT_SHIFT (13)
#define CPU_TRACE_RSV4 DEBUG_PRINT_SHIFT (14)
#define CPU_TRACE_RSV5 DEBUG_PRINT_SHIFT (15)
#define CPU_TRACE_RSV6 DEBUG_PRINT_SHIFT (16)
#define CPU_TRACE_RSV7 DEBUG_PRINT_SHIFT (17)
#define CPU_TRACE_RSV8 DEBUG_PRINT_SHIFT (18)
#define CPU_TRACE_RSV9 DEBUG_PRINT_SHIFT (19)
//GNB Masks
#define GNB_TRACE DEBUG_PRINT_SHIFT (20)
#define PCIE_MISC DEBUG_PRINT_SHIFT (21)
#define PCIE_PORTREG_TRACE DEBUG_PRINT_SHIFT (22)
#define PCIE_HOSTREG_TRACE DEBUG_PRINT_SHIFT (23)
#define GNB_TRACE_RSV2 DEBUG_PRINT_SHIFT (24)
#define NB_MISC DEBUG_PRINT_SHIFT (25)
#define GNB_TRACE_RSV3 DEBUG_PRINT_SHIFT (26)
#define GFX_MISC DEBUG_PRINT_SHIFT (27)
#define NB_SMUREG_TRACE DEBUG_PRINT_SHIFT (28)
#define GNB_TRACE_RSV1 DEBUG_PRINT_SHIFT (29)
//HT Masks
#define HT_TRACE DEBUG_PRINT_SHIFT (30)
#define HT_TRACE_RSV1 DEBUG_PRINT_SHIFT (31)
#define HT_TRACE_RSV2 DEBUG_PRINT_SHIFT (32)
#define HT_TRACE_RSV3 DEBUG_PRINT_SHIFT (33)
#define HT_TRACE_RSV4 DEBUG_PRINT_SHIFT (34)
#define HT_TRACE_RSV5 DEBUG_PRINT_SHIFT (35)
#define HT_TRACE_RSV6 DEBUG_PRINT_SHIFT (36)
#define HT_TRACE_RSV7 DEBUG_PRINT_SHIFT (37)
#define HT_TRACE_RSV8 DEBUG_PRINT_SHIFT (38)
#define HT_TRACE_RSV9 DEBUG_PRINT_SHIFT (39)
//FCH Masks
#define FCH_TRACE DEBUG_PRINT_SHIFT (40)
#define FCH_TRACE_RSV1 DEBUG_PRINT_SHIFT (41)
#define FCH_TRACE_RSV2 DEBUG_PRINT_SHIFT (42)
#define FCH_TRACE_RSV3 DEBUG_PRINT_SHIFT (43)
#define FCH_TRACE_RSV4 DEBUG_PRINT_SHIFT (44)
#define FCH_TRACE_RSV5 DEBUG_PRINT_SHIFT (45)
#define FCH_TRACE_RSV6 DEBUG_PRINT_SHIFT (46)
#define FCH_TRACE_RSV7 DEBUG_PRINT_SHIFT (47)
#define FCH_TRACE_RSV8 DEBUG_PRINT_SHIFT (48)
#define FCH_TRACE_RSV9 DEBUG_PRINT_SHIFT (49)
//Other Masks
#define MAIN_FLOW DEBUG_PRINT_SHIFT (50)
#define EVENT_LOG DEBUG_PRINT_SHIFT (51)
#define PERFORMANCE_ANALYSE DEBUG_PRINT_SHIFT (52)
//Ids Masks
#define IDS_TRACE DEBUG_PRINT_SHIFT (53)
#define IDS_REG DEBUG_PRINT_SHIFT (54)
#define IDS_TRACE_RSV2 DEBUG_PRINT_SHIFT (55)
#define IDS_TRACE_RSV3 DEBUG_PRINT_SHIFT (56)
//S3
#define S3_TRACE DEBUG_PRINT_SHIFT (57)
//Library function to read/write PCI/MSR registers
#define LIB_PCI_RD DEBUG_PRINT_SHIFT (58)
#define LIB_PCI_WR DEBUG_PRINT_SHIFT (59)
//Reserved
#define TRACE_RSV3 DEBUG_PRINT_SHIFT (60)
#define TRACE_RSV4 DEBUG_PRINT_SHIFT (61)
#define TRACE_RSV5 DEBUG_PRINT_SHIFT (62)
#define TRACE_RSV6 DEBUG_PRINT_SHIFT (63)
#define GNB_TRACE_DEFAULT 0
#define GNB_TRACE_REG 0
#define GNB_TRACE_ALL 0
#define CPU_TRACE_ALL 0
#define MEMORY_TRACE_ALL 0
#define HT_TRACE_ALL 0
#define FCH_TRACE_ALL 0
#define IDS_TRACE_ALL 0
#define OTHER_TRACE_ALL 0
#define TRACE_MASK_ALL (0ull)
#ifndef IDS_DEBUG_PRINT_MASK
#define IDS_DEBUG_PRINT_MASK 0
#endif
/**
* Macro to add HDT OUT
*
* The default minimal action is to do nothing and there is no any code to increase.
* For debug environments, the debug information can be displayed in HDT or other
* devices.
*
**/
#if IDSOPT_IDS_ENABLED == TRUE
#if IDSOPT_TRACING_ENABLED == TRUE
#define IDS_HDT_CONSOLE_INIT(x)
#define IDS_HDT_CONSOLE_EXIT(x)
#define IDS_HDT_CONSOLE_S3_EXIT(x)
#define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
#if IDSOPT_C_OPTIMIZATION_DISABLED == TRUE
#ifdef __GNUC__
#define IDS_HDT_CONSOLE(f, s, ...)
#else
#define IDS_HDT_CONSOLE(f, s, ...)
#endif
#else
#pragma warning(disable: 4127)
#ifdef __GNUC__
#define IDS_HDT_CONSOLE(f, s, ...)
#else
#define IDS_HDT_CONSOLE(f, s, ...)
#endif
#endif
#define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
#define IDS_HDT_CONSOLE_ASSERT(x)
#define IDS_FUNCLIST_ADDR NULL
#define IDS_FUNCLIST_EXTERN()
#define IDS_TIMEOUT_CTL(t)
#define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
#define CONSOLE(s, ...)
#else
#define IDS_HDT_CONSOLE_INIT(x)
#define IDS_HDT_CONSOLE_EXIT(x)
#define IDS_HDT_CONSOLE_S3_EXIT(x)
#define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
#define IDS_HDT_CONSOLE(f, s, ...)
#define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
#define IDS_HDT_CONSOLE_ASSERT(x)
#define IDS_FUNCLIST_ADDR NULL
#define IDS_FUNCLIST_EXTERN()
#define IDS_TIMEOUT_CTL(t)
#define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
#define CONSOLE(s, ...)
#endif
#else
#define IDS_HDT_CONSOLE_INIT(x)
#define IDS_HDT_CONSOLE_EXIT(x)
#define IDS_HDT_CONSOLE_S3_EXIT(x)
#define IDS_HDT_CONSOLE_S3_AP_EXIT(x)
#define IDS_HDT_CONSOLE(f, s, ...)
#define IDS_HDT_CONSOLE_FLUSH_BUFFER(x)
#define IDS_HDT_CONSOLE_ASSERT(x)
#define IDS_FUNCLIST_ADDR NULL
#define IDS_FUNCLIST_EXTERN()
#define IDS_TIMEOUT_CTL(t)
#define IDS_HDT_CONSOLE_DEBUG_CODE(Code)
#define CONSOLE(s, ...)
#endif
#define IDS_TRACE_SHOW_BLD_OPT_CFG IDSOPT_TRACE_USER_OPTIONS
#if IDSOPT_PERF_ANALYSIS == TRUE
#define IDS_PERF_TIMESTAMP(StdHeader, TestPoint)
#define IDS_PERF_ANALYSE(StdHeader)
#define IDS_PERF_TIME_MEASURE(StdHeader)
#else
#define IDS_PERF_TIMESTAMP(StdHeader, TestPoint)
#define IDS_PERF_ANALYSE(StdHeader)
#define IDS_PERF_TIME_MEASURE(StdHeader)
#endif
///For IDS feat use
#define IDS_FAMILY_ALL 0x0ull
#define IDS_BSP_ONLY TRUE
#define IDS_ALL_CORES FALSE
#define IDS_LATE_RUN_AP_TASK_ID PROC_IDS_CONTROL_IDSLIB_FILECODE
#define IDS_CALLOUT_INIT 0x00 ///< The function data of IDS callout function of initialization.
#define IDS_CALLOUT_GNB_PPFUSE_OVERRIDE 0x00 ///< The function data of IDS callout function of GNB pp fuse table.
#define IDS_CALLOUT_GNB_INTEGRATED_TABLE_CONFIG 0x00 ///< The function data of IDS callout function of GNB integrated table.
#define IDS_CALLOUT_GNB_NB_POWERGATE_CONFIG 0x00 ///< The function data of IDS callout function of GNB NB power gate config.
#define IDS_CALLOUT_GNB_PCIE_POWERGATE_CONFIG 0x00 ///< The function data of IDS callout function of GNB PCIE power gateconfig.
#define IDS_CALLOUT_GNB_PCIE_PLATFORM_CONFIG 0x00 ///< The function data of IDS callout function of GNB pcie platform config.
#define IDS_CALLOUT_GNB_PCIE_PHY_CONFIG 0x00 ///< The function data of IDS callout function of GNB pcie PHY config.
#define IDS_CALLOUT_GNB_GMM_REGISTER_OVERRIDE 0x00 ///< The function data of IDS callout function of GNB GMM register override
#define IDS_CALLOUT_MTC1E_PLATFORM_CONFIG 0x00 ///< The function data of IDS callout function of Message Triggered C1e platform config.
#define IDS_CALLOUT_FCH_INIT_RESET 0x00 ///< The function data of IDS callout function of FchInitReset
#define IDS_CALLOUT_FCH_INIT_ENV 0x00 ///< The function data of IDS callout function of FchInitEnv.
/// Function entry for HDT script to call
typedef struct _SCRIPT_FUNCTION {
UINT32 FuncAddr; ///< Function address in ROM
CHAR8 FuncName[40]; ///< Function name
} SCRIPT_FUNCTION;
/// Data Structure for Mem ECC parameter override
typedef struct {
IN BOOLEAN CfgEccRedirection; ///< ECC Redirection
IN UINT16 CfgScrubDramRate; ///< Scrub Dram Rate
IN UINT16 CfgScrubL2Rate; ///< Scrub L2Rate
IN UINT16 CfgScrubL3Rate; ///< Scrub L3Rate
IN UINT16 CfgScrubIcRate; ///< Scrub Ic Rate
IN UINT16 CfgScrubDcRate; ///< Scrub Dc Rate
IN BOOLEAN CfgEccSyncFlood; ///< ECC Sync Flood
} ECC_OVERRIDE_STRUCT;
/**
* AGESA Test Points
*
* These are the values displayed to the user to indicate progress through boot.
* These can be used in a debug environment to stop the debugger at a specific
* test point:
* For SimNow!, this command
* bi 81 w vb 49
* will stop the debugger on one of the TracePoints (49 is the TP value in this example).
*
*/
typedef enum {
StartProcessorTestPoints, ///< 00 Entry used for range testing for @b Processor related TPs
// Memory test points
TpProcMemBeforeMemDataInit, ///< 01 .. Memory structure initialization (Public interface)
TpProcMemBeforeSpdProcessing, ///< 02 .. SPD Data processing (Public interface)
TpProcMemAmdMemAuto, ///< 03 .. Memory configuration (Public interface)
TpProcMemDramInit, ///< 04 .. DRAM initialization
TpProcMemSPDChecking, ///< 05 ..
TpProcMemModeChecking, ///< 06 ..
TpProcMemSpeedTclConfig, ///< 07 .. Speed and TCL configuration
TpProcMemSpdTiming, ///< 08 ..
TpProcMemDramMapping, ///< 09 ..
TpProcMemPlatformSpecificConfig, ///< 0A ..
TPProcMemPhyCompensation, ///< 0B ..
TpProcMemStartDcts, ///< 0C ..
TpProcMemBeforeDramInit, ///< 0D .. (Public interface)
TpProcMemPhyFenceTraining, ///< 0E ..
TpProcMemSynchronizeDcts, ///< 0F ..
TpProcMemSystemMemoryMapping, ///< 10 ..
TpProcMemMtrrConfiguration, ///< 11 ..
TpProcMemDramTraining, ///< 12 ..
TpProcMemBeforeAnyTraining, ///< 13 .. (Public interface)
TpProcMemWriteLevelizationTraining, ///< 14 ..
TpProcMemWlFirstPass, ///< 15 .. Below 800Mhz first pass start
TpProcMemWlSecondPass, ///< 16 .. Above 800Mhz second pass start
TpProcMemWlTrainTargetDimm, ///< 17 .. Target DIMM configured
TpProcMemWlPrepDimms, ///< 18 .. Prepare DIMMS for WL
TpProcMemWlConfigDimms, ///< 19 .. Configure DIMMS for WL
TpProcMemReceiverEnableTraining, ///< 1A ..
TpProcMemRcvrStartSweep, ///< 1B .. Start sweep loop
TpProcMemRcvrSetDelay, ///< 1C .. Set receiver Delay
TpProcMemRcvrWritePattern, ///< 1D .. Write test pattern
TpProcMemRcvrReadPattern, ///< 1E .. Read test pattern
TpProcMemRcvrTestPattern, ///< 1F .. Compare test pattern
TpProcMemRcvrCalcLatency, ///< 20 .. Calculate MaxRdLatency per channel
TpProcMemReceiveDqsTraining, ///< 21 ..
TpProcMemRcvDqsSetDelay, ///< 22 .. Set Write Data delay
TpProcMemRcvDqsWritePattern, ///< 23 .. Write test pattern
TpProcMemRcvDqsStartSweep, ///< 24 .. Start read sweep
TpProcMemRcvDqsSetRcvDelay, ///< 25 .. Set Receive DQS delay
TpProcMemRcvDqsReadPattern, ///< 26 .. Read Test pattern
TpProcMemRcvDqsTstPattern, ///< 27 .. Compare Test pattern
TpProcMemRcvDqsResults, ///< 28 .. Update results
TpProcMemRcvDqsFindWindow, ///< 29 .. Start Find passing window
TpProcMemTransmitDqsTraining, ///< 2A ..
TpProcMemTxDqStartSweep, ///< 2B .. Start write sweep
TpProcMemTxDqSetDelay, ///< 2C .. Set Transmit DQ delay
TpProcMemTxDqWritePattern, ///< 2D .. Write test pattern
TpProcMemTxDqReadPattern, ///< 2E .. Read Test pattern
TpProcMemTxDqTestPattern, ///< 2F .. Compare Test pattern
TpProcMemTxDqResults, ///< 30 .. Update results
TpProcMemTxDqFindWindow, ///< 31 .. Start Find passing window
TpProcMemMaxRdLatencyTraining, ///< 32 ..
TpProcMemMaxRdLatStartSweep, ///< 33 .. Start sweep
TpProcMemMaxRdLatSetDelay, ///< 34 .. Set delay
TpProcMemMaxRdLatWritePattern, ///< 35 .. Write test pattern
TpProcMemMaxRdLatReadPattern, ///< 36 .. Read Test pattern
TpProcMemMaxRdLatTestPattern, ///< 37 .. Compare Test pattern
TpProcMemOnlineSpareInit, ///< 38 .. Online Spare init
TpProcMemBankInterleaveInit, ///< 39 .. Bank Interleave Init
TpProcMemNodeInterleaveInit, ///< 3A .. Node Interleave Init
TpProcMemChannelInterleaveInit, ///< 3B .. Channel Interleave Init
TpProcMemEccInitialization, ///< 3C .. ECC initialization
TpProcMemPlatformSpecificInit, ///< 3D .. Platform Specific Init
TpProcMemBeforeAgesaReadSpd, ///< 3E .. Before callout for "AgesaReadSpd"
TpProcMemAfterAgesaReadSpd, ///< 3F .. After callout for "AgesaReadSpd"
TpProcMemBeforeAgesaHookBeforeDramInit, ///< 40 .. Before optional callout "AgesaHookBeforeDramInit"
TpProcMemAfterAgesaHookBeforeDramInit, ///< 41 .. After optional callout "AgesaHookBeforeDramInit"
TpProcMemBeforeAgesaHookBeforeDQSTraining, ///< 42 .. Before optional callout "AgesaHookBeforeDQSTraining"
TpProcMemAfterAgesaHookBeforeDQSTraining, ///< 43 .. After optional callout "AgesaHookBeforeDQSTraining"
TpProcMemBeforeAgesaHookBeforeExitSelfRef, ///< 44 .. Before optional callout "AgesaHookBeforeDramInit"
TpProcMemAfterAgesaHookBeforeExitSelfRef, ///< 45 .. After optional callout "AgesaHookBeforeDramInit"
TpProcMemAfterMemDataInit, ///< 46 .. After MemDataInit
TpProcMemInitializeMCT, ///< 47 .. Before InitializeMCT
TpProcMemLvDdr3, ///< 48 .. Before LV DDR3
TpProcMemInitMCT, ///< 49 .. Before InitMCT
TpProcMemOtherTiming, ///< 4A.. Before OtherTiming
TpProcMemUMAMemTyping, ///< 4B .. Before UMAMemTyping
TpProcMemSetDqsEccTmgs, ///< 4C .. Before SetDqsEccTmgs
TpProcMemMemClr, ///< 4D .. Before MemClr
TpProcMemOnDimmThermal, ///< 4E .. Before On DIMM Thermal
TpProcMemDmi, ///< 4F .. Before DMI
TpProcMemEnd, ///< 50 .. End of memory code
// CPU test points
TpProcCpuEntryDmi, ///< 51 .. Entry point CreateDmiRecords
TpProcCpuEntryPstate, ///< 52 .. Entry point GenerateSsdt
TpProcCpuEntryPstateLeveling, ///< 53 .. Entry point PStateLeveling
TpProcCpuEntryPstateGather, ///< 54 .. Entry point PStateGatherData
TpProcCpuEntryWhea, ///< 55 .. Entry point CreateAcpiWhea
TpProcCpuEntrySrat, ///< 56 .. Entry point CreateAcpiSrat
TpProcCpuEntrySlit, ///< 57 .. Entry point CreateAcpiSlit
TpProcCpuProcessRegisterTables, ///< 58 .. Register table processing
TpProcCpuSetBrandID, ///< 59 .. Set brand ID
TpProcCpuLocalApicInit, ///< 5A .. Initialize local APIC
TpProcCpuLoadUcode, ///< 5B .. Load microcode patch
TpProcCpuBeforePMFeatureInit, ///< 5C .. BeforePM feature dispatch point
TpProcCpuPowerMgmtInit, ///< 5D .. Power Management table processing
TpProcCpuEarlyFeatureInit, ///< 5E .. Early feature dispatch point
TpProcCpuCoreLeveling, ///< 5F .. Core Leveling
TpProcCpuApMtrrSync, ///< 60 .. AP MTRR sync up
TpProcCpuPostFeatureInit, ///< 61 .. POST feature dispatch point
TpProcCpuFeatureLeveling, ///< 62 .. CPU Feature Leveling
TpProcCpuBeforeRelinquishAPsFeatureInit, ///< 63 .. Before Relinquishing control of APs feature dispatch point
TpProcCpuBeforeAllocateWheaBuffer, ///< 64 .. Before the WHEA init code calls out to allocate a buffer
TpProcCpuAfterAllocateWheaBuffer, ///< 65 .. After the WHEA init code calls out to allocate a buffer
TpProcCpuBeforeAllocateSratBuffer, ///< 66 .. Before the SRAT init code calls out to allocate a buffer
TpProcCpuAfterAllocateSratBuffer, ///< 67 .. After the SRAT init code calls out to allocate a buffer
TpProcCpuBeforeLocateSsdtBuffer, ///< 68 .. Before the P-state init code calls out to locate a buffer
TpProcCpuAfterLocateSsdtBuffer, ///< 69 .. After the P-state init code calls out to locate a buffer
TpProcCpuBeforeAllocateSsdtBuffer, ///< 6A .. Before the P-state init code calls out to allocate a buffer
TpProcCpuAfterAllocateSsdtBuffer, ///< 6B .. After the P-state init code calls out to allocate a buffer
// HT test points
TpProcHtEntry = 0x71, ///< 71 .. Coherent Discovery begin (Public interface)
TpProcHtTopology, ///< 72 .. Topology match, routing, begin
TpProcHtManualNc, ///< 73 .. Manual Non-coherent Init begin
TpProcHtAutoNc, ///< 74 .. Automatic Non-coherent init begin
TpProcHtOptGather, ///< 75 .. Optimization: Gather begin
TpProcHtOptRegang, ///< 76 .. Optimization: Regang begin
TpProcHtOptLinks, ///< 77 .. Optimization: Link Begin
TpProcHtOptSubLinks, ///< 78 .. Optimization: Sublinks begin
TpProcHtOptFinish, ///< 79 .. Optimization: Set begin
TpProcHtTrafficDist, ///< 7A .. Traffic Distribution begin
TpProcHtTuning, ///< 7B .. Misc Tuning Begin
TpProcHtDone, ///< 7C .. HT Init complete
TpProcHtApMapEntry, ///< 7D .. AP HT: Init Maps begin
TpProcHtApMapDone, ///< 7E .. AP HT: Complete
// Extended memory test point
TpProcMemSendMRS2 = 0x80, ///< 80 .. Sending MRS2
TpProcMemSendMRS3, ///< 81 .. Sedding MRS3
TpProcMemSendMRS1, ///< 82 .. Sending MRS1
TpProcMemSendMRS0, ///< 83 .. Sending MRS0
TpProcMemContinPatternGenRead, ///< 84 .. Continuous Pattern Read
TpProcMemContinPatternGenWrite, ///< 85 .. Continuous Pattern Write
StartNbTestPoints = 0x90, ///< 90 Entry used for range testing for @b NorthBridge related TPs
TpNbxxx, ///< 91 .
EndNbTestPoints, ///< 92 End of TP range for NB
StartSbTestPoints = 0xB0, ///< B0 Entry used for range testing for @b SouthBridge related TPs
TpSbxxx, ///< B1 .
EndSbTestPoints, ///< B2 End of TP range for SB
// Interface test points
TpIfAmdInitResetEntry = 0xC0, ///< C0 .. Entry to AmdInitReset
TpIfAmdInitResetExit, ///< C1 .. Exiting from AmdInitReset
TpIfAmdInitRecoveryEntry, ///< C2 .. Entry to AmdInitRecovery
TpIfAmdInitRecoveryExit, ///< C3 .. Exiting from AmdInitRecovery
TpIfAmdInitEarlyEntry, ///< C4 .. Entry to AmdInitEarly
TpIfAmdInitEarlyExit, ///< C5 .. Exiting from AmdInitEarly
TpIfAmdInitPostEntry, ///< C6 .. Entry to AmdInitPost
TpIfAmdInitPostExit, ///< C7 .. Exiting from AmdInitPost
TpIfAmdInitEnvEntry, ///< C8 .. Entry to AmdInitEnv
TpIfAmdInitEnvExit, ///< C9 .. Exiting from AmdInitEnv
TpIfAmdInitMidEntry, ///< CA .. Entry to AmdInitMid
TpIfAmdInitMidExit, ///< CB .. Exiting from AmdInitMid
TpIfAmdInitLateEntry, ///< CC .. Entry to AmdInitLate
TpIfAmdInitLateExit, ///< CD .. Exiting from AmdInitLate
TpIfAmdS3SaveEntry, ///< CE .. Entry to AmdS3Save
TpIfAmdS3SaveExit, ///< CF .. Exiting from AmdS3Save
TpIfAmdInitResumeEntry, ///< D0 .. Entry to AmdInitResume
TpIfAmdInitResumeExit, ///< D1 .. Exiting from AmdInitResume
TpIfAmdS3LateRestoreEntry, ///< D2 .. Entry to AmdS3LateRestore
TpIfAmdS3LateRestoreExit, ///< D3 .. Exiting from AmdS3LateRestore
TpIfAmdLateRunApTaskEntry, ///< D4 .. Entry to AmdS3LateRestore
TpIfAmdLateRunApTaskExit, ///< D5 .. Exiting from AmdS3LateRestore
TpIfAmdReadEventLogEntry, ///< D6 .. Entry to AmdReadEventLog
TpIfAmdReadEventLogExit, ///< D7 .. Exiting from AmdReadEventLog
TpIfAmdGetApicIdEntry, ///< D8 .. Entry to AmdGetApicId
TpIfAmdGetApicIdExit, ///< D9 .. Exiting from AmdGetApicId
TpIfAmdGetPciAddressEntry, ///< DA .. Entry to AmdGetPciAddress
TpIfAmdGetPciAddressExit, ///< DB .. Exiting from AmdGetPciAddress
TpIfAmdIdentifyCoreEntry, ///< DC .. Entry to AmdIdentifyCore
TpIfAmdIdentifyCoreExit, ///< DD .. Exiting from AmdIdentifyCore
TpIfBeforeRunApFromIds, ///< DE .. After IDS calls out to run code on an AP
TpIfAfterRunApFromIds, ///< DF .. After IDS calls out to run code on an AP
TpIfBeforeGetIdsData, ///< E0 .. Before IDS calls out to get IDS data
TpIfAfterGetIdsData, ///< E1 .. After IDS calls out to get IDS data
TpIfBeforeAllocateHeapBuffer, ///< E2 .. Before the heap manager calls out to allocate a buffer
TpIfAfterAllocateHeapBuffer, ///< E3 .. After the heap manager calls out to allocate a buffer
TpIfBeforeDeallocateHeapBuffer, ///< E4 .. Before the heap manager calls out to deallocate a buffer
TpIfAfterDeallocateHeapBuffer, ///< E5 .. After the heap manager calls out to deallocate a buffer
TpIfBeforeLocateHeapBuffer, ///< E6 .. Before the heap manager calls out to locate a buffer
TpIfAfterLocateHeapBuffer, ///< E7 .. After the heap manager calls out to locate a buffer
TpIfBeforeRunApFromAllAps, ///< E8 .. Before the BSP calls out to run code on an AP
TpIfAfterRunApFromAllAps, ///< E9 .. After the BSP calls out to run code on an AP
TpIfBeforeRunApFromAllCore0s, ///< EA .. Before the BSP calls out to run code on an AP
TpIfAfterRunApFromAllCore0s, ///< EB .. After the BSP calls out to run code on an AP
TpIfBeforeAllocateS3SaveBuffer, ///< EC .. Before the S3 save code calls out to allocate a buffer
TpIfAfterAllocateS3SaveBuffer, ///< ED .. After the S3 save code calls out to allocate a buffer
TpIfBeforeAllocateMemoryS3SaveBuffer, ///< EE .. Before the memory S3 save code calls out to allocate a buffer
TpIfAfterAllocateMemoryS3SaveBuffer, ///< EF .. After the memory S3 save code calls out to allocate a buffer
TpIfBeforeLocateS3PciBuffer, ///< F0 .. Before the memory code calls out to locate a buffer
TpIfAfterLocateS3PciBuffer, ///< F1 .. After the memory code calls out to locate a buffer
TpIfBeforeLocateS3CPciBuffer, ///< F2 .. Before the memory code calls out to locate a buffer
TpIfAfterLocateS3CPciBuffer, ///< F3 .. After the memory code calls out to locate a buffer
TpIfBeforeLocateS3MsrBuffer, ///< F4 .. Before the memory code calls out to locate a buffer
TpIfAfterLocateS3MsrBuffer, ///< F5 .. After the memory code calls out to locate a buffer
TpIfBeforeLocateS3CMsrBuffer, ///< F6 .. Before the memory code calls out to locate a buffer
TpIfAfterLocateS3CMsrBuffer, ///< F7 .. After the memory code calls out to locate a buffer
TpPerfUnit, ///< F8 .. The Unit of performance measure.
EndAgesaTps = 0xFF, ///< Last defined AGESA TP
} AGESA_TP;
///Ids Feat description
typedef enum {
IDS_FEAT_UCODE_UPDATE = 0x0000, ///< Feat for Ucode Update
IDS_FEAT_TARGET_PSTATE, ///< Feat for Target Pstate
IDS_FEAT_POSTPSTATE, ///< Feat for Post Pstate
IDS_FEAT_ECC_CTRL, ///< Feat for Ecc Control
IDS_FEAT_ECC_SYMBOL_SIZE, ///< Feat for Ecc symbol size
IDS_FEAT_DCT_ALLMEMCLK, ///< Feat for all memory clock
IDS_FEAT_DCT_GANGMODE, ///< Feat for Dct gang mode
IDS_FEAT_DCT_BURSTLENGTH, ///< Feat for dct burst length
IDS_FEAT_DCT_POWERDOWN, ///< Feat for dct power down
IDS_FEAT_DCT_DLLSHUTDOWN, ///< Feat for dct dll shut down
IDS_FEAT_PROBE_FILTER, ///< Feat for probe filter
IDS_FEAT_HDTOUT, ///< Feat for hdt out
IDS_FEAT_HT_SETTING, ///< Feat for Ht setting
IDS_FEAT_GNB_PLATFORMCFG, ///< Feat for override GNB platform config
IDS_FEAT_CPB_CTRL, ///< Feat for Config the Core peformance boost feature
IDS_FEAT_HTC_CTRL, ///< Feat for Hardware Thermal Control
IDS_FEAT_MEMORY_MAPPING, ///< Feat for Memory Mapping
IDS_FEAT_POWER_POLICY, ///< Feat for Power Policy
IDS_FEAT_NV_TO_CMOS, ///< Feat for Save BSP Nv to CMOS
IDS_FEAT_END = 0xFF ///< End of Common feat
} IDS_FEAT;
typedef IDS_STATUS IDS_COMMON_FUNC (
IN OUT VOID *DataPtr,
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN IDS_NV_ITEM *IdsNvPtr
);
typedef IDS_COMMON_FUNC *PIDS_COMMON_FUNC;
/// Data Structure of IDS Feature block
typedef struct _IDS_FEAT_STRUCT {
IDS_FEAT IdsFeat; ///< Ids Feat ID
BOOLEAN IsBsp; ///< swith for Bsp check
AGESA_IDS_OPTION IdsOption; ///< IDS option
UINT64 CpuFamily; ///<
PIDS_COMMON_FUNC pf_idsoption; ///<pointer to function
} IDS_FEAT_STRUCT;
/// Data Structure of IDS option
typedef struct _IDS_OPTION_STRUCT {
AGESA_IDS_OPTION idsoption; ///< IDS option
PIDS_COMMON_FUNC pf_idsoption; ///<pointer to function
} IDS_OPTION_STRUCT;
/// Data Structure of IDS option table
typedef struct _IDS_OPTION_STRUCT_TBL {
UINT8 version; ///<Version of IDS option table
UINT16 size; ///<Size of IDS option table
CONST IDS_OPTION_STRUCT *pIdsOptionStruct; ///<pointer to array of structure
} IDS_OPTION_STRUCT_TBL;
#endif // _IDS_H_

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src/vendorcode/amd/agesa/f12/Include/IdsHt.h Executable file
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/* $NoKeywords:$ */
/**
* @file
*
* AMD IDS HyperTransport Definitions
*
* Contains AMD AGESA Integrated Debug HT related items.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: IDS
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _IDS_HT_H_
#define _IDS_HT_H_
// Frequency equates for call backs which take an actual frequency setting
#define HT_FREQUENCY_200M 0
#define HT_FREQUENCY_400M 2
#define HT_FREQUENCY_600M 4
#define HT_FREQUENCY_800M 5
#define HT_FREQUENCY_1000M 6
#define HT_FREQUENCY_1200M 7
#define HT_FREQUENCY_1400M 8
#define HT_FREQUENCY_1600M 9
#define HT_FREQUENCY_1800M 10
#define HT_FREQUENCY_2000M 11
#define HT_FREQUENCY_2200M 12
#define HT_FREQUENCY_2400M 13
#define HT_FREQUENCY_2600M 14
#define HT_FREQUENCY_2800M 17
#define HT_FREQUENCY_3000M 18
#define HT_FREQUENCY_3200M 19
#define HT_FREQUENCY_3600M 20
/**
* HT IDS: HT Link Port Override params.
*
* Provide an absolute override of HT Link Port settings. No checking is done that
* the settings obey limits or capabilities, this responsibility rests with the user.
*
* Rules for values of structure items:
* - Socket
* - HT_LIST_TERMINAL == end of port override list, rest of item is not accessed
* - HT_LIST_MATCH_ANY == Match Any Socket
* - 0 .. 7 == The matching socket
* - Link
* - HT_LIST_MATCH_ANY == Match Any package link (that is not the internal links)
* - HT_LIST_MATCH_INTERNAL_LINK == Match the internal links
* - 0 .. 7 == The matching package link. 0 .. 3 are the ganged links or sublink 0's, 4 .. 7 are the sublink1's.
* - Frequency
* - HT_LIST_TERMINAL == Do not override the frequency, AUTO setting
* - HT_FREQUENCY_200M .. HT_FREQUENCY_3600M = The frequency value to use
* - Widthin
* - HT_LIST_TERMINAL == Do not override the width, AUTO setting
* - 2, 4, 8, 16, 32 == The width value to use
* - Widthout
* - HT_LIST_TERMINAL == Do not override the width, AUTO setting
* - 2, 4, 8, 16, 32 == The width value to use
*/
typedef struct {
// Match Fields
UINT8 Socket; ///< The Socket which this port is on.
UINT8 Link; ///< The port for this package link on that socket.
// Override fields
UINT8 Frequency; ///< Absolutely override the port's frequency.
UINT8 WidthIn; ///< Absolutely override the port's width.
UINT8 WidthOut; ///< Absolutely override the port's width.
} HTIDS_PORT_OVERRIDE;
/**
* A list of port overrides to search.
*/
typedef HTIDS_PORT_OVERRIDE *HTIDS_PORT_OVERRIDE_LIST;
VOID
HtIdsGetPortOverride (
IN BOOLEAN IsSourcePort,
IN OUT PORT_DESCRIPTOR *Port0,
IN OUT PORT_DESCRIPTOR *Port1,
IN OUT HTIDS_PORT_OVERRIDE_LIST *PortOverrideList,
IN STATE_DATA *State
);
typedef
VOID
F_HtIdsGetPortOverride (
IN BOOLEAN IsSourcePort,
IN OUT PORT_DESCRIPTOR *Port0,
IN OUT PORT_DESCRIPTOR *Port1,
IN OUT HTIDS_PORT_OVERRIDE_LIST *PortOverrideList,
IN STATE_DATA *State
);
typedef F_HtIdsGetPortOverride* PF_HtIdsGetPortOverride;
#endif // _IDS_HT_H

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build options for a Lynx platform solution
*
* This file generates the defaults tables for the "Lynx" platform solution
* set of processors. The documented build options are imported from a user
* controlled file for processing.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 52040 $ @e \$Date: 2011-04-30 05:56:20 +0800 (Sat, 30 Apr 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#include "cpuRegisters.h"
#include "cpuFamRegisters.h"
#include "cpuFamilyTranslation.h"
#include "AdvancedApi.h"
#include "heapManager.h"
#include "CreateStruct.h"
#include "cpuFeatures.h"
#include "Table.h"
#include "CommonReturns.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "GnbInterface.h"
/*****************************************************************************
* Define the RELEASE VERSION string
*
* The Release Version string should identify the next planned release.
* When a branch is made in preparation for a release, the release manager
* should change/confirm that the branch version of this file contains the
* string matching the desired version for the release. The trunk version of
* the file should always contain a trailing 'X'. This will make sure that a
* development build from trunk will not be confused for a released version.
* The release manager will need to remove the trailing 'X' and update the
* version string as appropriate for the release. The trunk copy of this file
* should also be updated/incremented for the next expected version, + trailing 'X'
****************************************************************************/
// This is the delivery package title, "LlanoPI "
// This string MUST be exactly 8 characters long
#define AGESA_PACKAGE_STRING {'L', 'l', 'a', 'n', 'o', 'P', 'I', ' '}
// This is the release version number of the AGESA component
// This string MUST be exactly 12 characters long
#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '0', ' ', ' ', ' ', ' '}
// The Lynx solution is defined to be family 0x12 in the FM1 socket.
#define INSTALL_FM1_SOCKET_SUPPORT TRUE
#define INSTALL_FAMILY_12_SUPPORT TRUE
// The following definitions specify the default values for various parameters in which there are
// no clearly defined defaults to be used in the common file. The values below are based on product
// and BKDG content, please consult the AGESA Memory team for consultation.
#define DFLT_SCRUB_DRAM_RATE (0)
#define DFLT_SCRUB_L2_RATE (0)
#define DFLT_SCRUB_L3_RATE (0)
#define DFLT_SCRUB_IC_RATE (0)
#define DFLT_SCRUB_DC_RATE (0)
#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
#define DFLT_VRM_SLEW_RATE (2500)
// Instantiate all solution relevant data.
#include "PlatformInstall.h"

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build options for a Maranello platform solution
*
* This file generates the defaults tables for the "Maranello" platform solution
* set of processors. The documented build options are imported from a user
* controlled file for processing.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 48494 $ @e \$Date: 2011-03-10 02:53:08 +0800 (Thu, 10 Mar 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#include "cpuRegisters.h"
#include "cpuFamRegisters.h"
#include "cpuFamilyTranslation.h"
#include "AdvancedApi.h"
#include "heapManager.h"
#include "CreateStruct.h"
#include "cpuFeatures.h"
#include "Table.h"
#include "CommonReturns.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "GnbInterfaceStub.h"
/*****************************************************************************
* Define the RELEASE VERSION string
*
* The Release Version string should identify the next planned release.
* When a branch is made in preparation for a release, the release manager
* should change/confirm that the branch version of this file contains the
* string matching the desired version for the release. The trunk version of
* the file should always contain a trailing 'X'. This will make sure that a
* development build from trunk will not be confused for a released version.
* The release manager will need to remove the trailing 'X' and update the
* version string as appropriate for the release. The trunk copy of this file
* should also be updated/incremented for the next expected version, + trailing 'X'
****************************************************************************/
// This is the delivery package title, "MarG34PI"
// This string MUST be exactly 8 characters long
#define AGESA_PACKAGE_STRING {'O', 'r', 'o', 'c', 'h', 'i', 'P', 'I'}
// This is the release version number of the AGESA component
// This string MUST be exactly 12 characters long
#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '7', '.', '5', 'X', ' ', ' ', ' '}
// The Maranello solution is defined to be families 0x10 and 0x15 in the G34 socket.
#define INSTALL_G34_SOCKET_SUPPORT TRUE
#define INSTALL_FAMILY_10_SUPPORT TRUE
#define INSTALL_FAMILY_15_SUPPORT TRUE
#ifdef BLDOPT_REMOVE_FAMILY_10_SUPPORT
#if BLDOPT_REMOVE_FAMILY_10_SUPPORT == TRUE
#undef INSTALL_FAMILY_10_SUPPORT
#define INSTALL_FAMILY_10_SUPPORT FALSE
#endif
#endif
#ifdef BLDOPT_REMOVE_FAMILY_15_SUPPORT
#if BLDOPT_REMOVE_FAMILY_15_SUPPORT == TRUE
#undef INSTALL_FAMILY_15_SUPPORT
#define INSTALL_FAMILY_15_SUPPORT FALSE
#endif
#endif
// The following definitions specify the default values for various parameters in which there are
// no clearly defined defaults to be used in the common file. The values below are based on product
// and BKDG content, please consult the AGESA Memory team for consultation.
#define DFLT_SCRUB_DRAM_RATE (0xFF)
#define DFLT_SCRUB_L2_RATE (0x10)
#define DFLT_SCRUB_L3_RATE (0x10)
#define DFLT_SCRUB_IC_RATE (0)
#define DFLT_SCRUB_DC_RATE (0x12)
#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
#define DFLT_VRM_SLEW_RATE (2500)
// Instantiate all solution relevant data.
#include "PlatformInstall.h"

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build options for a Nile platform solution
*
* This file generates the defaults tables for the "Nile" platform solution
* set of processors. The documented build options are imported from a user
* controlled file for processing.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#include "cpuRegisters.h"
#include "cpuFamRegisters.h"
#include "cpuFamilyTranslation.h"
#include "AdvancedApi.h"
#include "heapManager.h"
#include "CreateStruct.h"
#include "cpuFeatures.h"
#include "Table.h"
#include "CommonReturns.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "GnbInterfaceStub.h"
/*****************************************************************************
* Define the RELEASE VERSION string
*
* The Release Version string should identify the next planned release.
* When a branch is made in preparation for a release, the release manager
* should change/confirm that the branch version of this file contains the
* string matching the desired version for the release. The trunk version of
* the file should always contain a trailing 'X'. This will make sure that a
* development build from trunk will not be confused for a released version.
* The release manager will need to remove the trailing 'X' and update the
* version string as appropriate for the release. The trunk copy of this file
* should also be updated/incremented for the next expected version, + trailing 'X'
****************************************************************************/
// This is the delivery package title, "DanNiPI "
// This string MUST be exactly 8 characters long
#define AGESA_PACKAGE_STRING {'D', 'a', 'n', 'N', 'i', 'P', 'I', ' '}
// This is the release version number of the AGESA component
// This string MUST be exactly 12 characters long
#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '5', '.', '0', 'X', ' ', ' ', ' '}
// The Nile solution is defined to be family 0x10 in the ASB2 socket.
#define INSTALL_ASB2_SOCKET_SUPPORT TRUE
#define INSTALL_FAMILY_10_SUPPORT TRUE
// The following definitions specify the default values for various parameters in which there are
// no clearly defined defaults to be used in the common file. The values below are based on product
// and BKDG content, please consult the AGESA Memory team for consultation.
#define DFLT_SCRUB_DRAM_RATE (0)
#define DFLT_SCRUB_L2_RATE (0)
#define DFLT_SCRUB_L3_RATE (0)
#define DFLT_SCRUB_IC_RATE (0)
#define DFLT_SCRUB_DC_RATE (0)
#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
#define DFLT_VRM_SLEW_RATE (5000)
// Instantiate all solution relevant data.
#include "PlatformInstall.h"

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: C6 C-state
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_C6_STATE_INSTALL_H_
#define _OPTION_C6_STATE_INSTALL_H_
#include "cpuC6State.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_C6_STATE_FEAT
#define F12_C6_STATE_SUPPORT
#define F14_ON_C6_STATE_SUPPORT
#define F15_OR_C6_STATE_SUPPORT
#if OPTION_C6_STATE == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
#ifdef OPTION_FAMILY12H
#if OPTION_FAMILY12H == TRUE
#if OPTION_FAMILY12H_LN == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
#undef OPTION_C6_STATE_FEAT
#define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
extern CONST C6_FAMILY_SERVICES ROMDATA F12C6Support;
#undef F12_C6_STATE_SUPPORT
#define F12_C6_STATE_SUPPORT {AMD_FAMILY_12_LN, &F12C6Support},
#if OPTION_EARLY_SAMPLES == TRUE
extern F_F12_ES_C6_INIT F12C6A0Workaround;
CONST F12_ES_C6_SUPPORT ROMDATA F12EarlySampleC6Support =
{
F12C6A0Workaround
};
#else
CONST F12_ES_C6_SUPPORT ROMDATA F12EarlySampleC6Support =
{
(PF_F12_ES_C6_INIT) CommonVoid
};
#endif
#endif
#endif
#endif
#ifdef OPTION_FAMILY14H
#if OPTION_FAMILY14H == TRUE
#if (OPTION_FAMILY14H_ON == TRUE)
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
#undef OPTION_C6_STATE_FEAT
#define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
extern CONST C6_FAMILY_SERVICES ROMDATA F14OnC6Support;
#undef F14_ON_C6_STATE_SUPPORT
#define F14_ON_C6_STATE_SUPPORT {AMD_FAMILY_14_ON, &F14OnC6Support},
CONST F14_ON_ES_C6_SUPPORT ROMDATA F14OnEarlySampleC6Support =
{
(PF_F14_ON_ES_IS_C6_SUPPORTED) CommonVoid,
(PF_F14_ON_ES_C6_INIT) CommonVoid
};
#endif
#endif
#endif
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
#if (OPTION_FAMILY15H_OR == TRUE)
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureC6State;
#undef OPTION_C6_STATE_FEAT
#define OPTION_C6_STATE_FEAT &CpuFeatureC6State,
extern CONST C6_FAMILY_SERVICES ROMDATA F15OrC6Support;
#undef F15_OR_C6_STATE_SUPPORT
#define F15_OR_C6_STATE_SUPPORT {AMD_FAMILY_15_OR, &F15OrC6Support},
CONST F15_OR_ES_C6_SUPPORT ROMDATA F15OrEarlySampleC6Support =
{
(PF_F15_OR_ES_IS_C6_SUPPORTED) CommonVoid
};
#endif
#endif
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA C6FamilyServiceArray[] =
{
F12_C6_STATE_SUPPORT
F14_ON_C6_STATE_SUPPORT
F15_OR_C6_STATE_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA C6FamilyServiceTable =
{
(sizeof (C6FamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&C6FamilyServiceArray[0]
};
#endif // _OPTION_C6_STATE_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Core Performance Boost
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 46389 $ @e \$Date: 2011-02-01 11:22:49 +0800 (Tue, 01 Feb 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_CPB_INSTALL_H_
#define _OPTION_CPB_INSTALL_H_
#include "cpuCpb.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_CPB_FEAT
#define F10_CPB_SUPPORT
#define F12_CPB_SUPPORT
#define F14_ON_CPB_SUPPORT
#define F15_OR_CPB_SUPPORT
#if OPTION_CPB == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
// Family 10h
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
#if OPTION_FAMILY10H_PH == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
#undef OPTION_CPB_FEAT
#define OPTION_CPB_FEAT &CpuFeatureCpb,
extern CONST CPB_FAMILY_SERVICES ROMDATA F10CpbSupport;
#undef F10_CPB_SUPPORT
#define F10_CPB_SUPPORT {AMD_FAMILY_10_PH, &F10CpbSupport},
#endif
#endif
#endif
// Family 12h
#ifdef OPTION_FAMILY12H
#if OPTION_FAMILY12H == TRUE
#if OPTION_FAMILY12H_LN == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
#undef OPTION_CPB_FEAT
#define OPTION_CPB_FEAT &CpuFeatureCpb,
extern CONST CPB_FAMILY_SERVICES ROMDATA F12CpbSupport;
#undef F12_CPB_SUPPORT
#define F12_CPB_SUPPORT {AMD_FAMILY_12_LN, &F12CpbSupport},
// CONST F12_ES_CPB_SUPPORT ROMDATA F12EarlySampleCpbSupport =
// {
// (PF_F12_ES_CPB_INIT) CommonVoid
// };
#endif
#endif
#endif
// Family 14h
#ifdef OPTION_FAMILY14H
#if OPTION_FAMILY14H == TRUE
#if OPTION_FAMILY14H_ON == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
#undef OPTION_CPB_FEAT
#define OPTION_CPB_FEAT &CpuFeatureCpb,
extern CONST CPB_FAMILY_SERVICES ROMDATA F14OnCpbSupport;
#undef F14_ON_CPB_SUPPORT
#define F14_ON_CPB_SUPPORT {AMD_FAMILY_14_ON, &F14OnCpbSupport},
#endif
#endif
#endif
// Family 15h
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
#if (OPTION_FAMILY15H_OR == TRUE)
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCpb;
#undef OPTION_CPB_FEAT
#define OPTION_CPB_FEAT &CpuFeatureCpb,
extern CONST CPB_FAMILY_SERVICES ROMDATA F15OrCpbSupport;
#undef F15_OR_CPB_SUPPORT
#define F15_OR_CPB_SUPPORT {AMD_FAMILY_15_OR, &F15OrCpbSupport},
CONST F15_OR_ES_CPB_SUPPORT ROMDATA F15OrEarlySampleCpbSupport =
{
(PF_F15_OR_ES_IS_CPB_SUPPORTED) CommonVoid
};
#endif
#endif
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpbFamilyServiceArray[] =
{
F10_CPB_SUPPORT
F12_CPB_SUPPORT
F14_ON_CPB_SUPPORT
F15_OR_CPB_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpbFamilyServiceTable =
{
(sizeof (CpbFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&CpbFamilyServiceArray[0]
};
#endif // _OPTION_CPB_INSTALL_H_

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src/vendorcode/amd/agesa/f12/Include/OptionCpuCacheFlushOnHaltInstall.h Executable file
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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: CPU Cache Flush On Halt
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44737 $ @e \$Date: 2011-01-05 15:59:55 +0800 (Wed, 05 Jan 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
#define _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_
#include "cpuPostInit.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
#define F10_BL_CPU_CFOH_SUPPORT
#define F10_DA_CPU_CFOH_SUPPORT
#define F10_CPU_CFOH_SUPPORT
#define F15_OR_CPU_CFOH_SUPPORT
#if OPTION_CPU_CFOH == TRUE
#if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt;
#undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt,
#if OPTION_FAMILY10H_BL == TRUE
extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10BlCacheFlushOnHalt;
#undef F10_BL_CPU_CFOH_SUPPORT
#define F10_BL_CPU_CFOH_SUPPORT {AMD_FAMILY_10_BL, &F10BlCacheFlushOnHalt},
#endif
#if OPTION_FAMILY10H_DA == TRUE
extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10DaCacheFlushOnHalt;
#undef F10_DA_CPU_CFOH_SUPPORT
#define F10_DA_CPU_CFOH_SUPPORT {AMD_FAMILY_10_DA, &F10DaCacheFlushOnHalt},
#endif
#if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_HY == TRUE) || (OPTION_FAMILY10H_PH == TRUE)
extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F10CacheFlushOnHalt;
#undef F10_CPU_CFOH_SUPPORT
#define F10_CPU_CFOH_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_HY | AMD_FAMILY_10_PH, &F10CacheFlushOnHalt},
#endif
#endif
#endif
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCacheFlushOnHalt;
#undef OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
#define OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT &CpuFeatureCacheFlushOnHalt,
#if OPTION_FAMILY15H_OR == TRUE
extern CONST CPU_CFOH_FAMILY_SERVICES ROMDATA F15OrCacheFlushOnHalt;
#undef F15_OR_CPU_CFOH_SUPPORT
#define F15_OR_CPU_CFOH_SUPPORT {AMD_FAMILY_15_OR, &F15OrCacheFlushOnHalt},
#endif
#endif
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CacheFlushOnHaltFamilyServiceArray[] =
{
F10_BL_CPU_CFOH_SUPPORT
F10_DA_CPU_CFOH_SUPPORT
F10_CPU_CFOH_SUPPORT
F15_OR_CPU_CFOH_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CacheFlushOnHaltFamilyServiceTable =
{
(sizeof (CacheFlushOnHaltFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&CacheFlushOnHaltFamilyServiceArray[0]
};
#endif // _OPTION_CPU_CACHEFLUSHONHALT_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: CPU Core Leveling
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_CPU_CORELEVELING_INSTALL_H_
#define _OPTION_CPU_CORELEVELING_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_CPU_CORE_LEVELING_FEAT
#define F10_REVE_CPU_CORELEVELING_SUPPORT
#define F10_REVD_CPU_CORELEVELING_SUPPORT
#define F10_REVC_CPU_CORELEVELING_SUPPORT
#define F15_OR_CPU_CORELEVELING_SUPPORT
#if OPTION_CPU_CORELEVLING == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE)
// Family 10h
#if OPTION_FAMILY10H == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling;
#undef OPTION_CPU_CORE_LEVELING_FEAT
#define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling,
#if OPTION_FAMILY10H_HY == TRUE
extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevDCoreLeveling;
#undef F10_REVD_CPU_CORELEVELING_SUPPORT
#define F10_REVD_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_HY, &F10RevDCoreLeveling},
#endif
#if (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE)
extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevCCoreLeveling;
#undef F10_REVC_CPU_CORELEVELING_SUPPORT
#define F10_REVC_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_RB | AMD_FAMILY_10_BL | AMD_FAMILY_10_DA, &F10RevCCoreLeveling},
#endif
#if (OPTION_FAMILY10H_PH == TRUE)
extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F10RevECoreLeveling;
#undef F10_REVE_CPU_CORELEVELING_SUPPORT
#define F10_REVE_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_10_PH, &F10RevECoreLeveling},
#endif
#endif
// Family 15h
#if OPTION_FAMILY15H == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureCoreLeveling;
#undef OPTION_CPU_CORE_LEVELING_FEAT
#define OPTION_CPU_CORE_LEVELING_FEAT &CpuFeatureCoreLeveling,
extern CONST CPU_CORE_LEVELING_FAMILY_SERVICES ROMDATA F15OrCoreLeveling;
#undef F15_OR_CPU_CORELEVELING_SUPPORT
#define F15_OR_CPU_CORELEVELING_SUPPORT {AMD_FAMILY_15_OR, &F15OrCoreLeveling},
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CoreLevelingFamilyServiceArray[] =
{
F10_REVE_CPU_CORELEVELING_SUPPORT
F10_REVD_CPU_CORELEVELING_SUPPORT
F10_REVC_CPU_CORELEVELING_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CoreLevelingFamilyServiceTable =
{
(sizeof (CoreLevelingFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&CoreLevelingFamilyServiceArray[0]
};
#endif // _OPTION_CPU_CORELEVELING_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of all appropriate CPU family specific support.
*
* This file generates the defaults tables for all family specific
* combinations.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 49967 $ @e \$Date: 2011-03-31 11:15:12 +0800 (Thu, 31 Mar 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
/* Default all CPU Specific Service members to off. They
will be enabled as needed by cross referencing families
with entry points in the family / model install files. */
#define GET_PSTATE_POWER FALSE
#define GET_PSTATE_FREQ FALSE
#define DISABLE_PSTATE FALSE
#define TRANSITION_PSTATE FALSE
#define PROC_IDD_MAX FALSE
#define GET_TSC_RATE FALSE
#define PSTATE_TRANSITION_LATENCY FALSE
#define GET_PSTATE_REGISTER_INFO FALSE
#define GET_PSTATE_MAX_STATE FALSE
#define SET_PSTATE_LEVELING_REG FALSE
#define GET_NB_FREQ FALSE
#define GET_NB_IDD_MAX FALSE
#define IS_NBCOF_INIT_NEEDED FALSE
#define AP_INITIAL_LAUNCH FALSE
#define GET_AP_MAILBOX_FROM_HW FALSE
#define SET_AP_CORE_NUMBER FALSE
#define GET_AP_CORE_NUMBER FALSE
#define TRANSFER_AP_CORE_NUMBER FALSE
#define ID_POSITION_INITIAL_APICID FALSE
#define SAVE_FEATURES FALSE
#define WRITE_FEATURES FALSE
#define SET_DOWN_CORE_REG FALSE
#define SET_WARM_RESET_FLAG FALSE
#define GET_WARM_RESET_FLAG FALSE
#define USES_REGISTER_TABLES FALSE
#define BASE_FAMILY_PCI FALSE
#define MODEL_SPECIFIC_PCI FALSE
#define BASE_FAMILY_MSR FALSE
#define MODEL_SPECIFIC_MSR FALSE
#define BRAND_STRING1 FALSE
#define BRAND_STRING2 FALSE
#define BASE_FAMILY_HT_PCI FALSE
#define MODEL_SPECIFIC_HT_PCI FALSE
#define BASE_FAMILY_WORKAROUNDS FALSE
#define GET_PATCHES FALSE
#define GET_PATCHES_EQUIVALENCE_TABLE FALSE
#define GET_CACHE_INFO FALSE
#define GET_SYSTEM_PM_TABLE FALSE
#define GET_WHEA_INIT FALSE
#define GET_CFOH_REG FALSE
#define GET_PLATFORM_TYPE_SPECIFIC_INFO FALSE
#define IS_NB_PSTATE_ENABLED FALSE
/*
* Pull in family specific services based on entry point
*/
#if AGESA_ENTRY_INIT_RESET == TRUE
#undef ID_POSITION_INITIAL_APICID
#define ID_POSITION_INITIAL_APICID TRUE
#undef GET_AP_MAILBOX_FROM_HW
#define GET_AP_MAILBOX_FROM_HW TRUE
#undef SET_WARM_RESET_FLAG
#define SET_WARM_RESET_FLAG TRUE
#undef GET_WARM_RESET_FLAG
#define GET_WARM_RESET_FLAG TRUE
#undef GET_CACHE_INFO
#define GET_CACHE_INFO TRUE
#undef GET_AP_CORE_NUMBER
#define GET_AP_CORE_NUMBER TRUE
#undef TRANSFER_AP_CORE_NUMBER
#define TRANSFER_AP_CORE_NUMBER TRUE
#endif
#if AGESA_ENTRY_INIT_RECOVERY == TRUE
#undef ID_POSITION_INITIAL_APICID
#define ID_POSITION_INITIAL_APICID TRUE
#undef USES_REGISTER_TABLES
#define USES_REGISTER_TABLES TRUE
#undef BASE_FAMILY_PCI
#define BASE_FAMILY_PCI TRUE
#undef MODEL_SPECIFIC_PCI
#define MODEL_SPECIFIC_PCI TRUE
#undef BASE_FAMILY_MSR
#define BASE_FAMILY_MSR TRUE
#undef MODEL_SPECIFIC_MSR
#define MODEL_SPECIFIC_MSR TRUE
#undef GET_CACHE_INFO
#define GET_CACHE_INFO TRUE
#undef GET_PLATFORM_TYPE_SPECIFIC_INFO
#define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
#undef IS_NB_PSTATE_ENABLED
#define IS_NB_PSTATE_ENABLED TRUE
#undef GET_PATCHES
#define GET_PATCHES TRUE
#undef GET_PATCHES_EQUIVALENCE_TABLE
#define GET_PATCHES_EQUIVALENCE_TABLE TRUE
#endif
#if AGESA_ENTRY_INIT_EARLY == TRUE
#undef TRANSITION_PSTATE
#define TRANSITION_PSTATE TRUE
#undef DISABLE_PSTATE
#define DISABLE_PSTATE TRUE
#undef PROC_IDD_MAX
#define PROC_IDD_MAX TRUE
#undef GET_TSC_RATE
#define GET_TSC_RATE TRUE
#undef GET_NB_FREQ
#define GET_NB_FREQ TRUE
#undef GET_NB_IDD_MAX
#define GET_NB_IDD_MAX TRUE
#undef IS_NBCOF_INIT_NEEDED
#define IS_NBCOF_INIT_NEEDED TRUE
#undef AP_INITIAL_LAUNCH
#define AP_INITIAL_LAUNCH TRUE
#undef GET_AP_MAILBOX_FROM_HW
#define GET_AP_MAILBOX_FROM_HW TRUE
#undef SET_AP_CORE_NUMBER
#define SET_AP_CORE_NUMBER TRUE
#undef GET_AP_CORE_NUMBER
#define GET_AP_CORE_NUMBER TRUE
#undef TRANSFER_AP_CORE_NUMBER
#define TRANSFER_AP_CORE_NUMBER TRUE
#undef ID_POSITION_INITIAL_APICID
#define ID_POSITION_INITIAL_APICID TRUE
#undef SET_DOWN_CORE_REG
#define SET_DOWN_CORE_REG TRUE
#undef SET_WARM_RESET_FLAG
#define SET_WARM_RESET_FLAG TRUE
#undef GET_WARM_RESET_FLAG
#define GET_WARM_RESET_FLAG TRUE
#undef USES_REGISTER_TABLES
#define USES_REGISTER_TABLES TRUE
#undef BASE_FAMILY_PCI
#define BASE_FAMILY_PCI TRUE
#undef MODEL_SPECIFIC_PCI
#define MODEL_SPECIFIC_PCI TRUE
#undef BASE_FAMILY_MSR
#define BASE_FAMILY_MSR TRUE
#undef MODEL_SPECIFIC_MSR
#define MODEL_SPECIFIC_MSR TRUE
#undef BRAND_STRING1
#define BRAND_STRING1 TRUE
#undef BRAND_STRING2
#define BRAND_STRING2 TRUE
#undef BASE_FAMILY_HT_PCI
#define BASE_FAMILY_HT_PCI TRUE
#undef MODEL_SPECIFIC_HT_PCI
#define MODEL_SPECIFIC_HT_PCI TRUE
#undef BASE_FAMILY_WORKAROUNDS
#define BASE_FAMILY_WORKAROUNDS TRUE
#undef GET_PATCHES
#define GET_PATCHES TRUE
#undef GET_PATCHES_EQUIVALENCE_TABLE
#define GET_PATCHES_EQUIVALENCE_TABLE TRUE
#undef GET_SYSTEM_PM_TABLE
#define GET_SYSTEM_PM_TABLE TRUE
#undef GET_CACHE_INFO
#define GET_CACHE_INFO TRUE
#undef GET_PLATFORM_TYPE_SPECIFIC_INFO
#define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
#undef IS_NB_PSTATE_ENABLED
#define IS_NB_PSTATE_ENABLED TRUE
#endif
#if AGESA_ENTRY_INIT_POST == TRUE
#undef ID_POSITION_INITIAL_APICID
#define ID_POSITION_INITIAL_APICID TRUE
#undef GET_PSTATE_POWER
#define GET_PSTATE_POWER TRUE
#undef GET_PSTATE_FREQ
#define GET_PSTATE_FREQ TRUE
#undef TRANSITION_PSTATE
#define TRANSITION_PSTATE TRUE
#undef PROC_IDD_MAX
#define PROC_IDD_MAX TRUE
#undef GET_AP_CORE_NUMBER
#define GET_AP_CORE_NUMBER TRUE
#undef GET_PSTATE_REGISTER_INFO
#define GET_PSTATE_REGISTER_INFO TRUE
#undef GET_PSTATE_MAX_STATE
#define GET_PSTATE_MAX_STATE TRUE
#undef SET_PSTATE_LEVELING_REG
#define SET_PSTATE_LEVELING_REG TRUE
#undef SET_WARM_RESET_FLAG
#define SET_WARM_RESET_FLAG TRUE
#undef GET_WARM_RESET_FLAG
#define GET_WARM_RESET_FLAG TRUE
#undef SAVE_FEATURES
#define SAVE_FEATURES TRUE
#undef WRITE_FEATURES
#define WRITE_FEATURES TRUE
#undef GET_CFOH_REG
#define GET_CFOH_REG TRUE
#undef IS_NB_PSTATE_ENABLED
#define IS_NB_PSTATE_ENABLED TRUE
#endif
#if AGESA_ENTRY_INIT_ENV == TRUE
#endif
#if AGESA_ENTRY_INIT_MID == TRUE
#endif
#if AGESA_ENTRY_INIT_LATE == TRUE
#undef GET_AP_CORE_NUMBER
#define GET_AP_CORE_NUMBER TRUE
#undef GET_PSTATE_FREQ
#define GET_PSTATE_FREQ TRUE
#undef TRANSITION_PSTATE
#define TRANSITION_PSTATE TRUE
#undef PSTATE_TRANSITION_LATENCY
#define PSTATE_TRANSITION_LATENCY TRUE
#undef GET_WHEA_INIT
#define GET_WHEA_INIT TRUE
#undef GET_PLATFORM_TYPE_SPECIFIC_INFO
#define GET_PLATFORM_TYPE_SPECIFIC_INFO TRUE
#undef GET_TSC_RATE
#define GET_TSC_RATE TRUE
#undef BRAND_STRING1
#define BRAND_STRING1 TRUE
#undef BRAND_STRING2
#define BRAND_STRING2 TRUE
#endif
#if AGESA_ENTRY_INIT_S3SAVE == TRUE
#endif
#if AGESA_ENTRY_INIT_RESUME == TRUE
#undef GET_CFOH_REG
#define GET_CFOH_REG TRUE
#endif
#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
#endif
#if AGESA_ENTRY_INIT_GENERAL_SERVICES == TRUE
#undef ID_POSITION_INITIAL_APICID
#define ID_POSITION_INITIAL_APICID TRUE
#endif
/*
* Initialize PCI MMIO mask to 0
*/
#define FAMILY_MMIO_BASE_MASK (0ull)
/*
* Initialize all families to disabled
*/
#define OPT_F10_TABLE
#define OPT_F12_TABLE
#define OPT_F14_TABLE
#define OPT_F15_TABLE
#define OPT_F10_ID_TABLE
#define OPT_F12_ID_TABLE
#define OPT_F14_ID_TABLE
#define OPT_F15_ID_TABLE
/*
* Install family specific support
*/
#if (OPTION_FAMILY10H == TRUE)
#include "OptionFamily10hInstall.h"
#endif
#if (OPTION_FAMILY12H == TRUE)
#include "OptionFamily12hInstall.h"
#endif
#if (OPTION_FAMILY14H == TRUE)
#include "OptionFamily14hInstall.h"
#endif
#if (OPTION_FAMILY15H == TRUE)
#include "OptionFamily15hInstall.h"
#endif
/*
* Process PCI MMIO mask
*/
// If size is 0, but base is not, break the build.
#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE == 0)
#error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
#endif
// If base is 0, but size is not, break the build.
#if (CFG_PCI_MMIO_BASE == 0) && (CFG_PCI_MMIO_SIZE != 0)
#error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
#endif
#if (CFG_PCI_MMIO_BASE != 0) && (CFG_PCI_MMIO_SIZE != 0)
// Both are non-zero, begin further processing.
// Heap runs from 4MB to 8MB. Disallow any addresses below 8MB.
#if (CFG_PCI_MMIO_BASE < 0x800000)
#error BLDCFG: Invalid PCI MMIO base -- must be 8MB or greater
#endif
// Break the build if the address is too high for the enabled families.
#if ((CFG_PCI_MMIO_BASE & FAMILY_MMIO_BASE_MASK) != 0)
#error BLDCFG: Invalid PCI MMIO base address for the installed CPU families
#endif
// If the size parameter is not valid, break the build.
#if (CFG_PCI_MMIO_SIZE != 1) && (CFG_PCI_MMIO_SIZE != 2) && (CFG_PCI_MMIO_SIZE != 4) && (CFG_PCI_MMIO_SIZE != 8) && (CFG_PCI_MMIO_SIZE != 16)
#if (CFG_PCI_MMIO_SIZE != 32) && (CFG_PCI_MMIO_SIZE != 64) && (CFG_PCI_MMIO_SIZE != 128) && (CFG_PCI_MMIO_SIZE != 256)
#error BLDCFG: Invalid PCI MMIO size -- acceptable values are 1, 2, 4, 8, 16, 32, 64, 128, and 256
#endif
#endif
#define PCI_MMIO_ALIGNMENT ((0x100000 * CFG_PCI_MMIO_SIZE) - 1)
// If the base is not aligned according to size, break the build.
#if ((CFG_PCI_MMIO_BASE & PCI_MMIO_ALIGNMENT) != 0)
#error BLDCFG: Invalid PCI MMIO base -- must be properly aligned according to MMIO size
#endif
#undef PCI_MMIO_ALIGNMENT
#endif
/*
* Process sockets / modules
*/
#ifndef ADVCFG_PLATFORM_SOCKETS
#error BLDOPT Set Family supported sockets.
#endif
#ifndef ADVCFG_PLATFORM_MODULES
#error BLDOPT Set Family supported modules.
#endif
CONST OPTIONS_CONFIG_TOPOLOGY ROMDATA TopologyConfiguration =
{
ADVCFG_PLATFORM_SOCKETS,
ADVCFG_PLATFORM_MODULES
};
/*
* Instantiate global data needed for processor identification
*/
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA CpuSupportedFamiliesArray[] =
{
OPT_F10_TABLE
OPT_F12_TABLE
OPT_F14_TABLE
OPT_F15_TABLE
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA CpuSupportedFamiliesTable =
{
(sizeof (CpuSupportedFamiliesArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&CpuSupportedFamiliesArray[0]
};
CONST CPU_LOGICAL_ID_FAMILY_XLAT ROMDATA CpuSupportedFamilyIdArray[] =
{
OPT_F10_ID_TABLE
OPT_F12_ID_TABLE
OPT_F14_ID_TABLE
OPT_F15_ID_TABLE
};
CONST CPU_FAMILY_ID_XLAT_TABLE ROMDATA CpuSupportedFamilyIdTable =
{
(sizeof (CpuSupportedFamilyIdArray) / sizeof (CPU_LOGICAL_ID_FAMILY_XLAT)),
CpuSupportedFamilyIdArray
};

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/* $NoKeywords:$ */
/**
* @file
*
* Install of multiple CPU features.
*
* Aggregates enabled CPU features into a list for the dispatcher to process.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_CPU_FEATURES_INSTALL_H_
#define _OPTION_CPU_FEATURES_INSTALL_H_
#include "OptionHwC1eInstall.h"
#include "OptionMsgBasedC1eInstall.h"
#include "OptionSwC1eInstall.h"
#include "OptionL3FeaturesInstall.h"
#include "OptionCpuCoreLevelingInstall.h"
#include "OptionIoCstateInstall.h"
#include "OptionC6Install.h"
#include "OptionCpbInstall.h"
#include "OptionCpuCacheFlushOnHaltInstall.h"
#include "OptionLowPwrPstateInstall.h"
#include "OptionPreserveMailboxInstall.h"
CONST CPU_FEATURE_DESCRIPTOR* ROMDATA SupportedCpuFeatureList[] =
{
OPTION_HW_C1E_FEAT
OPTION_MSG_BASED_C1E_FEAT
OPTION_SW_C1E_FEAT
OPTION_L3_FEAT
OPTION_CPU_CORE_LEVELING_FEAT
OPTION_IO_CSTATE_FEAT
OPTION_C6_STATE_FEAT
OPTION_CPB_FEAT
OPTION_CPU_CACHE_FLUSH_ON_HALT_FEAT
OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT // this function should be run before creating ACPI objects and after Pstate initialization
OPTION_PRESERVE_MAILBOX_FEAT
NULL
};
#endif // _OPTION_CPU_FEATURES_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* AMD DMI option API.
*
* Contains structures and values used to control the DMI option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_DMI_H_
#define _OPTION_DMI_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_DMI_FEATURE (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN OUT DMI_INFO **DmiPtr
);
typedef AGESA_STATUS OPTION_DMI_RELEASE_BUFFER (
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
#define DMI_STRUCT_VERSION 0x01
/// DMI option configuration. Determine the item of structure when compiling.
typedef struct {
UINT16 OptDmiVersion; ///< Dmi version.
OPTION_DMI_FEATURE *DmiFeature; ///< Feature main routine, otherwise dummy.
OPTION_DMI_RELEASE_BUFFER *DmiReleaseBuffer; ///< Release buffer
UINT16 NumEntries; ///< Number of entry.
VOID *((*FamilyList)[]); ///< Family service.
} OPTION_DMI_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_DMI_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: DMI
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_DMI_INSTALL_H_
#define _OPTION_DMI_INSTALL_H_
#include "cpuLateInit.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#if AGESA_ENTRY_INIT_LATE == TRUE
#ifndef OPTION_DMI
#error BLDOPT: Option not defined: "OPTION_DMI"
#endif
#if OPTION_DMI == TRUE
OPTION_DMI_FEATURE GetDmiInfoMain;
OPTION_DMI_RELEASE_BUFFER ReleaseDmiBuffer;
#define USER_DMI_OPTION &GetDmiInfoMain
#define USER_DMI_RELEASE_BUFFER &ReleaseDmiBuffer
// This additional check keeps AP launch routines from being unnecessarily included
// in single socket systems.
#if OPTION_MULTISOCKET == TRUE
#undef AGESA_ENTRY_LATE_RUN_AP_TASK
#define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
#define CPU_DMI_AP_GET_TYPE4_TYPE7 {AP_LATE_TASK_GET_TYPE4_TYPE7, (IMAGE_ENTRY) GetType4Type7Info},
#else
#define CPU_DMI_AP_GET_TYPE4_TYPE7
#endif
// Family 10
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
extern PROC_FAMILY_TABLE ProcFamily10DmiTable;
#define FAM10_DMI_SUPPORT FAM10_ENABLED,
#define FAM10_DMI_TABLE &ProcFamily10DmiTable,
#else
#define FAM10_DMI_SUPPORT
#define FAM10_DMI_TABLE
#endif
#else
#define FAM10_DMI_SUPPORT
#define FAM10_DMI_TABLE
#endif
// Family 12
#ifdef OPTION_FAMILY12H
#if OPTION_FAMILY12H == TRUE
extern PROC_FAMILY_TABLE ProcFamily12DmiTable;
#define FAM12_DMI_SUPPORT FAM12_ENABLED,
#define FAM12_DMI_TABLE &ProcFamily12DmiTable,
#else
#define FAM12_DMI_SUPPORT
#define FAM12_DMI_TABLE
#endif
#else
#define FAM12_DMI_SUPPORT
#define FAM12_DMI_TABLE
#endif
// Family 14
#ifdef OPTION_FAMILY14H
#if OPTION_FAMILY14H == TRUE
extern PROC_FAMILY_TABLE ProcFamily14DmiTable;
#define FAM14_DMI_SUPPORT FAM14_ENABLED,
#define FAM14_DMI_TABLE &ProcFamily14DmiTable,
#else
#define FAM14_DMI_SUPPORT
#define FAM14_DMI_TABLE
#endif
#else
#define FAM14_DMI_SUPPORT
#define FAM14_DMI_TABLE
#endif
// Family 15
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
#if OPTION_FAMILY15H_OR == TRUE
extern PROC_FAMILY_TABLE ProcFamily15OrDmiTable;
#define FAM15_OR_DMI_SUPPORT FAM15_OR_ENABLED,
#define FAM15_OR_DMI_TABLE &ProcFamily15OrDmiTable,
#else
#define FAM15_OR_DMI_SUPPORT
#define FAM15_OR_DMI_TABLE
#endif
#define FAM15_TN_DMI_SUPPORT
#define FAM15_TN_DMI_TABLE
#else
#define FAM15_OR_DMI_SUPPORT
#define FAM15_OR_DMI_TABLE
#define FAM15_TN_DMI_SUPPORT
#define FAM15_TN_DMI_TABLE
#endif
#else
#define FAM15_OR_DMI_SUPPORT
#define FAM15_OR_DMI_TABLE
#define FAM15_TN_DMI_SUPPORT
#define FAM15_TN_DMI_TABLE
#endif
#else
OPTION_DMI_FEATURE GetDmiInfoStub;
OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub;
#define USER_DMI_OPTION GetDmiInfoStub
#define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub
#define FAM10_DMI_SUPPORT
#define FAM10_DMI_TABLE
#define FAM12_DMI_SUPPORT
#define FAM12_DMI_TABLE
#define FAM14_DMI_SUPPORT
#define FAM14_DMI_TABLE
#define FAM15_OR_DMI_SUPPORT
#define FAM15_OR_DMI_TABLE
#define FAM15_TN_DMI_SUPPORT
#define FAM15_TN_DMI_TABLE
#define CPU_DMI_AP_GET_TYPE4_TYPE7
#endif
#else
OPTION_DMI_FEATURE GetDmiInfoStub;
OPTION_DMI_RELEASE_BUFFER ReleaseDmiBufferStub;
#define USER_DMI_OPTION GetDmiInfoStub
#define USER_DMI_RELEASE_BUFFER ReleaseDmiBufferStub
#define FAM10_DMI_SUPPORT
#define FAM10_DMI_TABLE
#define FAM12_DMI_SUPPORT
#define FAM12_DMI_TABLE
#define FAM14_DMI_SUPPORT
#define FAM14_DMI_TABLE
#define FAM15_OR_DMI_SUPPORT
#define FAM15_OR_DMI_TABLE
#define FAM15_TN_DMI_SUPPORT
#define FAM15_TN_DMI_TABLE
#define CPU_DMI_AP_GET_TYPE4_TYPE7
#endif
/// DMI supported families enum
typedef enum {
FAM10_DMI_SUPPORT ///< Conditionally define F10 support
FAM12_DMI_SUPPORT ///< Conditionally define F12 support
FAM14_DMI_SUPPORT ///< Conditionally define F14 support
FAM15_OR_DMI_SUPPORT ///< Conditionally define F15 OR support
FAM15_TN_DMI_SUPPORT ///< Conditionally define F15 TN support
NUM_DMI_FAMILIES ///< Number of installed families
} AGESA_DMI_SUPPORTED_FAM;
/* Declare the Family List. An array of pointers to tables that each describe a family */
CONST PROC_FAMILY_TABLE ROMDATA *ProcTables[] = {
FAM10_DMI_TABLE
FAM12_DMI_TABLE
FAM14_DMI_TABLE
FAM15_OR_DMI_TABLE
FAM15_TN_DMI_TABLE
NULL
};
/* Declare the instance of the DMI option configuration structure */
CONST OPTION_DMI_CONFIGURATION ROMDATA OptionDmiConfiguration = {
DMI_STRUCT_VERSION,
USER_DMI_OPTION,
USER_DMI_RELEASE_BUFFER,
NUM_DMI_FAMILIES,
(VOID *((*)[])) &ProcTables // Compiler says array size must match struct decl
};
#endif // _OPTION_DMI_INSTALL_H_

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src/vendorcode/amd/agesa/f12/Include/OptionFamily12hEarlySample.h Executable file
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/* $NoKeywords:$ */
/**
* @file
*
* Family 12h 'early sample' support
*
* This file defines the required structures for family 12h pre-production processors.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 37456 $ @e \$Date: 2010-09-04 04:17:05 +0800 (Sat, 04 Sep 2010) $
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _OPTION_FAMILY_12H_EARLY_SAMPLE_H_
#define _OPTION_FAMILY_12H_EARLY_SAMPLE_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/**
* Return the appropriate values of certain NB P-state related registers.
*
* @param[in,out] FCRxFE00_6000 The value of FCRxFE006000.
* @param[in,out] FCRxFE00_6002 The value of FCRxFE006002.
* @param[in,out] FCRxFE00_7006 The value of FCRxFE007006.
* @param[in,out] FCRxFE00_7009 The value of FCRxFE007009.
* @param[in] MainPll The main PLL frequency.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
*/
typedef VOID F_F12_ES_NB_PSTATE_INIT (
IN OUT VOID *FCRxFE00_6000,
IN OUT VOID *FCRxFE00_6002,
IN OUT VOID *FCRxFE00_7006,
IN OUT VOID *FCRxFE00_7009,
IN UINT32 MainPll,
IN AMD_CONFIG_PARAMS *StdHeader
);
/// Reference to a Method.
typedef F_F12_ES_NB_PSTATE_INIT *PF_F12_ES_NB_PSTATE_INIT;
/**
* Return the appropriate value of a certain NB P-state related register.
*
* @param[in,out] FCRxFE00_6000 The value of FCRxFE006000.
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
*/
typedef VOID F_F12_ES_POWER_PLANE_INIT (
IN OUT VOID *FCRxFE00_6000,
IN AMD_CONFIG_PARAMS *StdHeader
);
/// Reference to a Method.
typedef F_F12_ES_POWER_PLANE_INIT *PF_F12_ES_POWER_PLANE_INIT;
/**
* Implements an early sample workaround required for C6
*
* @param[in] StdHeader Handle of Header for calling lib functions and services.
*
*/
typedef VOID F_F12_ES_C6_INIT (
IN AMD_CONFIG_PARAMS *StdHeader
);
/// Reference to a Method.
typedef F_F12_ES_C6_INIT *PF_F12_ES_C6_INIT;
/// Hook points in the core functionality necessary for
/// providing support for pre-production CPUs.
typedef struct {
PF_F12_ES_POWER_PLANE_INIT F12PowerPlaneInitHook; ///< Allows for override of a certain processor register value during power plane init
PF_F12_ES_NB_PSTATE_INIT F12NbPstateInitHook; ///< Allows for override of certain processor register values for proper NB P-state init
} F12_ES_CORE_SUPPORT;
/// Hook points in the C6 feature necessary for
/// providing support for pre-production CPUs.
typedef struct {
PF_F12_ES_C6_INIT F12InitializeC6; ///< Hook for erratum 453 workaround
} F12_ES_C6_SUPPORT;
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
#endif // _OPTION_FAMILY_12H_EARLY_SAMPLE_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of family 12h support
*
* This file generates the defaults tables for family 12h processors.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 49967 $ @e \$Date: 2011-03-31 11:15:12 +0800 (Thu, 31 Mar 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_FAMILY_12H_INSTALL_H_
#define _OPTION_FAMILY_12H_INSTALL_H_
#include "OptionFamily12hEarlySample.h"
/*
* Common Family 12h routines
*/
extern F_CPU_DISABLE_PSTATE F12DisablePstate;
extern F_CPU_TRANSITION_PSTATE F12TransitionPstate;
extern F_CPU_GET_TSC_RATE F12GetTscRate;
extern F_CPU_GET_NB_FREQ F12GetCurrentNbFrequency;
extern F_CPU_GET_NB_PSTATE_INFO F12GetNbPstateInfo;
extern F_CPU_IS_NBCOF_INIT_NEEDED F12GetNbCofVidUpdate;
extern F_CPU_AP_INITIAL_LAUNCH F12LaunchApCore;
extern F_CPU_GET_IDD_MAX F12GetProcIddMax;
extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F12GetApMailboxFromHardware;
extern F_CPU_GET_AP_CORE_NUMBER F12GetApCoreNumber;
extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F12CpuAmdCoreIdPositionInInitialApicId;
extern F_CPU_SET_DOWN_CORE_REGISTER F12SetDownCoreRegister;
extern F_CPU_SET_WARM_RESET_FLAG F12SetAgesaWarmResetFlag;
extern F_CPU_GET_WARM_RESET_FLAG F12GetAgesaWarmResetFlag;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12BrandIdString1;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12BrandIdString2;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12CacheInfo;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12SysPmTable;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12WheaInitData;
//extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetEmptyArray;
extern F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO F12GetPlatformTypeSpecificInfo;
extern CONST REGISTER_TABLE ROMDATA F12PciRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F12PerCorePciRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F12MsrRegisterTable;
extern F_CPU_NUMBER_OF_PHYSICAL_CORES F12GetNumberOfPhysicalCores;
extern F_GET_EARLY_INIT_TABLE GetCommonEarlyInitOnCoreTable;
extern F_IS_NB_PSTATE_ENABLED F12IsNbPstateEnabled;
#if OPTION_EARLY_SAMPLES == TRUE
extern CONST REGISTER_TABLE ROMDATA F12EarlySampleMsrRegisterTable;
#endif
/*
* Install family 12h model 0 support
*/
#ifdef OPTION_FAMILY12H_LN
#if OPTION_FAMILY12H_LN == TRUE
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12LnMicroCodePatchesStruct;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF12LnMicrocodeEquivalenceTable;
#if USES_REGISTER_TABLES == TRUE
CONST REGISTER_TABLE ROMDATA *F12LnRegisterTables[] =
{
#if BASE_FAMILY_PCI == TRUE
&F12PciRegisterTable,
#endif
#if BASE_FAMILY_PCI == TRUE
&F12PerCorePciRegisterTable,
#endif
#if BASE_FAMILY_MSR == TRUE
&F12MsrRegisterTable,
#if OPTION_EARLY_SAMPLES == TRUE
&F12EarlySampleMsrRegisterTable,
#endif
#endif
// the end.
NULL
};
#endif
#if USES_REGISTER_TABLES == TRUE
CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F12LnTableEntryTypeDescriptors[] =
{
{MsrRegister, SetRegisterForMsrEntry},
{PciRegister, SetRegisterForPciEntry},
{FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
{ProfileFixup, (PF_DO_TABLE_ENTRY)CommonVoid},
// End
{TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
};
#endif
CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF12LnServices =
{
0,
#if DISABLE_PSTATE == TRUE
F12DisablePstate,
#else
(PF_CPU_DISABLE_PSTATE) CommonAssert,
#endif
#if TRANSITION_PSTATE == TRUE
F12TransitionPstate,
#else
(PF_CPU_TRANSITION_PSTATE) CommonAssert,
#endif
#if PROC_IDD_MAX == TRUE
F12GetProcIddMax,
#else
(PF_CPU_GET_IDD_MAX) CommonAssert,
#endif
#if GET_TSC_RATE == TRUE
F12GetTscRate,
#else
(PF_CPU_GET_TSC_RATE) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
F12GetCurrentNbFrequency,
#else
(PF_CPU_GET_NB_FREQ) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
(PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
#else
(PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
F12GetNbPstateInfo,
#else
(PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
#endif
#if IS_NBCOF_INIT_NEEDED == TRUE
F12GetNbCofVidUpdate,
#else
(PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
#endif
#if GET_NB_IDD_MAX == TRUE
(PF_CPU_GET_NB_IDD_MAX) CommonAssert,
#else
(PF_CPU_GET_NB_IDD_MAX) CommonAssert,
#endif
#if AP_INITIAL_LAUNCH == TRUE
F12LaunchApCore,
#else
(PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
#endif
#if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
F12GetNumberOfPhysicalCores,
#else
(PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
#endif
#if GET_AP_MAILBOX_FROM_HW == TRUE
F12GetApMailboxFromHardware,
#else
(PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
#endif
#if SET_AP_CORE_NUMBER == TRUE
(PF_CPU_SET_AP_CORE_NUMBER) CommonVoid,
#else
(PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
#endif
#if GET_AP_CORE_NUMBER == TRUE
F12GetApCoreNumber,
#else
(PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
#endif
#if TRANSFER_AP_CORE_NUMBER == TRUE
(PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid,
#else
(PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
#endif
#if ID_POSITION_INITIAL_APICID == TRUE
F12CpuAmdCoreIdPositionInInitialApicId,
#else
(PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
#endif
#if SAVE_FEATURES == TRUE
(PF_CPU_SAVE_FEATURES) CommonVoid,
#else
(PF_CPU_SAVE_FEATURES) CommonAssert,
#endif
#if WRITE_FEATURES == TRUE
(PF_CPU_WRITE_FEATURES) CommonVoid,
#else
(PF_CPU_WRITE_FEATURES) CommonAssert,
#endif
#if SET_WARM_RESET_FLAG == TRUE
F12SetAgesaWarmResetFlag,
#else
(PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
#endif
#if GET_WARM_RESET_FLAG == TRUE
F12GetAgesaWarmResetFlag,
#else
(PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
#endif
#if BRAND_STRING1 == TRUE
GetF12BrandIdString1,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if BRAND_STRING2 == TRUE
GetF12BrandIdString2,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES == TRUE
GetF12LnMicroCodePatchesStruct,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
GetF12LnMicrocodeEquivalenceTable,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_CACHE_INFO == TRUE
GetF12CacheInfo,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_SYSTEM_PM_TABLE == TRUE
GetF12SysPmTable,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_WHEA_INIT == TRUE
GetF12WheaInitData,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
F12GetPlatformTypeSpecificInfo,
#else
(PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
#endif
#if IS_NB_PSTATE_ENABLED == TRUE
F12IsNbPstateEnabled,
#else
(PF_IS_NB_PSTATE_ENABLED) CommonAssert,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
(PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
#else
(PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
(PF_SET_HT_PHY_REGISTER) CommonVoid,
#else
(PF_SET_HT_PHY_REGISTER) CommonAssert,
#endif
#if BASE_FAMILY_PCI == TRUE
(PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
#else
(PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
#endif
#if USES_REGISTER_TABLES == TRUE
(REGISTER_TABLE **) F12LnRegisterTables,
#else
NULL,
#endif
#if USES_REGISTER_TABLES == TRUE
(TABLE_ENTRY_TYPE_DESCRIPTOR *) F12LnTableEntryTypeDescriptors,
#else
NULL,
#endif
#if MODEL_SPECIFIC_HT_PCI == TRUE
NULL,
#else
NULL,
#endif
NULL,
InitCacheDisabled,
#if AGESA_ENTRY_INIT_EARLY == TRUE
GetCommonEarlyInitOnCoreTable
#else
(PF_GET_EARLY_INIT_TABLE) CommonVoid
#endif
};
#define LN_SOCKETS 1
#define LN_MODULES 1
#define LN_RECOVERY_SOCKETS 1
#define LN_RECOVERY_MODULES 1
extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF12LnLogicalIdAndRev;
#define OPT_F12_LN_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF12LnLogicalIdAndRev,
#ifndef ADVCFG_PLATFORM_SOCKETS
#define ADVCFG_PLATFORM_SOCKETS LN_SOCKETS
#else
#if ADVCFG_PLATFORM_SOCKETS < LN_SOCKETS
#undef ADVCFG_PLATFORM_SOCKETS
#define ADVCFG_PLATFORM_SOCKETS LN_SOCKETS
#endif
#endif
#ifndef ADVCFG_PLATFORM_MODULES
#define ADVCFG_PLATFORM_MODULES LN_MODULES
#else
#if ADVCFG_PLATFORM_MODULES < LN_MODULES
#undef ADVCFG_PLATFORM_MODULES
#define ADVCFG_PLATFORM_MODULES LN_MODULES
#endif
#endif
#if GET_PATCHES == TRUE
#define F12_LN_UCODE_02
#define F12_LN_UCODE_0E
#define F12_LN_UCODE_0F
// If a patch is required for recovery mode to function properly, add a
// conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
#if AGESA_ENTRY_INIT_EARLY == TRUE
extern CONST MICROCODE_PATCHES ROMDATA CpuF12MicrocodePatch0300000f;
#undef F12_LN_UCODE_0F
#define F12_LN_UCODE_0F &CpuF12MicrocodePatch0300000f,
#if OPTION_EARLY_SAMPLES == TRUE
extern CONST MICROCODE_PATCHES ROMDATA CpuF12MicrocodePatch03000002;
extern CONST MICROCODE_PATCHES ROMDATA CpuF12MicrocodePatch0300000e;
#undef F12_LN_UCODE_02
#define F12_LN_UCODE_02 &CpuF12MicrocodePatch03000002,
#undef F12_LN_UCODE_0E
#define F12_LN_UCODE_0E &CpuF12MicrocodePatch0300000e,
#endif
#endif
CONST MICROCODE_PATCHES ROMDATA *CpuF12LnMicroCodePatchArray[] =
{
F12_LN_UCODE_0F
F12_LN_UCODE_0E
F12_LN_UCODE_02
NULL
};
CONST UINT8 ROMDATA CpuF12LnNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF12LnMicroCodePatchArray) / sizeof (CpuF12LnMicroCodePatchArray[0])) - 1);
#endif
#if OPTION_EARLY_SAMPLES == TRUE
extern F_F12_ES_NB_PSTATE_INIT F12NbPstateInitEarlySampleHook;
extern F_F12_ES_POWER_PLANE_INIT F12PowerPlaneInitEarlySampleHook;
CONST F12_ES_CORE_SUPPORT ROMDATA F12EarlySampleCoreSupport =
{
#if AGESA_ENTRY_INIT_EARLY == TRUE
F12PowerPlaneInitEarlySampleHook,
#else
(PF_F12_ES_POWER_PLANE_INIT) CommonAssert,
#endif
#if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE)
F12NbPstateInitEarlySampleHook
#else
(PF_F12_ES_NB_PSTATE_INIT) CommonAssert
#endif
};
#else
CONST F12_ES_CORE_SUPPORT ROMDATA F12EarlySampleCoreSupport =
{
#if AGESA_ENTRY_INIT_EARLY == TRUE
(PF_F12_ES_POWER_PLANE_INIT) CommonVoid,
#else
(PF_F12_ES_POWER_PLANE_INIT) CommonAssert,
#endif
#if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE)
(PF_F12_ES_NB_PSTATE_INIT) CommonVoid
#else
(PF_F12_ES_NB_PSTATE_INIT) CommonAssert
#endif
};
#endif
#define OPT_F12_LN_CPU {AMD_FAMILY_12_LN, &cpuF12LnServices},
#else // OPTION_FAMILY12H_LN == TRUE
#define OPT_F12_LN_CPU
#define OPT_F12_LN_ID
#endif // OPTION_FAMILY12H_LN == TRUE
#else // defined (OPTION_FAMILY12H_LN)
#define OPT_F12_LN_CPU
#define OPT_F12_LN_ID
#endif // defined (OPTION_FAMILY12H_LN)
/*
* Install unknown family 12h support
*/
#if USES_REGISTER_TABLES == TRUE
CONST REGISTER_TABLE ROMDATA *F12UnknownRegisterTables[] =
{
#if BASE_FAMILY_PCI == TRUE
&F12PciRegisterTable,
#endif
#if BASE_FAMILY_PCI == TRUE
&F12PerCorePciRegisterTable,
#endif
#if BASE_FAMILY_MSR == TRUE
&F12MsrRegisterTable,
#endif
// the end.
NULL
};
#endif
#if USES_REGISTER_TABLES == TRUE
CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F12UnknownTableEntryTypeDescriptors[] =
{
{MsrRegister, SetRegisterForMsrEntry},
{PciRegister, SetRegisterForPciEntry},
{FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
{ProfileFixup, (PF_DO_TABLE_ENTRY)CommonVoid},
// End
{TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
};
#endif
CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF12UnknownServices =
{
0,
#if DISABLE_PSTATE == TRUE
F12DisablePstate,
#else
(PF_CPU_DISABLE_PSTATE) CommonAssert,
#endif
#if TRANSITION_PSTATE == TRUE
F12TransitionPstate,
#else
(PF_CPU_TRANSITION_PSTATE) CommonAssert,
#endif
#if PROC_IDD_MAX == TRUE
F12GetProcIddMax,
#else
(PF_CPU_GET_IDD_MAX) CommonAssert,
#endif
#if GET_TSC_RATE == TRUE
F12GetTscRate,
#else
(PF_CPU_GET_TSC_RATE) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
F12GetCurrentNbFrequency,
#else
(PF_CPU_GET_NB_FREQ) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
(PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
#else
(PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
F12GetNbPstateInfo,
#else
(PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
#endif
#if IS_NBCOF_INIT_NEEDED == TRUE
F12GetNbCofVidUpdate,
#else
(PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
#endif
#if GET_NB_IDD_MAX == TRUE
(PF_CPU_GET_NB_IDD_MAX) CommonAssert,
#else
(PF_CPU_GET_NB_IDD_MAX) CommonAssert,
#endif
#if AP_INITIAL_LAUNCH == TRUE
F12LaunchApCore,
#else
(PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
#endif
#if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
F12GetNumberOfPhysicalCores,
#else
(PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
#endif
#if GET_AP_MAILBOX_FROM_HW == TRUE
F12GetApMailboxFromHardware,
#else
(PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
#endif
#if SET_AP_CORE_NUMBER == TRUE
(PF_CPU_SET_AP_CORE_NUMBER) CommonVoid,
#else
(PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
#endif
#if GET_AP_CORE_NUMBER == TRUE
F12GetApCoreNumber,
#else
(PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
#endif
#if TRANSFER_AP_CORE_NUMBER == TRUE
(PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid,
#else
(PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
#endif
#if ID_POSITION_INITIAL_APICID == TRUE
F12CpuAmdCoreIdPositionInInitialApicId,
#else
(PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
#endif
#if SAVE_FEATURES == TRUE
(PF_CPU_SAVE_FEATURES) CommonVoid,
#else
(PF_CPU_SAVE_FEATURES) CommonAssert,
#endif
#if WRITE_FEATURES == TRUE
(PF_CPU_WRITE_FEATURES) CommonVoid,
#else
(PF_CPU_WRITE_FEATURES) CommonAssert,
#endif
#if SET_WARM_RESET_FLAG == TRUE
F12SetAgesaWarmResetFlag,
#else
(PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
#endif
#if GET_WARM_RESET_FLAG == TRUE
F12GetAgesaWarmResetFlag,
#else
(PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
#endif
#if BRAND_STRING1 == TRUE
GetF12BrandIdString1,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if BRAND_STRING2 == TRUE
GetF12BrandIdString2,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES == TRUE
GetEmptyArray,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
GetEmptyArray,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_CACHE_INFO == TRUE
GetF12CacheInfo,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_SYSTEM_PM_TABLE == TRUE
GetF12SysPmTable,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_WHEA_INIT == TRUE
GetF12WheaInitData,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
F12GetPlatformTypeSpecificInfo,
#else
(PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
#endif
#if IS_NB_PSTATE_ENABLED == TRUE
F12IsNbPstateEnabled,
#else
(PF_IS_NB_PSTATE_ENABLED) CommonAssert,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
(PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
#else
(PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonAssert,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
(PF_SET_HT_PHY_REGISTER) CommonVoid,
#else
(PF_SET_HT_PHY_REGISTER) CommonAssert,
#endif
#if BASE_FAMILY_PCI == TRUE
(PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
#else
(PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert,
#endif
#if USES_REGISTER_TABLES == TRUE
(REGISTER_TABLE **) F12UnknownRegisterTables,
#else
NULL,
#endif
#if USES_REGISTER_TABLES == TRUE
(TABLE_ENTRY_TYPE_DESCRIPTOR *) F12UnknownTableEntryTypeDescriptors,
#else
NULL,
#endif
#if MODEL_SPECIFIC_HT_PCI == TRUE
NULL,
#else
NULL,
#endif
NULL,
InitCacheDisabled,
#if AGESA_ENTRY_INIT_EARLY == TRUE
GetCommonEarlyInitOnCoreTable
#else
(PF_GET_EARLY_INIT_TABLE) CommonVoid
#endif
};
// Family 12h maximum base address is 40 bits. Limit BLDCFG to 40 bits, if appropriate.
#if (FAMILY_MMIO_BASE_MASK < 0xFFFFFF0000000000ull)
#undef FAMILY_MMIO_BASE_MASK
#define FAMILY_MMIO_BASE_MASK (0xFFFFFF0000000000ull)
#endif
#undef OPT_F12_ID_TABLE
#define OPT_F12_ID_TABLE {0x12ul, {AMD_FAMILY_12, AMD_F12_UNKNOWN}, F12LogicalIdTable, (sizeof (F12LogicalIdTable) / sizeof (F12LogicalIdTable[0]))},
#define OPT_F12_UNKNOWN_CPU {AMD_FAMILY_12, &cpuF12UnknownServices},
#undef OPT_F12_TABLE
#define OPT_F12_TABLE OPT_F12_LN_CPU OPT_F12_UNKNOWN_CPU
#if OPTION_FS1_SOCKET_SUPPORT == TRUE
extern CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString1ArrayFs1;
extern CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString2ArrayFs1;
#define F12_FS1_BRANDSTRING1 &F12LnBrandIdString1ArrayFs1,
#define F12_FS1_BRANDSTRING2 &F12LnBrandIdString2ArrayFs1,
#else
#define F12_FS1_BRANDSTRING1
#define F12_FS1_BRANDSTRING2
#endif
#if OPTION_FM1_SOCKET_SUPPORT == TRUE
extern CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString1ArrayFm1;
extern CONST CPU_BRAND_TABLE ROMDATA F12LnBrandIdString2ArrayFm1;
#define F12_FM1_BRANDSTRING1 &F12LnBrandIdString1ArrayFm1,
#define F12_FM1_BRANDSTRING2 &F12LnBrandIdString2ArrayFm1,
#else
#define F12_FM1_BRANDSTRING1
#define F12_FM1_BRANDSTRING2
#endif
#if OPTION_FP1_SOCKET_SUPPORT == TRUE
#define F12_FP1_BRANDSTRING1 NULL,
#define F12_FP1_BRANDSTRING2 NULL,
#else
#define F12_FP1_BRANDSTRING1
#define F12_FP1_BRANDSTRING2
#endif
#if BRAND_STRING1 == TRUE
CONST CPU_BRAND_TABLE ROMDATA *F12BrandIdString1Tables[] =
{
F12_FS1_BRANDSTRING1
F12_FM1_BRANDSTRING1
F12_FP1_BRANDSTRING1
};
CONST UINT8 F12BrandIdString1TableCount = (sizeof (F12BrandIdString1Tables) / sizeof (F12BrandIdString1Tables[0]));
#endif
#if BRAND_STRING2 == TRUE
CONST CPU_BRAND_TABLE ROMDATA *F12BrandIdString2Tables[] =
{
F12_FS1_BRANDSTRING2
F12_FM1_BRANDSTRING2
F12_FP1_BRANDSTRING2
};
CONST UINT8 F12BrandIdString2TableCount = (sizeof (F12BrandIdString2Tables) / sizeof (F12BrandIdString2Tables[0]));
#endif
CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F12LogicalIdTable[] =
{
OPT_F12_LN_ID
};
#endif // _OPTION_FAMILY_12H_INSTALL_H_

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src/vendorcode/amd/agesa/f12/Include/OptionFamily14hInstall.h Executable file
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@ -0,0 +1,687 @@
/* $NoKeywords:$ */
/**
* @file
*
* Install of family 14h support
*
* This file generates the default tables for family 14h processors.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 49967 $ @e \$Date: 2011-03-31 11:15:12 +0800 (Thu, 31 Mar 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_FAMILY_14H_INSTALL_H_
#define _OPTION_FAMILY_14H_INSTALL_H_
#include "OptionFamily14hEarlySample.h"
/*
* Common Family 14h routines
*/
extern F_CPU_DISABLE_PSTATE F14DisablePstate;
extern F_CPU_TRANSITION_PSTATE F14TransitionPstate;
extern F_CPU_GET_TSC_RATE F14GetTscRate;
extern F_CPU_GET_NB_FREQ F14GetCurrentNbFrequency;
extern F_CPU_GET_NB_PSTATE_INFO F14GetNbPstateInfo;
extern F_CPU_IS_NBCOF_INIT_NEEDED F14GetNbCofVidUpdate;
extern F_CPU_AP_INITIAL_LAUNCH F14LaunchApCore;
extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F14GetApMailboxFromHardware;
extern F_CPU_GET_AP_CORE_NUMBER F14GetApCoreNumber;
extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F14CpuAmdCoreIdPositionInInitialApicId;
extern F_CPU_SET_WARM_RESET_FLAG F14SetAgesaWarmResetFlag;
extern F_CPU_GET_WARM_RESET_FLAG F14GetAgesaWarmResetFlag;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14BrandIdString1;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14BrandIdString2;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14CacheInfo;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14WheaInitData;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetEmptyArray;
extern F_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO F14GetPlatformTypeSpecificInfo;
extern F_CPU_GET_IDD_MAX F14GetProcIddMax;
extern CONST REGISTER_TABLE ROMDATA F14PciRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F14PerCorePciRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F14MsrRegisterTable;
extern F_CPU_NUMBER_OF_PHYSICAL_CORES F14GetNumberOfPhysicalCores;
extern F_IS_NB_PSTATE_ENABLED F14IsNbPstateEnabled;
#if OPTION_EARLY_SAMPLES == TRUE
extern CONST REGISTER_TABLE ROMDATA F14EarlySampleMsrRegisterTable;
#endif
/*
* Install family 14h model 0 support
*/
#ifdef OPTION_FAMILY14H_ON
#if OPTION_FAMILY14H_ON == TRUE
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14OnMicroCodePatchesStruct;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14OnMicrocodeEquivalenceTable;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF14OnSysPmTable;
extern F_GET_EARLY_INIT_TABLE GetF14OnEarlyInitOnCoreTable;
extern CONST REGISTER_TABLE ROMDATA F14OnMsrRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F14OnPciRegisterTable;
#if USES_REGISTER_TABLES == TRUE
CONST REGISTER_TABLE ROMDATA *F14OnRegisterTables[] =
{
#if BASE_FAMILY_PCI == TRUE
&F14PciRegisterTable,
#endif
#if BASE_FAMILY_PCI == TRUE
&F14PerCorePciRegisterTable,
#endif
#if BASE_FAMILY_MSR == TRUE
&F14MsrRegisterTable,
#if OPTION_EARLY_SAMPLES == TRUE
&F14EarlySampleMsrRegisterTable,
#endif
#endif
#if MODEL_SPECIFIC_PCI == TRUE
&F14OnPciRegisterTable,
#endif
#if MODEL_SPECIFIC_MSR == TRUE
&F14OnMsrRegisterTable,
#endif
// the end.
NULL
};
#endif
#if USES_REGISTER_TABLES == TRUE
CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F14OnTableEntryTypeDescriptors[] =
{
{MsrRegister, SetRegisterForMsrEntry},
{PciRegister, SetRegisterForPciEntry},
{FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
// End
{TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
};
#endif
CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF14OnServices =
{
0,
#if DISABLE_PSTATE == TRUE
F14DisablePstate,
#else
(PF_CPU_DISABLE_PSTATE) CommonAssert,
#endif
#if TRANSITION_PSTATE == TRUE
F14TransitionPstate,
#else
(PF_CPU_TRANSITION_PSTATE) CommonAssert,
#endif
#if PROC_IDD_MAX == TRUE
F14GetProcIddMax,
#else
(PF_CPU_GET_IDD_MAX) CommonAssert,
#endif
#if GET_TSC_RATE == TRUE
F14GetTscRate,
#else
(PF_CPU_GET_TSC_RATE) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
F14GetCurrentNbFrequency,
#else
(PF_CPU_GET_NB_FREQ) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
(PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
#else
(PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
F14GetNbPstateInfo,
#else
(PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
#endif
#if IS_NBCOF_INIT_NEEDED == TRUE
F14GetNbCofVidUpdate,
#else
(PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
#endif
#if GET_NB_IDD_MAX == TRUE
(PF_CPU_GET_NB_IDD_MAX) CommonAssert,
#else
(PF_CPU_GET_NB_IDD_MAX) CommonAssert,
#endif
#if AP_INITIAL_LAUNCH == TRUE
F14LaunchApCore,
#else
(PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
#endif
#if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
F14GetNumberOfPhysicalCores,
#else
(PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
#endif
#if GET_AP_MAILBOX_FROM_HW == TRUE
F14GetApMailboxFromHardware,
#else
(PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
#endif
#if SET_AP_CORE_NUMBER == TRUE
(PF_CPU_SET_AP_CORE_NUMBER) CommonVoid,
#else
(PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
#endif
#if GET_AP_CORE_NUMBER == TRUE
F14GetApCoreNumber,
#else
(PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
#endif
#if TRANSFER_AP_CORE_NUMBER == TRUE
(PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid,
#else
(PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
#endif
#if ID_POSITION_INITIAL_APICID == TRUE
F14CpuAmdCoreIdPositionInInitialApicId,
#else
(PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
#endif
#if SAVE_FEATURES == TRUE
(PF_CPU_SAVE_FEATURES) CommonVoid,
#else
(PF_CPU_SAVE_FEATURES) CommonAssert,
#endif
#if WRITE_FEATURES == TRUE
(PF_CPU_WRITE_FEATURES) CommonVoid,
#else
(PF_CPU_WRITE_FEATURES) CommonAssert,
#endif
#if SET_WARM_RESET_FLAG == TRUE
F14SetAgesaWarmResetFlag,
#else
(PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
#endif
#if GET_WARM_RESET_FLAG == TRUE
F14GetAgesaWarmResetFlag,
#else
(PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
#endif
#if BRAND_STRING1 == TRUE
GetF14BrandIdString1,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if BRAND_STRING2 == TRUE
GetF14BrandIdString2,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES == TRUE
GetF14OnMicroCodePatchesStruct,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
GetF14OnMicrocodeEquivalenceTable,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_CACHE_INFO == TRUE
GetF14CacheInfo,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_SYSTEM_PM_TABLE == TRUE
GetF14OnSysPmTable,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_WHEA_INIT == TRUE
GetF14WheaInitData,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
F14GetPlatformTypeSpecificInfo,
#else
(PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
#endif
#if IS_NB_PSTATE_ENABLED == TRUE
F14IsNbPstateEnabled,
#else
(PF_IS_NB_PSTATE_ENABLED) CommonAssert,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
(PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
#else
(PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
(PF_SET_HT_PHY_REGISTER) CommonVoid,
#else
(PF_SET_HT_PHY_REGISTER) CommonAssert,
#endif
#if BASE_FAMILY_PCI == TRUE
(PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
#else
(PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
#endif
#if USES_REGISTER_TABLES == TRUE
(REGISTER_TABLE **) F14OnRegisterTables,
#else
NULL,
#endif
#if USES_REGISTER_TABLES == TRUE
(TABLE_ENTRY_TYPE_DESCRIPTOR *) F14OnTableEntryTypeDescriptors,
#else
NULL,
#endif
#if MODEL_SPECIFIC_HT_PCI == TRUE
NULL,
#else
NULL,
#endif
NULL,
InitCacheDisabled,
#if AGESA_ENTRY_INIT_EARLY == TRUE
GetF14OnEarlyInitOnCoreTable
#else
(PF_GET_EARLY_INIT_TABLE) CommonVoid
#endif
};
#define ON_SOCKETS 1
#define ON_MODULES 1
#define ON_RECOVERY_SOCKETS 1
#define ON_RECOVERY_MODULES 1
extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF14OnLogicalIdAndRev;
#define OPT_F14_ON_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF14OnLogicalIdAndRev,
#ifndef ADVCFG_PLATFORM_SOCKETS
#define ADVCFG_PLATFORM_SOCKETS ON_SOCKETS
#else
#if ADVCFG_PLATFORM_SOCKETS < ON_SOCKETS
#undef ADVCFG_PLATFORM_SOCKETS
#define ADVCFG_PLATFORM_SOCKETS ON_SOCKETS
#endif
#endif
#ifndef ADVCFG_PLATFORM_MODULES
#define ADVCFG_PLATFORM_MODULES ON_MODULES
#else
#if ADVCFG_PLATFORM_MODULES < ON_MODULES
#undef ADVCFG_PLATFORM_MODULES
#define ADVCFG_PLATFORM_MODULES ON_MODULES
#endif
#endif
#if GET_PATCHES == TRUE
#define F14_ON_UCODE_0B
#define F14_ON_UCODE_1A
#define F14_ON_UCODE_25
// If a patch is required for recovery mode to function properly, add a
// conditional for AGESA_ENTRY_INIT_RECOVERY, and pull it in.
#if AGESA_ENTRY_INIT_EARLY == TRUE
#if OPTION_EARLY_SAMPLES == TRUE
extern CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch0500000B;
#undef F14_ON_UCODE_0B
#define F14_ON_UCODE_0B &CpuF14MicrocodePatch0500000B,
extern CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch0500001A;
#undef F14_ON_UCODE_1A
#define F14_ON_UCODE_1A &CpuF14MicrocodePatch0500001A,
#endif
extern CONST MICROCODE_PATCHES ROMDATA CpuF14MicrocodePatch05000025;
#undef F14_ON_UCODE_25
#define F14_ON_UCODE_25 &CpuF14MicrocodePatch05000025,
#endif
CONST MICROCODE_PATCHES ROMDATA *CpuF14OnMicroCodePatchArray[] =
{
F14_ON_UCODE_0B
F14_ON_UCODE_1A
F14_ON_UCODE_25
NULL
};
CONST UINT8 ROMDATA CpuF14OnNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF14OnMicroCodePatchArray) / sizeof (CpuF14OnMicroCodePatchArray[0])) - 1);
#endif
#if OPTION_EARLY_SAMPLES == TRUE
extern F_F14_ON_ES_GET_EARLY_INIT_TABLE GetF14OnEarlySampleEarlyInitTable;
extern F_F14_ON_ES_NB_PSTATE_INIT F14OnNbPstateInitEarlySampleHook;
extern F_F14_ON_ES_POWER_PLANE_INIT F14OnPowerPlaneInitEarlySampleHook;
CONST F14_ON_ES_CORE_SUPPORT ROMDATA F14OnEarlySampleCoreSupport =
{
#if AGESA_ENTRY_INIT_EARLY == TRUE
GetF14OnEarlySampleEarlyInitTable,
F14OnPowerPlaneInitEarlySampleHook,
#else
(PF_F14_ON_ES_GET_EARLY_INIT_TABLE) CommonAssert,
(PF_F14_ON_ES_POWER_PLANE_INIT) CommonAssert,
#endif
#if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE)
F14OnNbPstateInitEarlySampleHook
#else
(PF_F14_ON_ES_NB_PSTATE_INIT) CommonAssert
#endif
};
#else
CONST F14_ON_ES_CORE_SUPPORT ROMDATA F14OnEarlySampleCoreSupport =
{
#if AGESA_ENTRY_INIT_EARLY == TRUE
(PF_F14_ON_ES_GET_EARLY_INIT_TABLE) CommonVoid,
(PF_F14_ON_ES_POWER_PLANE_INIT) CommonVoid,
#else
(PF_F14_ON_ES_GET_EARLY_INIT_TABLE) CommonAssert,
(PF_F14_ON_ES_POWER_PLANE_INIT) CommonAssert,
#endif
#if (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_RECOVERY == TRUE)
(PF_F14_ON_ES_NB_PSTATE_INIT) CommonVoid
#else
(PF_F14_ON_ES_NB_PSTATE_INIT) CommonAssert
#endif
};
#endif
#define OPT_F14_ON_CPU {AMD_FAMILY_14_ON, &cpuF14OnServices},
#else // OPTION_FAMILY14H_ON == TRUE
#define OPT_F14_ON_CPU
#define OPT_F14_ON_ID
#endif // OPTION_FAMILY14H_ON == TRUE
#else // defined (OPTION_FAMILY14H_ON)
#define OPT_F14_ON_CPU
#define OPT_F14_ON_ID
#endif // defined (OPTION_FAMILY14H_ON)
/*
* Install unknown family 14h support
*/
#if USES_REGISTER_TABLES == TRUE
CONST REGISTER_TABLE ROMDATA *F14UnknownRegisterTables[] =
{
#if BASE_FAMILY_PCI == TRUE
&F14PciRegisterTable,
#endif
#if BASE_FAMILY_PCI == TRUE
&F14PerCorePciRegisterTable,
#endif
#if BASE_FAMILY_MSR == TRUE
&F14MsrRegisterTable,
#endif
// the end.
NULL
};
#endif
#if USES_REGISTER_TABLES == TRUE
CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F14UnknownTableEntryTypeDescriptors[] =
{
{MsrRegister, SetRegisterForMsrEntry},
{PciRegister, SetRegisterForPciEntry},
{FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
// End
{TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
};
#endif
CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF14UnknownServices =
{
0,
#if DISABLE_PSTATE == TRUE
F14DisablePstate,
#else
(PF_CPU_DISABLE_PSTATE) CommonAssert,
#endif
#if TRANSITION_PSTATE == TRUE
F14TransitionPstate,
#else
(PF_CPU_TRANSITION_PSTATE) CommonAssert,
#endif
#if PROC_IDD_MAX == TRUE
(PF_CPU_GET_IDD_MAX) F14GetProcIddMax,
#else
(PF_CPU_GET_IDD_MAX) CommonAssert,
#endif
#if GET_TSC_RATE == TRUE
F14GetTscRate,
#else
(PF_CPU_GET_TSC_RATE) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
F14GetCurrentNbFrequency,
#else
(PF_CPU_GET_NB_FREQ) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
(PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
#else
(PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
F14GetNbPstateInfo,
#else
(PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
#endif
#if IS_NBCOF_INIT_NEEDED == TRUE
F14GetNbCofVidUpdate,
#else
(PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
#endif
#if GET_NB_IDD_MAX == TRUE
(PF_CPU_GET_NB_IDD_MAX) CommonAssert,
#else
(PF_CPU_GET_NB_IDD_MAX) CommonAssert,
#endif
#if AP_INITIAL_LAUNCH == TRUE
F14LaunchApCore,
#else
(PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
#endif
#if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
F14GetNumberOfPhysicalCores,
#else
(PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
#endif
#if GET_AP_MAILBOX_FROM_HW == TRUE
F14GetApMailboxFromHardware,
#else
(PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
#endif
#if SET_AP_CORE_NUMBER == TRUE
(PF_CPU_SET_AP_CORE_NUMBER) CommonVoid,
#else
(PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
#endif
#if GET_AP_CORE_NUMBER == TRUE
F14GetApCoreNumber,
#else
(PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
#endif
#if TRANSFER_AP_CORE_NUMBER == TRUE
(PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonVoid,
#else
(PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
#endif
#if ID_POSITION_INITIAL_APICID == TRUE
F14CpuAmdCoreIdPositionInInitialApicId,
#else
(PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
#endif
#if SAVE_FEATURES == TRUE
(PF_CPU_SAVE_FEATURES) CommonVoid,
#else
(PF_CPU_SAVE_FEATURES) CommonAssert,
#endif
#if WRITE_FEATURES == TRUE
(PF_CPU_WRITE_FEATURES) CommonVoid,
#else
(PF_CPU_WRITE_FEATURES) CommonAssert,
#endif
#if SET_WARM_RESET_FLAG == TRUE
F14SetAgesaWarmResetFlag,
#else
(PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
#endif
#if GET_WARM_RESET_FLAG == TRUE
F14GetAgesaWarmResetFlag,
#else
(PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
#endif
#if BRAND_STRING1 == TRUE
GetF14BrandIdString1,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if BRAND_STRING2 == TRUE
GetF14BrandIdString2,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES == TRUE
GetEmptyArray,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
GetEmptyArray,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_CACHE_INFO == TRUE
GetF14CacheInfo,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_SYSTEM_PM_TABLE == TRUE
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_WHEA_INIT == TRUE
GetF14WheaInitData,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
F14GetPlatformTypeSpecificInfo,
#else
(PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
#endif
#if IS_NB_PSTATE_ENABLED == TRUE
F14IsNbPstateEnabled,
#else
(PF_IS_NB_PSTATE_ENABLED) CommonAssert,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
(PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
#else
(PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonVoid,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
(PF_SET_HT_PHY_REGISTER) CommonVoid,
#else
(PF_SET_HT_PHY_REGISTER) CommonVoid,
#endif
#if BASE_FAMILY_PCI == TRUE
(PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
#else
(PF_GET_NEXT_HT_LINK_FEATURES) CommonReturnFalse,
#endif
#if USES_REGISTER_TABLES == TRUE
(REGISTER_TABLE **) F14UnknownRegisterTables,
#else
NULL,
#endif
#if USES_REGISTER_TABLES == TRUE
(TABLE_ENTRY_TYPE_DESCRIPTOR *) F14UnknownTableEntryTypeDescriptors,
#else
NULL,
#endif
#if MODEL_SPECIFIC_HT_PCI == TRUE
NULL,
#else
NULL,
#endif
NULL,
InitCacheDisabled,
#if AGESA_ENTRY_INIT_EARLY == TRUE
(PF_GET_EARLY_INIT_TABLE) CommonVoid
#else
(PF_GET_EARLY_INIT_TABLE) CommonVoid
#endif
};
// End - unknown family 14h support
// Family 14h maximum base address is 40 bits. Limit BLDCFG to 40 bits, if appropriate.
#if (FAMILY_MMIO_BASE_MASK < 0xFFFFFF0000000000ull)
#undef FAMILY_MMIO_BASE_MASK
#define FAMILY_MMIO_BASE_MASK (0xFFFFFF0000000000ull)
#endif
#undef OPT_F14_ID_TABLE
#define OPT_F14_ID_TABLE {0x14ul, {AMD_FAMILY_14, AMD_F14_UNKNOWN}, F14LogicalIdTable, (sizeof (F14LogicalIdTable) / sizeof (F14LogicalIdTable[0]))},
#define OPT_F14_UNKNOWN_CPU {AMD_FAMILY_14, &cpuF14UnknownServices},
#undef OPT_F14_TABLE
#define OPT_F14_TABLE OPT_F14_ON_CPU OPT_F14_UNKNOWN_CPU
#if OPTION_FT1_SOCKET_SUPPORT == TRUE
extern CONST CPU_BRAND_TABLE ROMDATA F14OnBrandIdString1ArrayFt1;
extern CONST CPU_BRAND_TABLE ROMDATA F14OnBrandIdString2ArrayFt1;
#define F14_FT1_BRANDSTRING1 &F14OnBrandIdString1ArrayFt1,
#define F14_FT1_BRANDSTRING2 &F14OnBrandIdString2ArrayFt1,
#else
#define F14_FT1_BRANDSTRING1
#define F14_FT1_BRANDSTRING2
#endif
#if BRAND_STRING1 == TRUE
CONST CPU_BRAND_TABLE ROMDATA *F14BrandIdString1Tables[] =
{
F14_FT1_BRANDSTRING1
};
CONST UINT8 F14BrandIdString1TableCount = (sizeof (F14BrandIdString1Tables) / sizeof (F14BrandIdString1Tables[0]));
#endif
#if BRAND_STRING2 == TRUE
CONST CPU_BRAND_TABLE ROMDATA *F14BrandIdString2Tables[] =
{
F14_FT1_BRANDSTRING2
};
CONST UINT8 F14BrandIdString2TableCount = (sizeof (F14BrandIdString2Tables) / sizeof (F14BrandIdString2Tables[0]));
#endif
CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F14LogicalIdTable[] =
{
OPT_F14_ON_ID
};
#endif // _OPTION_FAMILY_14H_INSTALL_H_

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src/vendorcode/amd/agesa/f12/Include/OptionFamily15hInstall.h Executable file
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/* $NoKeywords:$ */
/**
* @file
*
* Install of family 15h support
*
* This file generates the defaults tables for family 15h processors.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 50117 $ @e \$Date: 2011-04-02 14:36:40 +0800 (Sat, 02 Apr 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_FAMILY_15H_INSTALL_H_
#define _OPTION_FAMILY_15H_INSTALL_H_
/*
* Pull in family specific services based on entry point
*/
/*
* Common Family 15h routines
*/
extern F_IS_NB_PSTATE_ENABLED F15IsNbPstateEnabled;
/*
* Install family 15h model 0 support
*/
#ifdef OPTION_FAMILY15H_OR
#if OPTION_FAMILY15H_OR == TRUE
extern F_CPU_GET_IDD_MAX F15OrGetProcIddMax;
extern F_CPU_GET_NB_PSTATE_INFO F15OrGetNbPstateInfo;
extern F_CPU_IS_NBCOF_INIT_NEEDED F15CommonGetNbCofVidUpdate;
extern F_CPU_DISABLE_PSTATE F15DisablePstate;
extern F_CPU_TRANSITION_PSTATE F15TransitionPstate;
extern F_CPU_GET_TSC_RATE F15GetTscRate;
extern F_CPU_GET_NB_FREQ F15OrGetCurrentNbFrequency;
extern F_CPU_GET_MIN_MAX_NB_FREQ F15OrGetMinMaxNbFrequency;
extern F_CPU_AP_INITIAL_LAUNCH F15LaunchApCore;
extern F_CPU_NUMBER_OF_PHYSICAL_CORES F15OrGetNumberOfPhysicalCores;
extern F_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE F15OrGetApMailboxFromHardware;
extern F_CPU_SET_AP_CORE_NUMBER F15OrSetApCoreNumber;
extern F_CPU_GET_AP_CORE_NUMBER F15OrGetApCoreNumber;
extern F_CPU_TRANSFER_AP_CORE_NUMBER F15OrTransferApCoreNumber;
extern F_CORE_ID_POSITION_IN_INITIAL_APIC_ID F15CpuAmdCoreIdPositionInInitialApicId;
extern F_CPU_SET_WARM_RESET_FLAG F15SetAgesaWarmResetFlag;
extern F_CPU_GET_WARM_RESET_FLAG F15GetAgesaWarmResetFlag;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15CacheInfo;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15OrSysPmTable;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15WheaInitData;
extern F_CPU_SET_CFOH_REG SetF15OrCacheFlushOnHaltRegister;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetEmptyArray;
extern F_NEXT_LINK_HAS_HTFPY_FEATS F15NextLinkHasHtPhyFeats;
extern F_SET_HT_PHY_REGISTER F15SetHtPhyRegister;
extern F_GET_NEXT_HT_LINK_FEATURES F15GetNextHtLinkFeatures;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15OrMicroCodePatchesStruct;
extern F_CPU_GET_FAMILY_SPECIFIC_ARRAY GetF15OrMicrocodeEquivalenceTable;
extern F_GET_EARLY_INIT_TABLE GetF15OrEarlyInitOnCoreTable;
extern CONST REGISTER_TABLE ROMDATA F15OrPciRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F15OrMsrRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F15OrSharedMsrRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F15OrSharedMsrCuRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F15OrSharedMsrWorkaroundTable;
extern CONST REGISTER_TABLE ROMDATA F15OrHtPhyRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F15PciRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F15MsrRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F15OrMultiLinkPciRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F15OrSingleLinkPciRegisterTable;
extern CONST REGISTER_TABLE ROMDATA F15OrWorkaroundsTable;
extern CONST PACKAGE_HTLINK_MAP_ITEM ROMDATA HtFam15PackageLinkMap[];
/**
* Core Pair and core pair primary determination table.
*
* The two fields from the core pair hardware register can be used to determine whether
* even number cores are primary or all cores are primary. It can be extended if it is
* decided to have other configs as well. The other logically possible value sets are BitMapMapping,
* but they are currently not supported by the processor.
*/
CONST CORE_PAIR_MAP ROMDATA HtFam15CorePairMapping[] =
{
{1, 1, EvenCoresMapping}, ///< 1 Compute Unit with 2 cores
{3, 3, EvenCoresMapping}, ///< 2 Compute Units both with 2 Cores
{7, 7, EvenCoresMapping}, ///< 3 Compute Units all with 2 Cores
{0xF, 0xF, EvenCoresMapping}, ///< 4 Compute Units all with 2 Cores
{1, 0, AllCoresMapping}, ///< 1 Compute Unit with 1 core
{3, 0, AllCoresMapping}, ///< 2 Compute Units both with 1 Core
{7, 0, AllCoresMapping}, ///< 3 Compute Units all with 1 Core
{0xF, 0, AllCoresMapping}, ///< 4 Compute Units all with 1 Core
{HT_LIST_TERMINAL, HT_LIST_TERMINAL, MaxComputeUnitMapping} ///< End
};
#if USES_REGISTER_TABLES == TRUE
CONST REGISTER_TABLE ROMDATA *F15OrRegisterTables[] =
{
#if BASE_FAMILY_PCI == TRUE
&F15PciRegisterTable,
#endif
#if MODEL_SPECIFIC_PCI == TRUE
&F15OrMultiLinkPciRegisterTable,
&F15OrSingleLinkPciRegisterTable,
#endif
#if MODEL_SPECIFIC_PCI == TRUE
&F15OrPciRegisterTable,
#endif
#if BASE_FAMILY_MSR == TRUE
&F15MsrRegisterTable,
#endif
#if MODEL_SPECIFIC_MSR == TRUE
&F15OrMsrRegisterTable,
#endif
#if MODEL_SPECIFIC_MSR == TRUE
&F15OrSharedMsrRegisterTable,
&F15OrSharedMsrCuRegisterTable,
&F15OrSharedMsrWorkaroundTable,
#endif
#if MODEL_SPECIFIC_HT_PCI == TRUE
&F15OrHtPhyRegisterTable,
#endif
#if BASE_FAMILY_WORKAROUNDS == TRUE
&F15OrWorkaroundsTable,
#endif
// the end.
NULL
};
#endif
#if USES_REGISTER_TABLES == TRUE
CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15OrTableEntryTypeDescriptors[] =
{
{MsrRegister, SetRegisterForMsrEntry},
{PciRegister, SetRegisterForPciEntry},
{FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
{HtPhyRegister, SetRegisterForHtPhyEntry},
{HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
{DeemphasisRegister, SetRegisterForDeemphasisEntry},
{HtPhyFreqRegister, SetRegisterForHtPhyFreqEntry},
{ProfileFixup, SetRegisterForPerformanceProfileEntry},
{HtHostPciRegister, SetRegisterForHtHostEntry},
{HtHostPerfPciRegister, SetRegisterForHtHostPerfEntry},
{HtTokenPciRegister, SetRegisterForHtLinkTokenEntry},
{CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
{ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
{CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry},
{TokenPciRegister, SetRegisterForTokenPciEntry},
{HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
{HtLinkPciRegister, SetRegisterForHtLinkPciEntry},
{CompUnitCountsMsr, SetMsrForComputeUnitCountsEntry},
// End
{TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
};
#endif
CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15OrServices =
{
0,
#if DISABLE_PSTATE == TRUE
F15DisablePstate,
#else
(PF_CPU_DISABLE_PSTATE) CommonAssert,
#endif
#if TRANSITION_PSTATE == TRUE
F15TransitionPstate,
#else
(PF_CPU_TRANSITION_PSTATE) CommonAssert,
#endif
#if PROC_IDD_MAX == TRUE
F15OrGetProcIddMax,
#else
(PF_CPU_GET_IDD_MAX) CommonAssert,
#endif
#if GET_TSC_RATE == TRUE
F15GetTscRate,
#else
(PF_CPU_GET_TSC_RATE) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
F15OrGetCurrentNbFrequency,
#else
(PF_CPU_GET_NB_FREQ) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
F15OrGetMinMaxNbFrequency,
#else
(PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
F15OrGetNbPstateInfo,
#else
(PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
#endif
#if IS_NBCOF_INIT_NEEDED == TRUE
F15CommonGetNbCofVidUpdate,
#else
(PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
#endif
#if GET_NB_IDD_MAX == TRUE
(PF_CPU_GET_NB_IDD_MAX) CommonAssert,
#else
(PF_CPU_GET_NB_IDD_MAX) CommonAssert,
#endif
#if AP_INITIAL_LAUNCH == TRUE
F15LaunchApCore,
#else
(PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
#endif
#if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
F15OrGetNumberOfPhysicalCores,
#else
(PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
#endif
#if GET_AP_MAILBOX_FROM_HW == TRUE
F15OrGetApMailboxFromHardware,
#else
(PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
#endif
#if SET_AP_CORE_NUMBER == TRUE
F15OrSetApCoreNumber,
#else
(PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
#endif
#if GET_AP_CORE_NUMBER == TRUE
F15OrGetApCoreNumber,
#else
(PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
#endif
#if TRANSFER_AP_CORE_NUMBER == TRUE
F15OrTransferApCoreNumber,
#else
(PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
#endif
#if ID_POSITION_INITIAL_APICID == TRUE
F15CpuAmdCoreIdPositionInInitialApicId,
#else
(PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
#endif
#if SAVE_FEATURES == TRUE
// F15OrSaveFeatures,
(PF_CPU_SAVE_FEATURES) CommonVoid,
#else
(PF_CPU_SAVE_FEATURES) CommonAssert,
#endif
#if WRITE_FEATURES == TRUE
// F15OrWriteFeatures,
(PF_CPU_WRITE_FEATURES) CommonVoid,
#else
(PF_CPU_WRITE_FEATURES) CommonAssert,
#endif
#if SET_WARM_RESET_FLAG == TRUE
F15SetAgesaWarmResetFlag,
#else
(PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
#endif
#if GET_WARM_RESET_FLAG == TRUE
F15GetAgesaWarmResetFlag,
#else
(PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
#endif
#if BRAND_STRING1 == TRUE
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if BRAND_STRING2 == TRUE
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES == TRUE
GetF15OrMicroCodePatchesStruct,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
GetF15OrMicrocodeEquivalenceTable,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_CACHE_INFO == TRUE
GetF15CacheInfo,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_SYSTEM_PM_TABLE == TRUE
GetF15OrSysPmTable,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_WHEA_INIT == TRUE
GetF15WheaInitData,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
(PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess,
#else
(PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
#endif
#if IS_NB_PSTATE_ENABLED == TRUE
F15IsNbPstateEnabled,
#else
(PF_IS_NB_PSTATE_ENABLED) CommonAssert,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
F15NextLinkHasHtPhyFeats,
#else
(PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
F15SetHtPhyRegister,
#else
(PF_SET_HT_PHY_REGISTER) CommonAssert,
#endif
#if BASE_FAMILY_PCI == TRUE
F15GetNextHtLinkFeatures,
#else
(PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert,
#endif
#if USES_REGISTER_TABLES == TRUE
(REGISTER_TABLE **) F15OrRegisterTables,
#else
NULL,
#endif
#if USES_REGISTER_TABLES == TRUE
(TABLE_ENTRY_TYPE_DESCRIPTOR *) F15OrTableEntryTypeDescriptors,
#else
NULL,
#endif
#if MODEL_SPECIFIC_HT_PCI == TRUE
(PACKAGE_HTLINK_MAP) &HtFam15PackageLinkMap,
#else
NULL,
#endif
(CORE_PAIR_MAP *) &HtFam15CorePairMapping,
InitCacheEnabled,
#if AGESA_ENTRY_INIT_EARLY == TRUE
GetF15OrEarlyInitOnCoreTable
#else
(PF_GET_EARLY_INIT_TABLE) CommonVoid
#endif
};
#define OR_SOCKETS 8
#define OR_MODULES 2
#define OR_RECOVERY_SOCKETS 1
#define OR_RECOVERY_MODULES 1
extern F_CPU_GET_SUBFAMILY_ID_ARRAY GetF15OrLogicalIdAndRev;
#define OPT_F15_OR_ID (PF_CPU_GET_SUBFAMILY_ID_ARRAY) GetF15OrLogicalIdAndRev,
#ifndef ADVCFG_PLATFORM_SOCKETS
#define ADVCFG_PLATFORM_SOCKETS OR_SOCKETS
#else
#if ADVCFG_PLATFORM_SOCKETS < OR_SOCKETS
#undef ADVCFG_PLATFORM_SOCKETS
#define ADVCFG_PLATFORM_SOCKETS OR_SOCKETS
#endif
#endif
#ifndef ADVCFG_PLATFORM_MODULES
#define ADVCFG_PLATFORM_MODULES OR_MODULES
#else
#if ADVCFG_PLATFORM_MODULES < OR_MODULES
#undef ADVCFG_PLATFORM_MODULES
#define ADVCFG_PLATFORM_MODULES OR_MODULES
#endif
#endif
#if GET_PATCHES == TRUE
#define F15_OR_UCODE_17
#define F15_OR_UCODE_11F
#define F15_OR_UCODE_41C
#if AGESA_ENTRY_INIT_EARLY == TRUE
#if OPTION_EARLY_SAMPLES == TRUE
extern CONST MICROCODE_PATCHES_4K ROMDATA CpuF15OrMicrocodePatch06000017;
#undef F15_OR_UCODE_17
#define F15_OR_UCODE_17 &CpuF15OrMicrocodePatch06000017,
extern CONST MICROCODE_PATCHES_4K ROMDATA CpuF15OrMicrocodePatch0600011F;
#undef F15_OR_UCODE_11F
#define F15_OR_UCODE_11F &CpuF15OrMicrocodePatch0600011F,
extern CONST MICROCODE_PATCHES_4K ROMDATA CpuF15OrMicrocodePatch0600041C_Enc;
#undef F15_OR_UCODE_41C
#define F15_OR_UCODE_41C &CpuF15OrMicrocodePatch0600041C_Enc,
#endif
#endif
CONST MICROCODE_PATCHES_4K ROMDATA *CpuF15OrMicroCodePatchArray[] =
{
F15_OR_UCODE_41C
F15_OR_UCODE_11F
F15_OR_UCODE_17
NULL
};
CONST UINT8 ROMDATA CpuF15OrNumberOfMicrocodePatches = (UINT8) ((sizeof (CpuF15OrMicroCodePatchArray) / sizeof (CpuF15OrMicroCodePatchArray[0])) - 1);
#endif
#if OPTION_EARLY_SAMPLES == TRUE
extern F_F15_OR_ES_HTC_INIT_HOOK F15OrHtcInitEarlySampleHook;
CONST F15_OR_ES_CORE_SUPPORT ROMDATA F15OrEarlySampleCoreSupport =
{
#if AGESA_ENTRY_INIT_EARLY == TRUE
F15OrHtcInitEarlySampleHook,
#else
(PF_F15_OR_ES_HTC_INIT_HOOK) CommonAssert,
#endif
};
#else
CONST F15_OR_ES_CORE_SUPPORT ROMDATA F15OrEarlySampleCoreSupport =
{
#if AGESA_ENTRY_INIT_EARLY == TRUE
(PF_F15_OR_ES_HTC_INIT_HOOK) CommonVoid,
#else
(PF_F15_OR_ES_HTC_INIT_HOOK) CommonAssert,
#endif
};
#endif
#define OPT_F15_OR_CPU {AMD_FAMILY_15_OR, &cpuF15OrServices},
#else // OPTION_FAMILY15H_OR == TRUE
#define OPT_F15_OR_CPU
#define OPT_F15_OR_ID
#endif // OPTION_FAMILY15H_OR == TRUE
#else // defined (OPTION_FAMILY15H_OR)
#define OPT_F15_OR_CPU
#define OPT_F15_OR_ID
#endif // defined (OPTION_FAMILY15H_OR)
/*
* Install unknown family 15h support
*/
#if USES_REGISTER_TABLES == TRUE
CONST REGISTER_TABLE ROMDATA *F15UnknownRegisterTables[] =
{
#if BASE_FAMILY_PCI == TRUE
&F15PciRegisterTable,
#endif
#if BASE_FAMILY_MSR == TRUE
&F15MsrRegisterTable,
#endif
#if BASE_FAMILY_HT_PCI == TRUE
&F15HtPhyRegisterTable,
#endif
#if OPTION_MULTISOCKET == TRUE
#if MODEL_SPECIFIC_PCI == TRUE
&F15MultiLinkPciRegisterTable,
#endif
#endif
#if OPTION_MULTISOCKET == FALSE
#if MODEL_SPECIFIC_PCI == TRUE
&F15SingleLinkPciRegisterTable,
#endif
#endif
#if BASE_FAMILY_WORKAROUNDS == TRUE
&F15WorkaroundsTable,
#endif
// the end.
NULL
};
#endif
#if USES_REGISTER_TABLES == TRUE
CONST TABLE_ENTRY_TYPE_DESCRIPTOR ROMDATA F15UnknownTableEntryTypeDescriptors[] =
{
{MsrRegister, SetRegisterForMsrEntry},
{PciRegister, SetRegisterForPciEntry},
{FamSpecificWorkaround, SetRegisterForFamSpecificWorkaroundEntry},
{HtPhyRegister, SetRegisterForHtPhyEntry},
{HtPhyRangeRegister, SetRegisterForHtPhyRangeEntry},
{DeemphasisRegister, SetRegisterForDeemphasisEntry},
{ProfileFixup, SetRegisterForPerformanceProfileEntry},
{HtHostPciRegister, SetRegisterForHtHostEntry},
{HtHostPerfPciRegister, SetRegisterForHtHostPerfEntry},
{HtTokenPciRegister, (PF_DO_TABLE_ENTRY)CommonVoid},
{CoreCountsPciRegister, SetRegisterForCoreCountsPerformanceEntry},
{ProcCountsPciRegister, SetRegisterForProcessorCountsEntry},
{CompUnitCountsPciRegister, SetRegisterForComputeUnitCountsEntry},
{HtFeatPciRegister, SetRegisterForHtFeaturePciEntry},
{CompUnitCountsMsr, SetMsrForComputeUnitCountsEntry},
// End
{TableEntryTypeMax, (PF_DO_TABLE_ENTRY)CommonVoid}
};
#endif
CONST CPU_SPECIFIC_SERVICES ROMDATA cpuF15UnknownServices =
{
0,
#if DISABLE_PSTATE == TRUE
F15DisablePstate,
#else
(PF_CPU_DISABLE_PSTATE) CommonAssert,
#endif
#if TRANSITION_PSTATE == TRUE
F15TransitionPstate,
#else
(PF_CPU_TRANSITION_PSTATE) CommonAssert,
#endif
#if PROC_IDD_MAX == TRUE
(PF_CPU_GET_IDD_MAX) CommonReturnFalse,
#else
(PF_CPU_GET_IDD_MAX) CommonAssert,
#endif
#if GET_TSC_RATE == TRUE
F15GetTscRate,
#else
(PF_CPU_GET_TSC_RATE) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
(PF_CPU_GET_NB_FREQ) CommonAssert,
#else
(PF_CPU_GET_NB_FREQ) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
(PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
#else
(PF_CPU_GET_MIN_MAX_NB_FREQ) CommonAssert,
#endif
#if GET_NB_FREQ == TRUE
(PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
#else
(PF_CPU_GET_NB_PSTATE_INFO) CommonAssert,
#endif
#if IS_NBCOF_INIT_NEEDED == TRUE
(PF_CPU_IS_NBCOF_INIT_NEEDED) CommonReturnFalse,
#else
(PF_CPU_IS_NBCOF_INIT_NEEDED) CommonAssert,
#endif
#if GET_NB_IDD_MAX == TRUE
(PF_CPU_GET_NB_IDD_MAX) CommonAssert,
#else
(PF_CPU_GET_NB_IDD_MAX) CommonAssert,
#endif
#if AP_INITIAL_LAUNCH == TRUE
F15LaunchApCore,
#else
(PF_CPU_AP_INITIAL_LAUNCH) CommonAssert,
#endif
#if (BRAND_STRING1 == TRUE) || (BRAND_STRING2 == TRUE)
(PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonVoid,
#else
(PF_CPU_NUMBER_OF_PHYSICAL_CORES) CommonAssert,
#endif
#if GET_AP_MAILBOX_FROM_HW == TRUE
(PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
#else
(PF_CPU_AMD_GET_AP_MAILBOX_FROM_HARDWARE) CommonAssert,
#endif
#if SET_AP_CORE_NUMBER == TRUE
(PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
#else
(PF_CPU_SET_AP_CORE_NUMBER) CommonAssert,
#endif
#if GET_AP_CORE_NUMBER == TRUE
(PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
#else
(PF_CPU_GET_AP_CORE_NUMBER) CommonAssert,
#endif
#if TRANSFER_AP_CORE_NUMBER == TRUE
(PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
#else
(PF_CPU_TRANSFER_AP_CORE_NUMBER) CommonAssert,
#endif
#if ID_POSITION_INITIAL_APICID == TRUE
F15CpuAmdCoreIdPositionInInitialApicId,
#else
(PF_CORE_ID_POSITION_IN_INITIAL_APIC_ID) CommonAssert,
#endif
#if SAVE_FEATURES == TRUE
// F15SaveFeatures,
(PF_CPU_SAVE_FEATURES) CommonVoid,
#else
(PF_CPU_SAVE_FEATURES) CommonAssert,
#endif
#if WRITE_FEATURES == TRUE
// F15WriteFeatures,
(PF_CPU_WRITE_FEATURES) CommonVoid,
#else
(PF_CPU_WRITE_FEATURES) CommonAssert,
#endif
#if SET_WARM_RESET_FLAG == TRUE
F15SetAgesaWarmResetFlag,
#else
(PF_CPU_SET_WARM_RESET_FLAG) CommonAssert,
#endif
#if GET_WARM_RESET_FLAG == TRUE
F15GetAgesaWarmResetFlag,
#else
(PF_CPU_GET_WARM_RESET_FLAG) CommonAssert,
#endif
#if BRAND_STRING1 == TRUE
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if BRAND_STRING2 == TRUE
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES == TRUE
GetEmptyArray,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PATCHES_EQUIVALENCE_TABLE == TRUE
GetEmptyArray,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_CACHE_INFO == TRUE
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonVoid,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_SYSTEM_PM_TABLE == TRUE
GetEmptyArray,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_WHEA_INIT == TRUE
GetF15WheaInitData,
#else
(PF_CPU_GET_FAMILY_SPECIFIC_ARRAY) CommonAssert,
#endif
#if GET_PLATFORM_TYPE_SPECIFIC_INFO == TRUE
(PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonReturnAgesaSuccess,
#else
(PF_CPU_GET_PLATFORM_TYPE_SPECIFIC_INFO) CommonAssert,
#endif
#if IS_NB_PSTATE_ENABLED == TRUE
F15IsNbPstateEnabled,
#else
(PF_IS_NB_PSTATE_ENABLED) CommonAssert,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
F15NextLinkHasHtPhyFeats,
#else
(PF_NEXT_LINK_HAS_HTFPY_FEATS) CommonReturnFalse,
#endif
#if (BASE_FAMILY_HT_PCI == TRUE)
F15SetHtPhyRegister,
#else
(PF_SET_HT_PHY_REGISTER) CommonVoid,
#endif
#if BASE_FAMILY_PCI == TRUE
F15GetNextHtLinkFeatures,
#else
(PF_GET_NEXT_HT_LINK_FEATURES) CommonAssert,
#endif
#if USES_REGISTER_TABLES == TRUE
(REGISTER_TABLE **) F15UnknownRegisterTables,
#else
NULL,
#endif
#if USES_REGISTER_TABLES == TRUE
(TABLE_ENTRY_TYPE_DESCRIPTOR *) F15UnknownTableEntryTypeDescriptors,
#else
NULL,
#endif
NULL,
NULL,
InitCacheEnabled,
#if AGESA_ENTRY_INIT_EARLY == TRUE
(PF_GET_EARLY_INIT_TABLE) CommonVoid
#else
(PF_GET_EARLY_INIT_TABLE) CommonVoid
#endif
};
// Family 15h maximum base address is 48 bits. Limit BLDCFG to 48 bits, if appropriate.
#if (FAMILY_MMIO_BASE_MASK < 0xFFFF000000000000ull)
#undef FAMILY_MMIO_BASE_MASK
#define FAMILY_MMIO_BASE_MASK (0xFFFF000000000000ull)
#endif
#undef OPT_F15_ID_TABLE
#define OPT_F15_ID_TABLE {0x15, {AMD_FAMILY_15, AMD_F15_UNKNOWN}, F15LogicalIdTable, (sizeof (F15LogicalIdTable) / sizeof (F15LogicalIdTable[0]))},
#define OPT_F15_UNKNOWN_CPU {AMD_FAMILY_15, &cpuF15UnknownServices},
#undef OPT_F15_TABLE
#define OPT_F15_TABLE OPT_F15_OR_CPU OPT_F15_UNKNOWN_CPU
#if OPTION_G34_SOCKET_SUPPORT == TRUE
#define F15_G34_BRANDSTRING1 NULL,
#define F15_G34_BRANDSTRING2 NULL,
#else
#define F15_G34_BRANDSTRING1
#define F15_G34_BRANDSTRING2
#endif
#if OPTION_C32_SOCKET_SUPPORT == TRUE
#define F15_C32_BRANDSTRING1 NULL,
#define F15_C32_BRANDSTRING2 NULL,
#else
#define F15_C32_BRANDSTRING1
#define F15_C32_BRANDSTRING2
#endif
#if OPTION_AM3_SOCKET_SUPPORT == TRUE
#define F15_AM3_BRANDSTRING1 NULL,
#define F15_AM3_BRANDSTRING2 NULL,
#else
#define F15_AM3_BRANDSTRING1
#define F15_AM3_BRANDSTRING2
#endif
#if BRAND_STRING1 == TRUE
CONST CPU_BRAND_TABLE ROMDATA *F15BrandIdString1Tables[] =
{
F15_G34_BRANDSTRING1
F15_C32_BRANDSTRING1
F15_AM3_BRANDSTRING1
};
CONST UINT8 F15BrandIdString1TableCount = (sizeof (F15BrandIdString1Tables) / sizeof (F15BrandIdString1Tables[0]));
#endif
#if BRAND_STRING2 == TRUE
CONST CPU_BRAND_TABLE ROMDATA *F15BrandIdString2Tables[] =
{
F15_G34_BRANDSTRING2
F15_C32_BRANDSTRING2
F15_AM3_BRANDSTRING2
};
CONST UINT8 F15BrandIdString2TableCount = (sizeof (F15BrandIdString2Tables) / sizeof (F15BrandIdString2Tables[0]));
#endif
CONST PF_CPU_GET_SUBFAMILY_ID_ARRAY ROMDATA F15LogicalIdTable[] =
{
OPT_F15_OR_ID
};
#endif // _OPTION_FAMILY_15H_INSTALL_H_

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src/vendorcode/amd/agesa/f12/Include/OptionFchInstall.h Executable file
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/*********************************************************************************
;
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*********************************************************************************/
#ifndef _OPTION_FCH_INSTALL_H_
#define _OPTION_FCH_INSTALL_H_
#include "AmdFch.h"
#ifndef FCH_SUPPORT
#define FCH_SUPPORT FALSE
#endif
/* ACPI block register offset definitions */
#define PM1_STATUS_OFFSET 0x00
#define PM1_ENABLE_OFFSET 0x02
#define PM_CONTROL_OFFSET 0x04
#define PM_TIMER_OFFSET 0x08
#define CPU_CONTROL_OFFSET 0x10
#define EVENT_STATUS_OFFSET 0x20
#define EVENT_ENABLE_OFFSET 0x24
#if FCH_SUPPORT == TRUE
/*
* FCH subfunctions
*/
#ifdef AGESA_ENTRY_INIT_RESET
#if AGESA_ENTRY_INIT_RESET == TRUE
extern FCH_TASK_ENTRY FchInitResetHwAcpiP;
extern FCH_TASK_ENTRY FchInitResetHwAcpi;
extern FCH_TASK_ENTRY FchInitResetAb;
extern FCH_TASK_ENTRY FchInitResetSpi;
extern FCH_TASK_ENTRY FchInitResetGec;
extern FCH_TASK_ENTRY FchInitResetSata;
extern FCH_TASK_ENTRY FchInitResetLpc;
extern FCH_TASK_ENTRY FchInitResetPcib;
extern FCH_TASK_ENTRY FchInitResetPcie;
extern FCH_TASK_ENTRY FchInitResetGpp;
extern FCH_TASK_ENTRY FchInitResetUsb;
extern FCH_TASK_ENTRY FchInitResetEhci;
extern FCH_TASK_ENTRY FchInitResetOhci;
extern FCH_TASK_ENTRY FchInitResetXhci;
extern FCH_TASK_ENTRY FchInitResetImc;
#endif
#endif
#ifdef AGESA_ENTRY_INIT_ENV
#if AGESA_ENTRY_INIT_ENV == TRUE
extern FCH_TASK_ENTRY FchInitEnvUsbXhci;
extern FCH_TASK_ENTRY FchInitEnvUsbOhci;
extern FCH_TASK_ENTRY FchInitEnvUsbEhci;
extern FCH_TASK_ENTRY FchInitEnvUsb;
extern FCH_TASK_ENTRY FchInitEnvAb;
extern FCH_TASK_ENTRY FchInitEnvGpp;
extern FCH_TASK_ENTRY FchInitEnvPcie;
extern FCH_TASK_ENTRY FchInitEnvPcib;
extern FCH_TASK_ENTRY FchInitEnvHwAcpiP;
extern FCH_TASK_ENTRY FchInitEnvHwAcpi;
extern FCH_TASK_ENTRY FchInitEnvAbSpecial;
extern FCH_TASK_ENTRY FchInitEnvSpi;
extern FCH_TASK_ENTRY FchInitEnvGec;
extern FCH_TASK_ENTRY FchInitEnvSata;
extern FCH_TASK_ENTRY FchInitEnvIde;
extern FCH_TASK_ENTRY FchInitEnvSd;
extern FCH_TASK_ENTRY FchInitEnvIr;
extern FCH_TASK_ENTRY FchInitEnvAzalia;
extern FCH_TASK_ENTRY FchInitEnvHwm;
extern FCH_TASK_ENTRY FchInitEnvImc;
#endif
#endif
#ifdef AGESA_ENTRY_INIT_MID
#if AGESA_ENTRY_INIT_MID == TRUE
extern FCH_TASK_ENTRY FchInitMidHwm;
extern FCH_TASK_ENTRY FchInitMidAzalia;
extern FCH_TASK_ENTRY FchInitMidGec;
extern FCH_TASK_ENTRY FchInitMidSata;
extern FCH_TASK_ENTRY FchInitMidIde;
extern FCH_TASK_ENTRY FchInitMidAb;
extern FCH_TASK_ENTRY FchInitMidUsb;
extern FCH_TASK_ENTRY FchInitMidUsbEhci;
extern FCH_TASK_ENTRY FchInitMidUsbOhci;
extern FCH_TASK_ENTRY FchInitMidUsbXhci;
extern FCH_TASK_ENTRY FchInitMidImc;
#endif
#endif
#ifdef AGESA_ENTRY_INIT_LATE
#if AGESA_ENTRY_INIT_LATE == TRUE
extern FCH_TASK_ENTRY FchInitLateHwAcpi;
extern FCH_TASK_ENTRY FchInitLateSpi;
extern FCH_TASK_ENTRY FchInitLateGec;
extern FCH_TASK_ENTRY FchInitLateSata;
extern FCH_TASK_ENTRY FchInitLateIde;
extern FCH_TASK_ENTRY FchInitLatePcib;
extern FCH_TASK_ENTRY FchInitLateAb;
extern FCH_TASK_ENTRY FchInitLatePcie;
extern FCH_TASK_ENTRY FchInitLateGpp;
extern FCH_TASK_ENTRY FchInitLateUsb;
extern FCH_TASK_ENTRY FchInitLateUsbEhci;
extern FCH_TASK_ENTRY FchInitLateUsbOhci;
extern FCH_TASK_ENTRY FchInitLateUsbXhci;
extern FCH_TASK_ENTRY FchInitLateImc;
extern FCH_TASK_ENTRY FchInitLateAzalia;
extern FCH_TASK_ENTRY FchInitLateHwm;
#endif
#endif
extern FCH_TASK_ENTRY FchTaskDummy;
/* FCH Interface entries */
extern FCH_INIT CommonFchInitStub;
/* FCH Interface entries */
#ifdef AGESA_ENTRY_INIT_RESET
#if AGESA_ENTRY_INIT_RESET == TRUE
extern FCH_INIT FchInitReset;
extern FCH_INIT FchResetConstructor;
#define FP_FCH_INIT_RESET &FchInitReset
#define FP_FCH_INIT_RESET_CONSTRUCT &FchResetConstructor
#else
#define FP_FCH_INIT_RESET &CommonFchInitStub
#define FP_FCH_INIT_RESET_CONSTRUCT &CommonFchInitStub
#endif
#endif
#ifdef AGESA_ENTRY_INIT_ENV
#if AGESA_ENTRY_INIT_ENV == TRUE
extern FCH_INIT FchInitEnv;
extern FCH_INIT FchEnvConstructor;
#define FP_FCH_INIT_ENV &FchInitEnv
#define FP_FCH_INIT_ENV_CONSTRUCT &FchEnvConstructor
#else
#define FP_FCH_INIT_ENV &CommonFchInitStub
#define FP_FCH_INIT_ENV_CONSTRUCT &CommonFchInitStub
#endif
#endif
#ifdef AGESA_ENTRY_INIT_MID
#if AGESA_ENTRY_INIT_MID == TRUE
extern FCH_INIT FchInitMid;
extern FCH_INIT FchMidConstructor;
#define FP_FCH_INIT_MID &FchInitMid
#define FP_FCH_INIT_MID_CONSTRUCT &FchMidConstructor
#else
#define FP_FCH_INIT_MID &CommonFchInitStub
#define FP_FCH_INIT_MID_CONSTRUCT &CommonFchInitStub
#endif
#endif
#ifdef AGESA_ENTRY_INIT_LATE
#if AGESA_ENTRY_INIT_LATE == TRUE
extern FCH_INIT FchInitLate;
extern FCH_INIT FchLateConstructor;
#define FP_FCH_INIT_LATE &FchInitLate
#define FP_FCH_INIT_LATE_CONSTRUCT &FchLateConstructor
#else
#define FP_FCH_INIT_LATE &CommonFchInitStub
#define FP_FCH_INIT_LATE_CONSTRUCT &CommonFchInitStub
#endif
#endif
/* FCH subcomponent build options */
#undef FCH_NO_HWACPI_SUPPORT
#undef FCH_NO_AB_SUPPORT
#undef FCH_NO_SPI_SUPPORT
#undef FCH_NO_GEC_SUPPORT
#undef FCH_NO_SATA_SUPPORT
#undef FCH_NO_IDE_SUPPORT
#undef FCH_NO_LPC_SUPPORT
#undef FCH_NO_PCIB_SUPPORT
#undef FCH_NO_PCIE_SUPPORT
#undef FCH_NO_GPP_SUPPORT
#undef FCH_NO_USB_SUPPORT
#undef FCH_NO_EHCI_SUPPORT
#undef FCH_NO_OHCI_SUPPORT
#undef FCH_NO_XHCI_SUPPORT
#undef FCH_NO_IMC_SUPPORT
#undef FCH_NO_SD_SUPPORT
#undef FCH_NO_IR_SUPPORT
#undef FCH_NO_AZALIA_SUPPORT
#undef FCH_NO_HWM_SUPPORT
// Following are determined by silicon characteristics
#if (OPTION_FAMILY14H_KR == TRUE)
#define FCH_NO_GPP_SUPPORT TRUE
#define FCH_NO_PCIB_SUPPORT TRUE
#define FCH_NO_PCIE_SUPPORT TRUE
#else
#if (OPTION_FAMILY15H_TN == TRUE)
//#define FCH_NO_GEC_SUPPORT TRUE
#else
#error FCH_SUPPORT: No chip type selected.
#endif
#endif
//
// Installable blocks depending on build switches
//
#ifndef FCH_NO_HWACPI_SUPPORT
#define BLOCK_HWACPI_SIZE sizeof (FCH_ACPI)
#define InstallFchInitResetHwAcpiP &FchInitResetHwAcpiP
#define InstallFchInitResetHwAcpi &FchInitResetHwAcpi
#define InstallFchInitEnvHwAcpiP &FchInitEnvHwAcpiP
#define InstallFchInitEnvHwAcpi &FchInitEnvHwAcpi
#define InstallFchInitMidHwAcpi &FchTaskDummy
#define InstallFchInitLateHwAcpi &FchInitLateHwAcpi
#else
#define BLOCK_HWACPI_SIZE 0
#define InstallFchInitResetHwAcpiP &FchTaskDummy
#define InstallFchInitResetHwAcpi &FchTaskDummy
#define InstallFchInitEnvHwAcpi &FchTaskDummy
#define InstallFchInitMidHwAcpi &FchTaskDummy
#define InstallFchInitLateHwAcpi &FchTaskDummy
#endif
#ifndef FCH_NO_AB_SUPPORT
#define BLOCK_AB_SIZE sizeof (FCH_AB)
#define InstallFchInitResetAb &FchInitResetAb
#define InstallFchInitEnvAb &FchInitEnvAb
#define InstallFchInitEnvAbS &FchInitEnvAbSpecial
#define InstallFchInitMidAb &FchInitMidAb
#define InstallFchInitLateAb &FchInitLateAb
#else
#define BLOCK_AB_SIZE 0
#define InstallFchInitResetAb &FchTaskDummy
#define InstallFchInitEnvAb &FchTaskDummy
#define InstallFchInitEnvAbS &FchTaskDummy
#define InstallFchInitMidAb &FchTaskDummy
#define InstallFchInitLateAb &FchTaskDummy
#endif
#ifndef FCH_NO_SPI_SUPPORT
#define BLOCK_SPI_SIZE sizeof (FCH_SPI)
#define InstallFchInitResetSpi &FchInitResetSpi
#define InstallFchInitEnvSpi &FchInitEnvSpi
#define InstallFchInitMidSpi &FchTaskDummy
#define InstallFchInitLateSpi &FchInitLateSpi
#else
#define BLOCK_SPI_SIZE 0
#define InstallFchInitResetSpi &FchTaskDummy
#define InstallFchInitEnvSpi &FchTaskDummy
#define InstallFchInitMidSpi &FchTaskDummy
#define InstallFchInitLateSpi &FchTaskDummy
#endif
#ifndef FCH_NO_GEC_SUPPORT
#define BLOCK_GEC_SIZE sizeof (FCH_GEC)
#define InstallFchInitResetGec &FchInitResetGec
#define InstallFchInitEnvGec &FchInitEnvGec
#define InstallFchInitMidGec &FchInitMidGec
#define InstallFchInitLateGec &FchInitLateGec
#else
#define BLOCK_GEC_SIZE 0
#define InstallFchInitResetGec &FchTaskDummy
#define InstallFchInitEnvGec &FchTaskDummy
#define InstallFchInitMidGec &FchTaskDummy
#define InstallFchInitLateGec &FchTaskDummy
#endif
#ifndef FCH_NO_SATA_SUPPORT
#define BLOCK_SATA_SIZE sizeof (FCH_SATA)
#define InstallFchInitResetSata &FchInitResetSata
#define InstallFchInitEnvSata &FchInitEnvSata
#define InstallFchInitMidSata &FchInitMidSata
#define InstallFchInitLateSata &FchInitLateSata
#else
#define BLOCK_SATA_SIZE 0
#define InstallFchInitResetSata &FchTaskDummy
#define InstallFchInitEnvSata &FchTaskDummy
#define InstallFchInitMidSata &FchTaskDummy
#define InstallFchInitLateSata &FchTaskDummy
#endif
#ifndef FCH_NO_IDE_SUPPORT
#define BLOCK_IDE_SIZE sizeof (FCH_IDE)
#define InstallFchInitResetIde &FchTaskDummy
#define InstallFchInitEnvIde &FchInitEnvIde
#define InstallFchInitMidIde &FchInitMidIde
#define InstallFchInitLateIde &FchInitLateIde
#else
#define BLOCK_IDE_SIZE 0
#define InstallFchInitResetIde &FchTaskDummy
#define InstallFchInitEnvIde &FchTaskDummy
#define InstallFchInitMidIde &FchTaskDummy
#define InstallFchInitLateIde &FchTaskDummy
#endif
#ifndef FCH_NO_LPC_SUPPORT
#define BLOCK_LPC_SIZE sizeof (FCH_LPC)
#define InstallFchInitResetLpc &FchInitResetLpc
#define InstallFchInitEnvLpc &FchTaskDummy
#define InstallFchInitMidLpc &FchTaskDummy
#define InstallFchInitLateLpc &FchTaskDummy
#else
#define BLOCK_LPC_SIZE 0
#define InstallFchInitResetLpc &FchTaskDummy
#define InstallFchInitEnvLpc &FchTaskDummy
#define InstallFchInitMidLpc &FchTaskDummy
#define InstallFchInitLateLpc &FchTaskDummy
#endif
#ifndef FCH_NO_PCIB_SUPPORT
#define BLOCK_PCIB_SIZE sizeof (FCH_PCIB)
#define InstallFchInitResetPcib &FchInitResetPcib
#define InstallFchInitEnvPcib &FchInitEnvPcib
#define InstallFchInitMidPcib &FchTaskDummy
#define InstallFchInitLatePcib &FchInitLatePcib
#else
#define BLOCK_PCIB_SIZE 0
#define InstallFchInitResetPcib &FchTaskDummy
#define InstallFchInitEnvPcib &FchTaskDummy
#define InstallFchInitMidPcib &FchTaskDummy
#define InstallFchInitLatePcib &FchTaskDummy
#endif
#ifndef FCH_NO_PCIE_SUPPORT
#define InstallFchInitResetPcie &FchInitResetPcie
#define InstallFchInitEnvPcie &FchInitEnvPcie
#define InstallFchInitMidPcie &FchTaskDummy
#define InstallFchInitLatePcie &FchInitLatePcie
#else
#define InstallFchInitResetPcie &FchTaskDummy
#define InstallFchInitEnvPcie &FchTaskDummy
#define InstallFchInitMidPcie &FchTaskDummy
#define InstallFchInitLatePcie &FchTaskDummy
#endif
#ifndef FCH_NO_GPP_SUPPORT
#define BLOCK_GPP_SIZE sizeof (FCH_GPP)
#define InstallFchInitResetGpp &FchInitResetGpp
#define InstallFchInitEnvGpp &FchInitEnvGpp
#define InstallFchInitMidGpp &FchTaskDummy
#define InstallFchInitLateGpp &FchInitLateGpp
#else
#define BLOCK_GPP_SIZE 0
#define InstallFchInitResetGpp &FchTaskDummy
#define InstallFchInitEnvGpp &FchTaskDummy
#define InstallFchInitMidGpp &FchTaskDummy
#define InstallFchInitLateGpp &FchTaskDummy
#endif
#ifndef FCH_NO_USB_SUPPORT
#define BLOCK_USB_SIZE sizeof (FCH_USB)
#define InstallFchInitResetUsb &FchInitResetUsb
#define InstallFchInitEnvUsb &FchInitEnvUsb
#define InstallFchInitMidUsb &FchInitMidUsb
#define InstallFchInitLateUsb &FchInitLateUsb
#else
#define BLOCK_USB_SIZE 0
#define InstallFchInitResetUsb &FchTaskDummy
#define InstallFchInitEnvUsb &FchTaskDummy
#define InstallFchInitMidUsb &FchTaskDummy
#define InstallFchInitLateUsb &FchTaskDummy
#endif
#ifndef FCH_NO_EHCI_SUPPORT
#define InstallFchInitResetUsbEhci &FchInitResetEhci
#define InstallFchInitEnvUsbEhci &FchInitEnvUsbEhci
#define InstallFchInitMidUsbEhci &FchInitMidUsbEhci
#define InstallFchInitLateUsbEhci &FchInitLateUsbEhci
#else
#define InstallFchInitResetUsbEhci &FchTaskDummy
#define InstallFchInitEnvUsbEhci &FchTaskDummy
#define InstallFchInitMidUsbEhci &FchTaskDummy
#define InstallFchInitLateUsbEhci &FchTaskDummy
#endif
#ifndef FCH_NO_OHCI_SUPPORT
#define InstallFchInitResetUsbOhci &FchInitResetOhci
#define InstallFchInitEnvUsbOhci &FchInitEnvUsbOhci
#define InstallFchInitMidUsbOhci &FchInitMidUsbOhci
#define InstallFchInitLateUsbOhci &FchInitLateUsbOhci
#else
#define InstallFchInitResetUsbOhci &FchTaskDummy
#define InstallFchInitEnvUsbOhci &FchTaskDummy
#define InstallFchInitMidUsbOhci &FchTaskDummy
#define InstallFchInitLateUsbOhci &FchTaskDummy
#endif
#ifndef FCH_NO_XHCI_SUPPORT
#define InstallFchInitResetUsbXhci &FchInitResetXhci
#define InstallFchInitEnvUsbXhci &FchInitEnvUsbXhci
#define InstallFchInitMidUsbXhci &FchInitMidUsbXhci
#define InstallFchInitLateUsbXhci &FchInitLateUsbXhci
#else
#define InstallFchInitResetUsbXhci &FchTaskDummy
#define InstallFchInitEnvUsbXhci &FchTaskDummy
#define InstallFchInitMidUsbXhci &FchTaskDummy
#define InstallFchInitLateUsbXhci &FchTaskDummy
#endif
#ifndef FCH_NO_IMC_SUPPORT
#define BLOCK_IMC_SIZE sizeof (FCH_IMC)
#define InstallFchInitResetImc &FchInitResetImc
#define InstallFchInitEnvImc &FchInitEnvImc
#define InstallFchInitMidImc &FchInitMidImc
#define InstallFchInitLateImc &FchInitLateImc
#else
#define BLOCK_IMC_SIZE 0
#define InstallFchInitResetImc &FchTaskDummy
#define InstallFchInitEnvImc &FchTaskDummy
#define InstallFchInitMidImc &FchTaskDummy
#define InstallFchInitLateImc &FchTaskDummy
#endif
#ifndef FCH_NO_SD_SUPPORT
#define BLOCK_SD_SIZE sizeof (FCH_SD)
#define InstallFchInitResetSd &FchTaskDummy
#define InstallFchInitEnvSd &FchInitEnvSd
#define InstallFchInitMidSd &FchTaskDummy
#define InstallFchInitLateSd &FchTaskDummy
#else
#define BLOCK_SD_SIZE 0
#define InstallFchInitResetSd &FchTaskDummy
#define InstallFchInitEnvSd &FchTaskDummy
#define InstallFchInitMidSd &FchTaskDummy
#define InstallFchInitLateSd &FchTaskDummy
#endif
#ifndef FCH_NO_IR_SUPPORT
#define BLOCK_IR_SIZE sizeof (FCH_IR)
#define InstallFchInitResetIr &FchTaskDummy
#define InstallFchInitEnvIr &FchInitEnvIr
#define InstallFchInitMidIr &FchTaskDummy
#define InstallFchInitLateIr &FchTaskDummy
#else
#define BLOCK_IR_SIZE 0
#define InstallFchInitResetIr &FchTaskDummy
#define InstallFchInitEnvIr &FchTaskDummy
#define InstallFchInitMidIr &FchTaskDummy
#define InstallFchInitLateIr &FchTaskDummy
#endif
#ifndef FCH_NO_AZALIA_SUPPORT
#define BLOCK_AZALIA_SIZE sizeof (FCH_AZALIA)
#define InstallFchInitResetAzalia &FchTaskDummy
#define InstallFchInitEnvAzalia &FchInitEnvAzalia
#define InstallFchInitMidAzalia &FchInitMidAzalia
#define InstallFchInitLateAzalia &FchInitLateAzalia
#else
#define BLOCK_AZALIA_SIZE 0
#define InstallFchInitResetAzalia &FchTaskDummy
#define InstallFchInitEnvAzalia &FchTaskDummy
#define InstallFchInitMidAzalia &FchTaskDummy
#define InstallFchInitLateAzalia &FchTaskDummy
#endif
#ifndef FCH_NO_HWM_SUPPORT
#define BLOCK_HWM_SIZE sizeof (FCH_HWM)
#define InstallFchInitResetHwm &FchTaskDummy
#define InstallFchInitEnvHwm &FchInitEnvHwm
#define InstallFchInitMidHwm &FchInitMidHwm
#define InstallFchInitLateHwm &FchInitLateHwm
#else
#define InstallFchInitResetHwm &FchTaskDummy
#define InstallFchInitEnvHwm &FchTaskDummy
#define InstallFchInitMidHwm &FchTaskDummy
#define InstallFchInitLateHwm &FchTaskDummy
#endif
#define BLOCK_SMBUS_SIZE sizeof (FCH_SMBUS)
#define BLOCK_HPET_SIZE sizeof (FCH_HPET)
#define BLOCK_GCPU_SIZE sizeof (FCH_GCPU)
#define BLOCK_SDB_SIZE sizeof (FCH_SERIALDB)
#define BLOCK_MISC_SIZE sizeof (FCH_MISC)
// Optionally declare OEM hooks after each phase
#ifndef FCH_INIT_RESET_HOOK
#define InstallFchInitResetHook FchTaskDummy
#else
#define InstallFchInitResetHook OemFchInitResetHook
#endif
//
// Define FCH build time options and configurations
//
#ifdef BLDCFG_SMBUS0_BASE_ADDRESS
#define CFG_SMBUS0_BASE_ADDRESS BLDCFG_SMBUS0_BASE_ADDRESS
#else
#define CFG_SMBUS0_BASE_ADDRESS DFLT_SMBUS0_BASE_ADDRESS
#endif
#ifdef BLDCFG_SMBUS1_BASE_ADDRESS
#define CFG_SMBUS1_BASE_ADDRESS BLDCFG_SMBUS1_BASE_ADDRESS
#else
#define CFG_SMBUS1_BASE_ADDRESS DFLT_SMBUS1_BASE_ADDRESS
#endif
#ifdef BLDCFG_SIO_PME_BASE_ADDRESS
#define CFG_SIO_PME_BASE_ADDRESS BLDCFG_SIO_PME_BASE_ADDRESS
#else
#define CFG_SIO_PME_BASE_ADDRESS DFLT_SIO_PME_BASE_ADDRESS
#endif
#ifdef BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS
#define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS BLDCFG_ACPI_PM1_EVT_BLOCK_ADDRESS
#else
#define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS
#endif
#ifdef BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS
#define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS BLDCFG_ACPI_PM1_CNT_BLOCK_ADDRESS
#else
#define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS
#endif
#ifdef BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS
#define CFG_ACPI_PM_TMR_BLOCK_ADDRESS BLDCFG_ACPI_PM_TMR_BLOCK_ADDRESS
#else
#define CFG_ACPI_PM_TMR_BLOCK_ADDRESS DFLT_ACPI_PM_TMR_BLOCK_ADDRESS
#endif
#ifdef BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS
#define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS BLDCFG_ACPI_CPU_CNT_BLOCK_ADDRESS
#else
#define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS
#endif
#ifdef BLDCFG_ACPI_GPE0_BLOCK_ADDRESS
#define CFG_ACPI_GPE0_BLOCK_ADDRESS BLDCFG_ACPI_GPE0_BLOCK_ADDRESS
#else
#define CFG_ACPI_GPE0_BLOCK_ADDRESS DFLT_ACPI_GPE0_BLOCK_ADDRESS
#endif
#ifdef BLDCFG_WATCHDOG_TIMER_BASE
#define CFG_WATCHDOG_TIMER_BASE BLDCFG_WATCHDOG_TIMER_BASE
#else
#define CFG_WATCHDOG_TIMER_BASE DFLT_WATCHDOG_TIMER_BASE_ADDRESS
#endif
#ifdef BLDCFG_ACPI_PMA_BLK_ADDRESS
#define CFG_ACPI_PMA_CNTBLK_ADDRESS BLDCFG_ACPI_PMA_BLK_ADDRESS
#else
#define CFG_ACPI_PMA_CNTBLK_ADDRESS DFLT_ACPI_PMA_CNT_BLK_ADDRESS
#endif
#ifdef BLDCFG_SMI_CMD_PORT_ADDRESS
#define CFG_SMI_CMD_PORT_ADDRESS BLDCFG_SMI_CMD_PORT_ADDRESS
#else
#define CFG_SMI_CMD_PORT_ADDRESS DFLT_SMI_CMD_PORT
#endif
#ifdef BLDCFG_ROM_BASE_ADDRESS
#define CFG_SPI_ROM_BASE_ADDRESS BLDCFG_ROM_BASE_ADDRESS
#else
#define CFG_SPI_ROM_BASE_ADDRESS DFLT_SPI_BASE_ADDRESS
#endif
#ifdef BLDCFG_GEC_SHADOW_ROM_BASE
#define CFG_GEC_SHADOW_ROM_BASE BLDCFG_GEC_SHADOW_ROM_BASE
#else
#define CFG_GEC_SHADOW_ROM_BASE DFLT_GEC_BASE_ADDRESS
#endif
#ifdef BLDCFG_HPET_BASE_ADDRESS
#define CFG_HPET_BASE_ADDRESS BLDCFG_HPET_BASE_ADDRESS
#else
#define CFG_HPET_BASE_ADDRESS DFLT_HPET_BASE_ADDRESS
#endif
#ifdef BLDCFG_AZALIA_SSID
#define CFG_AZALIA_SSID BLDCFG_AZALIA_SSID
#else
#define CFG_AZALIA_SSID DFLT_AZALIA_SSID
#endif
#ifdef BLDCFG_SMBUS_SSID
#define CFG_SMBUS_SSID BLDCFG_SMBUS_SSID
#else
#define CFG_SMBUS_SSID DFLT_SMBUS_SSID
#endif
#ifdef BLDCFG_IDE_SSID
#define CFG_IDE_SSID BLDCFG_IDE_SSID
#else
#define CFG_IDE_SSID DFLT_IDE_SSID
#endif
#ifdef BLDCFG_SATA_AHCI_SSID
#define CFG_SATA_AHCI_SSID BLDCFG_SATA_AHCI_SSID
#else
#define CFG_SATA_AHCI_SSID DFLT_SATA_AHCI_SSID
#endif
#ifdef BLDCFG_SATA_IDE_SSID
#define CFG_SATA_IDE_SSID BLDCFG_SATA_IDE_SSID
#else
#define CFG_SATA_IDE_SSID DFLT_SATA_IDE_SSID
#endif
#ifdef BLDCFG_SATA_RAID5_SSID
#define CFG_SATA_RAID5_SSID BLDCFG_SATA_RAID5_SSID
#else
#define CFG_SATA_RAID5_SSID DFLT_SATA_RAID5_SSID
#endif
#ifdef BLDCFG_SATA_RAID_SSID
#define CFG_SATA_RAID_SSID BLDCFG_SATA_RAID_SSID
#else
#define CFG_SATA_RAID_SSID DFLT_SATA_RAID_SSID
#endif
#ifdef BLDCFG_EHCI_SSID
#define CFG_EHCI_SSID BLDCFG_EHCI_SSID
#else
#define CFG_EHCI_SSID DFLT_EHCI_SSID
#endif
#ifdef BLDCFG_OHCI_SSID
#define CFG_OHCI_SSID BLDCFG_OHCI_SSID
#else
#define CFG_OHCI_SSID DFLT_OHCI_SSID
#endif
#ifdef BLDCFG_LPC_SSID
#define CFG_LPC_SSID BLDCFG_LPC_SSID
#else
#define CFG_LPC_SSID DFLT_LPC_SSID
#endif
#ifdef BLDCFG_FCH_GPP_LINK_CONFIG
#define CFG_FCH_GPP_LINK_CONFIG BLDCFG_FCH_GPP_LINK_CONFIG
#else
#define CFG_FCH_GPP_LINK_CONFIG DFLT_FCH_GPP_LINK_CONFIG
#endif
#ifdef BLDCFG_FCH_GPP_PORT0_PRESENT
#define CFG_FCH_GPP_PORT0_PRESENT BLDCFG_FCH_GPP_PORT0_PRESENT
#else
#define CFG_FCH_GPP_PORT0_PRESENT DFLT_FCH_GPP_PORT0_PRESENT
#endif
#ifdef BLDCFG_FCH_GPP_PORT1_PRESENT
#define CFG_FCH_GPP_PORT1_PRESENT BLDCFG_FCH_GPP_PORT1_PRESENT
#else
#define CFG_FCH_GPP_PORT1_PRESENT DFLT_FCH_GPP_PORT1_PRESENT
#endif
#ifdef BLDCFG_FCH_GPP_PORT2_PRESENT
#define CFG_FCH_GPP_PORT2_PRESENT BLDCFG_FCH_GPP_PORT2_PRESENT
#else
#define CFG_FCH_GPP_PORT2_PRESENT DFLT_FCH_GPP_PORT2_PRESENT
#endif
#ifdef BLDCFG_FCH_GPP_PORT3_PRESENT
#define CFG_FCH_GPP_PORT3_PRESENT BLDCFG_FCH_GPP_PORT3_PRESENT
#else
#define CFG_FCH_GPP_PORT3_PRESENT DFLT_FCH_GPP_PORT3_PRESENT
#endif
#ifdef BLDCFG_FCH_GPP_PORT0_HOTPLUG
#define CFG_FCH_GPP_PORT0_HOTPLUG BLDCFG_FCH_GPP_PORT0_HOTPLUG
#else
#define CFG_FCH_GPP_PORT0_HOTPLUG DFLT_FCH_GPP_PORT0_HOTPLUG
#endif
#ifdef BLDCFG_FCH_GPP_PORT1_HOTPLUG
#define CFG_FCH_GPP_PORT1_HOTPLUG BLDCFG_FCH_GPP_PORT1_HOTPLUG
#else
#define CFG_FCH_GPP_PORT1_HOTPLUG DFLT_FCH_GPP_PORT1_HOTPLUG
#endif
#ifdef BLDCFG_FCH_GPP_PORT2_HOTPLUG
#define CFG_FCH_GPP_PORT2_HOTPLUG BLDCFG_FCH_GPP_PORT2_HOTPLUG
#else
#define CFG_FCH_GPP_PORT2_HOTPLUG DFLT_FCH_GPP_PORT2_HOTPLUG
#endif
#ifdef BLDCFG_FCH_GPP_PORT3_HOTPLUG
#define CFG_FCH_GPP_PORT3_HOTPLUG BLDCFG_FCH_GPP_PORT3_HOTPLUG
#else
#define CFG_FCH_GPP_PORT3_HOTPLUG DFLT_FCH_GPP_PORT3_HOTPLUG
#endif
#ifdef AGESA_ENTRY_INIT_RESET
#if AGESA_ENTRY_INIT_RESET == TRUE
//
// Define task list for InitReset phase
//
FCH_TASK_ENTRY ROMDATA *FchInitResetTaskTable[] = {
InstallFchInitResetHwAcpiP,
InstallFchInitResetAb,
InstallFchInitResetSpi,
InstallFchInitResetGec,
InstallFchInitResetHwAcpi,
InstallFchInitResetSata,
InstallFchInitResetLpc,
InstallFchInitResetPcib,
InstallFchInitResetPcie,
InstallFchInitResetGpp,
InstallFchInitResetUsb,
InstallFchInitResetUsbEhci,
InstallFchInitResetUsbOhci,
InstallFchInitResetUsbXhci,
InstallFchInitResetImc,
NULL
};
#endif
#endif
#ifdef AGESA_ENTRY_INIT_ENV
#if AGESA_ENTRY_INIT_ENV == TRUE
//
// Define task list for InitEnv phase
//
FCH_TASK_ENTRY ROMDATA *FchInitEnvTaskTable[] = {
InstallFchInitEnvHwAcpiP,
InstallFchInitEnvPcib,
InstallFchInitEnvPcie,
InstallFchInitEnvIr,
InstallFchInitEnvHwAcpi,
InstallFchInitEnvSpi,
InstallFchInitEnvSd,
InstallFchInitEnvImc,
InstallFchInitEnvUsb,
InstallFchInitEnvUsbEhci,
InstallFchInitEnvUsbOhci,
InstallFchInitEnvUsbXhci,
InstallFchInitEnvSata,
InstallFchInitEnvIde,
InstallFchInitEnvGec,
InstallFchInitEnvAzalia,
InstallFchInitEnvAb,
InstallFchInitEnvGpp,
InstallFchInitEnvAbS,
InstallFchInitEnvHwm,
NULL
};
#endif
#endif
#ifdef AGESA_ENTRY_INIT_MID
#if AGESA_ENTRY_INIT_MID == TRUE
//
// Define task list for InitMid phase
//
FCH_TASK_ENTRY ROMDATA *FchInitMidTaskTable[] = {
InstallFchInitMidImc,
InstallFchInitMidUsb,
InstallFchInitMidUsbEhci,
InstallFchInitMidUsbOhci,
InstallFchInitMidUsbXhci,
InstallFchInitMidSata,
InstallFchInitMidIde,
InstallFchInitMidGec,
InstallFchInitMidAzalia,
InstallFchInitMidHwm,
NULL
};
#endif
#endif
#ifdef AGESA_ENTRY_INIT_LATE
#if AGESA_ENTRY_INIT_LATE == TRUE
//
// Define task list for InitLate phase
//
FCH_TASK_ENTRY ROMDATA *FchInitLateTaskTable[] = {
InstallFchInitLatePcie,
InstallFchInitLatePcib,
InstallFchInitLateSpi,
InstallFchInitLateUsb,
InstallFchInitLateUsbEhci,
InstallFchInitLateUsbOhci,
InstallFchInitLateUsbXhci,
InstallFchInitLateSata,
InstallFchInitLateIde,
InstallFchInitLateGec,
InstallFchInitLateAzalia,
InstallFchInitLateImc,
InstallFchInitLateHwm,
InstallFchInitLateGpp,
InstallFchInitLateHwAcpi,
NULL
};
#endif
#endif
#ifdef AGESA_ENTRY_INIT_ENV
#if AGESA_ENTRY_INIT_ENV == TRUE
//
// Define task list for S3 resume before PCI phase
//
FCH_TASK_ENTRY ROMDATA *FchInitS3EarlyTaskTable[] = {
InstallFchInitEnvPcie,
InstallFchInitEnvPcib,
InstallFchInitEnvIr,
InstallFchInitEnvHwAcpi,
InstallFchInitEnvSpi,
InstallFchInitEnvSd,
InstallFchInitEnvUsb,
InstallFchInitEnvSata,
InstallFchInitEnvIde,
InstallFchInitEnvGec,
InstallFchInitEnvAzalia,
InstallFchInitEnvAb,
InstallFchInitEnvGpp,
InstallFchInitEnvAbS,
NULL
};
#endif
#endif
#ifdef AGESA_ENTRY_INIT_LATE
#if AGESA_ENTRY_INIT_LATE == TRUE
//
// Define task list for S3 resume after PCI phase
//
FCH_TASK_ENTRY ROMDATA *FchInitS3LateTaskTable[] = {
InstallFchInitLatePcie,
InstallFchInitLatePcib,
InstallFchInitLateSpi,
InstallFchInitLateUsb,
InstallFchInitLateUsbEhci,
InstallFchInitLateUsbOhci,
InstallFchInitLateUsbXhci,
InstallFchInitMidSata,
InstallFchInitMidIde,
InstallFchInitMidGec,
InstallFchInitMidAzalia,
InstallFchInitLateSata,
InstallFchInitLateIde,
InstallFchInitLateHwAcpi,
InstallFchInitEnvHwm,
InstallFchInitLateHwm,
NULL
};
#endif
#endif
#else // FCH_SUPPORT == FALSE
/* FCH Interface entries */
extern FCH_INIT CommonFchInitStub;
#define FP_FCH_INIT_RESET &CommonFchInitStub
#define FP_FCH_INIT_RESET_CONSTRUCT &CommonFchInitStub
#define FP_FCH_INIT_ENV &CommonFchInitStub
#define FP_FCH_INIT_ENV_CONSTRUCT &CommonFchInitStub
#define FP_FCH_INIT_MID &CommonFchInitStub
#define FP_FCH_INIT_MID_CONSTRUCT &CommonFchInitStub
#define FP_FCH_INIT_LATE &CommonFchInitStub
#define FP_FCH_INIT_LATE_CONSTRUCT &CommonFchInitStub
#define CFG_SMBUS0_BASE_ADDRESS 0
#define CFG_SMBUS1_BASE_ADDRESS 0
#define CFG_SIO_PME_BASE_ADDRESS 0
#define CFG_ACPI_PM1_EVT_BLOCK_ADDRESS 0
#define CFG_ACPI_PM1_CNT_BLOCK_ADDRESS 0
#define CFG_ACPI_PM_TMR_BLOCK_ADDRESS 0
#define CFG_ACPI_CPU_CNT_BLOCK_ADDRESS 0
#define CFG_ACPI_GPE0_BLOCK_ADDRESS 0
#define CFG_SPI_ROM_BASE_ADDRESS 0
#define CFG_WATCHDOG_TIMER_BASE 0
#define CFG_HPET_BASE_ADDRESS 0
#define CFG_SMI_CMD_PORT_ADDRESS 0
#define CFG_ACPI_PMA_CNTBLK_ADDRESS 0
#define CFG_GEC_SHADOW_ROM_BASE 0
#define CFG_AZALIA_SSID 0
#define CFG_SMBUS_SSID 0
#define CFG_IDE_SSID 0
#define CFG_SATA_AHCI_SSID 0
#define CFG_SATA_IDE_SSID 0
#define CFG_SATA_RAID5_SSID 0
#define CFG_SATA_RAID_SSID 0
#define CFG_EHCI_SSID 0
#define CFG_OHCI_SSID 0
#define CFG_LPC_SSID 0
#define CFG_FCH_GPP_LINK_CONFIG 0
#define CFG_FCH_GPP_PORT0_PRESENT 0
#define CFG_FCH_GPP_PORT1_PRESENT 0
#define CFG_FCH_GPP_PORT2_PRESENT 0
#define CFG_FCH_GPP_PORT3_PRESENT 0
#define CFG_FCH_GPP_PORT0_HOTPLUG 0
#define CFG_FCH_GPP_PORT1_HOTPLUG 0
#define CFG_FCH_GPP_PORT2_HOTPLUG 0
#define CFG_FCH_GPP_PORT3_HOTPLUG 0
#endif
CONST BLDOPT_FCH_FUNCTION ROMDATA BldoptFchFunction = {
FP_FCH_INIT_RESET,
FP_FCH_INIT_RESET_CONSTRUCT,
FP_FCH_INIT_ENV,
FP_FCH_INIT_ENV_CONSTRUCT,
FP_FCH_INIT_MID,
FP_FCH_INIT_MID_CONSTRUCT,
FP_FCH_INIT_LATE,
FP_FCH_INIT_LATE_CONSTRUCT,
};
#endif // _OPTION_FCH_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* AMD GFX Recovery option API.
*
* Contains structures and values used to control the GfxRecovery option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_GFX_RECOVERY_H_
#define _OPTION_GFX_RECOVERY_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_GFX_RECOVERY_FEATURE (
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
#define GFX_RECOVERY_STRUCT_VERSION 0x01
/// The Option Configuration of GFX Recovery
typedef struct {
UINT16 OptGfxRecoveryVersion; ///< The version number of GFX Recovery
OPTION_GFX_RECOVERY_FEATURE *GfxRecoveryFeature; ///< The Option Feature of GFX Recovery
} OPTION_GFX_RECOVERY_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_GFX_RECOVERY_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: GfxRecovery
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_GFX_RECOVERY_INSTALL_H_
#define _OPTION_GFX_RECOVERY_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#endif // _OPTION_GFX_RECOVERY_INSTALL_H_

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src/vendorcode/amd/agesa/f12/Include/OptionGnb.h Executable file
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/* $NoKeywords:$ */
/**
* @file
*
* AMD ALIB option API.
*
* Contains structures and values used to control the ALIB option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 49316 $ @e \$Date: 2011-03-22 03:06:29 +0800 (Tue, 22 Mar 2011) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_GNB_H_
#define _OPTION_GNB_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_GNB_FEATURE (
IN AMD_CONFIG_PARAMS *StdHeader
);
/// The Option Configuration
typedef struct {
UINT64 Type; ///< Type
OPTION_GNB_FEATURE *GnbFeature; ///< The GNB Feature
} OPTION_GNB_CONFIGURATION;
/// The Build time options configuration
typedef struct {
BOOLEAN IgfxModeAsPcieEp; ///< Itegrated Gfx mode Pcie EP or Legacy
BOOLEAN LclkDeepSleepEn; ///< Default for LCLK deep sleep
BOOLEAN LclkDpmEn; ///< Default for LCLK DPM
BOOLEAN GmcPowerGateStutterOnly; ///< Force GMC power gate to stutter only
BOOLEAN SmuSclkClockGatingEnable; ///< Control SMU SCLK gating
BOOLEAN PcieAspmBlackListEnable; ///< Control Pcie Aspm Black List
BOOLEAN IvrsRelativeAddrNamesSupport; ///< Support for relative address names
BOOLEAN GnbLoadRealFuseTable; ///< Support for fuse table loading
UINT32 CfgGnbLinkReceiverDetectionPooling; ///< Receiver pooling detection time in us.
UINT32 CfgGnbLinkL0Pooling; ///< Pooling for link to get to L0 in us
UINT32 CfgGnbLinkGpioResetAssertionTime; ///< Gpio reset assertion time in us
UINT32 CfgGnbLinkResetToTrainingTime; ///< Time duration between deassert GPIO reset and release training in us
UINT8 CfgGnbTrainingAlgorithm; ///< distribution of training across interface calls
BOOLEAN CfgForceCableSafeOff; ///< Force cable safe off
BOOLEAN CfgOrbClockGatingEnable; ///< Control ORB clock gating
UINT8 CfgPciePowerGatingFlags; ///< Pcie Power gating flags
BOOLEAN CfgIocLclkClockGatingEnable; ///< Control IOC LCLK clock gating
BOOLEAN CfgIocSclkClockGatingEnable; ///< Control IOC SCLK clock gating
BOOLEAN CfgIommuL1ClockGatingEnable; ///< Control IOMMU L1 clock gating
BOOLEAN CfgIommuL2ClockGatingEnable; ///< Control IOMMU L2 clock gating
BOOLEAN CfgAltVddNb; ///< AltVDDNB support
} GNB_BUILD_OPTIONS;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_GNB_H_

592
src/vendorcode/amd/agesa/f12/Include/OptionGnbInstall.h Executable file
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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: GNB
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 49877 $ @e \$Date: 2011-03-30 13:15:18 +0800 (Wed, 30 Mar 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_GNB_INSTALL_H_
#define _OPTION_GNB_INSTALL_H_
#include "S3SaveState.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
//---------------------------------------------------------------------------------------------------
// Family installation
//---------------------------------------------------------------------------------------------------
#define GNB_TYPE_KR FALSE
#define GNB_TYPE_TN FALSE
#define GNB_TYPE_LN FALSE
#define GNB_TYPE_ON FALSE
#if (OPTION_FAMILY14H_ON == TRUE)
#undef GNB_TYPE_ON
#define GNB_TYPE_ON TRUE
#endif
#if (OPTION_FAMILY12H_LN == TRUE)
#undef GNB_TYPE_LN
#define GNB_TYPE_LN TRUE
#endif
#if (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
//---------------------------------------------------------------------------------------------------
// Service installation
//---------------------------------------------------------------------------------------------------
#include "Gnb.h"
#include "GnbPcie.h"
#define SERVICES_POINTER NULL
GNB_SERVICE *ServiceTable = SERVICES_POINTER;
//---------------------------------------------------------------------------------------------------
// BUILD options
//---------------------------------------------------------------------------------------------------
#ifndef CFG_IGFX_AS_PCIE_EP
#define CFG_IGFX_AS_PCIE_EP TRUE
#endif
#ifndef CFG_LCLK_DEEP_SLEEP_EN
#define CFG_LCLK_DEEP_SLEEP_EN TRUE
#endif
#ifndef CFG_LCLK_DPM_EN
#define CFG_LCLK_DPM_EN TRUE
#endif
#ifndef CFG_GMC_POWER_GATE_STUTTER_ONLY
#define CFG_GMC_POWER_GATE_STUTTER_ONLY FALSE
#endif
#ifndef CFG_SMU_SCLK_CLOCK_GATING_ENABLE
#if (GNB_TYPE_ON == TRUE)
#define CFG_SMU_SCLK_CLOCK_GATING_ENABLE TRUE
#else
#define CFG_SMU_SCLK_CLOCK_GATING_ENABLE FALSE
#endif
#endif
#ifndef CFG_PCIE_ASPM_BLACK_LIST_ENABLE
#define CFG_PCIE_ASPM_BLACK_LIST_ENABLE TRUE
#endif
#ifndef CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT
#define CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT FALSE
#endif
#ifndef CFG_GNB_LOAD_REAL_FUSE
#define CFG_GNB_LOAD_REAL_FUSE TRUE
#endif
#ifndef CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING
#define CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING (60 * 1000)
#endif
#ifndef CFG_GNB_PCIE_LINK_L0_POOLING
#define CFG_GNB_PCIE_LINK_L0_POOLING (60 * 1000)
#endif
#ifndef CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME
#define CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME (2 * 1000)
#endif
#ifndef CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME
#define CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME (2 * 1000)
#endif
#ifdef BLDCFG_PCIE_TRAINING_ALGORITHM
#define CFG_GNB_PCIE_TRAINING_ALGORITHM BLDCFG_PCIE_TRAINING_ALGORITHM
#else
#define CFG_GNB_PCIE_TRAINING_ALGORITHM PcieTrainingStandard
#endif
#ifndef CFG_GNB_FORCE_CABLESAFE_OFF
#define CFG_GNB_FORCE_CABLESAFE_OFF FALSE
#endif
#ifndef CFG_ORB_CLOCK_GATING_ENABLE
#define CFG_ORB_CLOCK_GATING_ENABLE TRUE
#endif
#ifndef CFG_GNB_PCIE_POWERGATING_FLAGS
#define CFG_GNB_PCIE_POWERGATING_FLAGS 0x0
#endif
#ifndef CFG_IOC_LCLK_CLOCK_GATING_ENABLE
#define CFG_IOC_LCLK_CLOCK_GATING_ENABLE FALSE
#endif
#ifndef CFG_IOC_SCLK_CLOCK_GATING_ENABLE
#define CFG_IOC_SCLK_CLOCK_GATING_ENABLE FALSE
#endif
#ifndef CFG_IOMMU_L1_CLOCK_GATING_ENABLE
#define CFG_IOMMU_L1_CLOCK_GATING_ENABLE FALSE
#endif
#ifndef CFG_IOMMU_L2_CLOCK_GATING_ENABLE
#define CFG_IOMMU_L2_CLOCK_GATING_ENABLE FALSE
#endif
#ifndef CFG_GNB_ALTVDDNB_SUPPORT
#define CFG_GNB_ALTVDDNB_SUPPORT TRUE
#endif
GNB_BUILD_OPTIONS ROMDATA GnbBuildOptions = {
CFG_IGFX_AS_PCIE_EP,
CFG_LCLK_DEEP_SLEEP_EN,
CFG_LCLK_DPM_EN,
CFG_GMC_POWER_GATE_STUTTER_ONLY,
CFG_SMU_SCLK_CLOCK_GATING_ENABLE,
CFG_PCIE_ASPM_BLACK_LIST_ENABLE,
CFG_GNB_IVRS_RELATIVE_ADDR_NAMES_SUPPORT,
CFG_GNB_LOAD_REAL_FUSE,
CFG_GNB_PCIE_LINK_RECEIVER_DETECTION_POOLING,
CFG_GNB_PCIE_LINK_L0_POOLING,
CFG_GNB_PCIE_LINK_GPIO_RESET_ASSERT_TIME,
CFG_GNB_PCIE_LINK_RESET_TO_TRAINING_TIME,
CFG_GNB_PCIE_TRAINING_ALGORITHM,
CFG_GNB_FORCE_CABLESAFE_OFF,
CFG_ORB_CLOCK_GATING_ENABLE,
CFG_GNB_PCIE_POWERGATING_FLAGS,
CFG_IOC_LCLK_CLOCK_GATING_ENABLE,
CFG_IOC_SCLK_CLOCK_GATING_ENABLE,
CFG_IOMMU_L1_CLOCK_GATING_ENABLE,
CFG_IOMMU_L2_CLOCK_GATING_ENABLE,
CFG_GNB_ALTVDDNB_SUPPORT
};
//---------------------------------------------------------------------------------------------------
// Module entries
//---------------------------------------------------------------------------------------------------
#if (AGESA_ENTRY_INIT_EARLY == TRUE)
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_NB_EARLY_INIT
#define OPTION_NB_EARLY_INIT TRUE
#endif
#if (OPTION_NB_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE NbInitAtEarly;
#define OPTION_NBINITATEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtEarly},
#else
#define OPTION_NBINITATEARLY_ENTRY
#endif
#define OPTION_GNBEARLYINTERFACETN_ENTRY
//---------------------------------------------------------------------------------------------------
// SMU init
#ifndef OPTION_SMU
#define OPTION_SMU TRUE
#endif
#if (OPTION_SMU == TRUE) && (GNB_TYPE_LN == TRUE)
OPTION_GNB_FEATURE F12NbSmuInitFeature;
#define OPTION_F12NBSMUINITFEATURE_ENTRY {AMD_FAMILY_LN, F12NbSmuInitFeature},
#else
#define OPTION_F12NBSMUINITFEATURE_ENTRY
#endif
#if (OPTION_SMU == TRUE) && (GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE F14NbSmuInitFeature;
#define OPTION_F14NBSMUINITFEATURE_ENTRY {AMD_FAMILY_ON, F14NbSmuInitFeature},
#else
#define OPTION_F14NBSMUINITFEATURE_ENTRY
#endif
#define OPTION_KRNBSMUINITFEATURE_ENTRY
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_CONFIG_INIT
#define OPTION_PCIE_CONFIG_INIT TRUE
#endif
#if (OPTION_PCIE_CONFIG_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE PcieConfigurationInit;
#define OPTION_PCIECONFIGURATIONINIT_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieConfigurationInit},
#else
#define OPTION_PCIECONFIGURATIONINIT_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_EARLY_INIT
#define OPTION_PCIE_EARLY_INIT TRUE
#endif
#if (OPTION_PCIE_EARLY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE PcieInitAtEarly;
#define OPTION_PCIEINITATEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtEarly},
#else
#define OPTION_PCIEINITATEARLY_ENTRY
#endif
#define OPTION_PCIEEARLYINTERFACETN_ENTRY
//---------------------------------------------------------------------------------------------------
OPTION_GNB_CONFIGURATION GnbEarlyFeatureTable[] = {
OPTION_NBINITATEARLY_ENTRY
OPTION_GNBEARLYINTERFACETN_ENTRY
OPTION_F12NBSMUINITFEATURE_ENTRY
OPTION_F14NBSMUINITFEATURE_ENTRY
OPTION_KRNBSMUINITFEATURE_ENTRY
OPTION_PCIECONFIGURATIONINIT_ENTRY
OPTION_PCIEINITATEARLY_ENTRY
OPTION_PCIEEARLYINTERFACETN_ENTRY
{0, NULL}
};
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_NB_EARLIER_INIT
#define OPTION_NB_EARLIER_INIT TRUE
#endif
#define OPTION_GNBEARLIERINTERFACETN_ENTRY
OPTION_GNB_CONFIGURATION GnbEarlierFeatureTable[] = {
OPTION_GNBEARLIERINTERFACETN_ENTRY
{0, NULL}
};
#endif
#if (AGESA_ENTRY_INIT_POST == TRUE)
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_CONFIG_POST_INIT
#define OPTION_GFX_CONFIG_POST_INIT TRUE
#endif
#if (OPTION_GFX_CONFIG_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE GfxConfigPostInterface;
#define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxConfigPostInterface},
#else
#define OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_POST_INIT
#define OPTION_GFX_POST_INIT TRUE
#endif
#if (OPTION_GFX_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE GfxInitAtPost;
#define OPTION_GFXINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtPost},
#else
#define OPTION_GFXINITATPOST_ENTRY
#endif
#define OPTION_GFXPOSTINTERFACETN_ENTRY
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_NB_POST_INIT
#define OPTION_NB_POST_INIT TRUE
#endif
#if (OPTION_NB_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE NbInitAtPost;
#define OPTION_NBINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtPost},
#else
#define OPTION_NBINITATPOST_ENTRY
#endif
#define OPTION_GNBPOSTINTERFACETN_ENTRY
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_POST_EALRY_INIT
#define OPTION_PCIE_POST_EALRY_INIT TRUE
#endif
#if (OPTION_PCIE_POST_EALRY_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE PcieInitAtPostEarly;
#define OPTION_PCIEINITATPOSTEARLY_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtPostEarly},
#else
#define OPTION_PCIEINITATPOSTEARLY_ENTRY
#endif
#define OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_POST_INIT
#define OPTION_PCIE_POST_INIT TRUE
#endif
#if (OPTION_PCIE_POST_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE PcieInitAtPost;
#define OPTION_PCIEINITATPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtPost},
#else
#define OPTION_PCIEINITATPOST_ENTRY
#endif
#define OPTION_PCIEPOSTINTERFACETN_ENTRY
//---------------------------------------------------------------------------------------------------
OPTION_GNB_CONFIGURATION GnbPostFeatureTable[] = {
OPTION_PCIEINITATPOSTEARLY_ENTRY
OPTION_PCIEPOSTEARLYINTERFACETN_ENTRY
OPTION_GFXCONFIGPOSTINTERFACE_ENTRY
OPTION_GFXINITATPOST_ENTRY
OPTION_GFXPOSTINTERFACETN_ENTRY
{0, NULL}
};
OPTION_GNB_CONFIGURATION GnbPostAfterDramFeatureTable[] = {
OPTION_NBINITATPOST_ENTRY
OPTION_GNBPOSTINTERFACETN_ENTRY
OPTION_PCIEINITATPOST_ENTRY
OPTION_PCIEPOSTINTERFACETN_ENTRY
{0, NULL}
};
#endif
#if (AGESA_ENTRY_INIT_ENV == TRUE)
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_FUSE_TABLE_INIT
#define OPTION_FUSE_TABLE_INIT TRUE
#endif
#if (OPTION_FUSE_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE NbFuseTableFeature;
#define OPTION_NBFUSETABLEFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbFuseTableFeature},
#else
#define OPTION_NBFUSETABLEFEATURE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_NB_ENV_INIT
#define OPTION_NB_ENV_INIT TRUE
#endif
#if (OPTION_NB_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE NbInitAtEnv;
#define OPTION_NBINITATENVT_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtEnv},
#else
#define OPTION_NBINITATENVT_ENTRY
#endif
#define OPTION_GNBENVINTERFACETN_ENTRY
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_CONFIG_ENV_INIT
#define OPTION_GFX_CONFIG_ENV_INIT TRUE
#endif
#if (OPTION_GFX_CONFIG_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE GfxConfigEnvInterface;
#define OPTION_GFXCONFIGENVINTERFACE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxConfigEnvInterface},
#else
#define OPTION_GFXCONFIGENVINTERFACE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_ENV_INIT
#define OPTION_GFX_ENV_INIT TRUE
#endif
#if (OPTION_GFX_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE GfxInitAtEnvPost;
#define OPTION_GFXINITATENVPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtEnvPost},
#else
#define OPTION_GFXINITATENVPOST_ENTRY
#endif
#define OPTION_GFXENVINTERFACETN_ENTRY
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_POWER_GATE
#define OPTION_POWER_GATE TRUE
#endif
#if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE)
OPTION_GNB_FEATURE F12NbPowerGateFeature;
#define OPTION_F12NBPOWERGATEFEATURE_ENTRY {AMD_FAMILY_LN, F12NbPowerGateFeature},
#else
#define OPTION_F12NBPOWERGATEFEATURE_ENTRY
#endif
#if (OPTION_POWER_GATE == TRUE) && (GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE F14NbPowerGateFeature;
#define OPTION_F14NBPOWERGATEFEATURE_ENTRY {AMD_FAMILY_ON, F14NbPowerGateFeature},
#else
#define OPTION_F14NBPOWERGATEFEATURE_ENTRY
#endif
#define OPTION_KRNBPOWERGATEFEATURE_ENTRY
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_ENV_INIT
#define OPTION_PCIE_ENV_INIT TRUE
#endif
#if (OPTION_PCIE_ENV_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE PcieInitAtEnv;
#define OPTION_PCIEINITATENV_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtEnv},
#else
#define OPTION_PCIEINITATENV_ENTRY
#endif
#define OPTION_PCIEENVINTERFACETN_ENTRY
//---------------------------------------------------------------------------------------------------
OPTION_GNB_CONFIGURATION GnbEnvFeatureTable[] = {
OPTION_NBFUSETABLEFEATURE_ENTRY
OPTION_NBINITATENVT_ENTRY
OPTION_GNBENVINTERFACETN_ENTRY
OPTION_PCIEINITATENV_ENTRY
OPTION_PCIEENVINTERFACETN_ENTRY
OPTION_GFXCONFIGENVINTERFACE_ENTRY
OPTION_GFXINITATENVPOST_ENTRY
OPTION_GFXENVINTERFACETN_ENTRY
OPTION_F12NBPOWERGATEFEATURE_ENTRY
OPTION_F14NBPOWERGATEFEATURE_ENTRY
OPTION_KRNBPOWERGATEFEATURE_ENTRY
{0, NULL}
};
#endif
#if (AGESA_ENTRY_INIT_MID == TRUE)
//---------------------------------------------------------------------------------------------------
#ifndef OPTOIN_GNB_CABLESAFE
#define OPTOIN_GNB_CABLESAFE TRUE
#endif
#if (OPTOIN_GNB_CABLESAFE == TRUE) && (GNB_TYPE_LN == TRUE)
OPTION_GNB_FEATURE GnbCableSafeEntry;
#define OPTION_GNBCABLESAFEENTRY_ENTRY {AMD_FAMILY_LN, GnbCableSafeEntry},
#else
#define OPTION_GNBCABLESAFEENTRY_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTOIN_NB_LCLK_NCLK_RATIO
#define OPTOIN_NB_LCLK_NCLK_RATIO TRUE
#endif
#if (OPTOIN_NB_LCLK_NCLK_RATIO == TRUE) && (GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE F14NbLclkNclkRatioFeature;
#define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY {AMD_FAMILY_ON, F14NbLclkNclkRatioFeature},
#else
#define OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY
#endif
#define OPTION_KRNBLCLKNCLKRATIOFEATURE_ENTRY
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_NB_LCLK_DPM_INIT
#define OPTION_NB_LCLK_DPM_INIT TRUE
#endif
#if (OPTION_NB_LCLK_DPM_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE NbLclkDpmFeature;
#define OPTION_NBLCLKDPMFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbLclkDpmFeature},
#else
#define OPTION_NBLCLKDPMFEATURE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIE_POWER_GATE
#define OPTION_PCIE_POWER_GATE TRUE
#endif
#if (OPTION_PCIE_POWER_GATE == TRUE) && (GNB_TYPE_LN == TRUE)
OPTION_GNB_FEATURE PciePowerGateFeature;
#define OPTION_PCIEPOWERGATEFEATURE_ENTRY {AMD_FAMILY_LN, PciePowerGateFeature},
#else
#define OPTION_PCIEPOWERGATEFEATURE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_MID_INIT
#define OPTION_GFX_MID_INIT TRUE
#endif
#if (OPTION_GFX_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE GfxInitAtMidPost;
#define OPTION_GFXINITATMIDPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxInitAtMidPost},
#else
#define OPTION_GFXINITATMIDPOST_ENTRY
#endif
#define OPTION_GFXMIDINTERFACETN_ENTRY
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_GFX_INTEGRATED_TABLE_INIT
#define OPTION_GFX_INTEGRATED_TABLE_INIT TRUE
#endif
#if (OPTION_GFX_INTEGRATED_TABLE_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE GfxIntegratedInfoTableEntry;
#define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, GfxIntegratedInfoTableEntry},
#else
#define OPTION_GFXINTEGRATEDINFOTABLE_ENTRY
#endif
#define OPTION_GFXINTINFOTABLEINTERFACETN_ENTRY
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_PCIe_MID_INIT
#define OPTION_PCIe_MID_INIT TRUE
#endif
#if (OPTION_PCIe_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE PcieInitAtMid;
#define OPTION_PCIEINITATMID_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieInitAtMid},
#else
#define OPTION_PCIEINITATMID_ENTRY
#endif
#define OPTION_PCIEMIDINTERFACETN_ENTRY
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_NB_MID_INIT
#define OPTION_NB_MID_INIT TRUE
#endif
#if (OPTION_NB_MID_INIT == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE NbInitAtLatePost;
#define OPTION_NBINITATLATEPOST_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, NbInitAtLatePost},
#else
#define OPTION_NBINITATLATEPOST_ENTRY
#endif
#define OPTION_GNBMIDINTERFACETN_ENTRY
//---------------------------------------------------------------------------------------------------
OPTION_GNB_CONFIGURATION GnbMidFeatureTable[] = {
OPTION_GFXINITATMIDPOST_ENTRY
OPTION_GFXMIDINTERFACETN_ENTRY
OPTION_GFXINTEGRATEDINFOTABLE_ENTRY
OPTION_GFXINTINFOTABLEINTERFACETN_ENTRY
OPTION_GNBCABLESAFEENTRY_ENTRY
OPTION_PCIEINITATMID_ENTRY
OPTION_PCIEMIDINTERFACETN_ENTRY
OPTION_NBINITATLATEPOST_ENTRY
OPTION_GNBMIDINTERFACETN_ENTRY
OPTION_F14NBLCLKNCLKRATIOFEATURE_ENTRY
OPTION_KRNBLCLKNCLKRATIOFEATURE_ENTRY
OPTION_NBLCLKDPMFEATURE_ENTRY
OPTION_PCIEPOWERGATEFEATURE_ENTRY
{0, NULL}
};
#endif
#if (AGESA_ENTRY_INIT_LATE == TRUE)
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_ALIB
#define OPTION_ALIB FALSE
#endif
#if (OPTION_ALIB == TRUE) && (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
OPTION_GNB_FEATURE PcieAlibFeature;
#define OPTION_PCIEALIBFEATURE_ENTRY {AMD_FAMILY_LN | AMD_FAMILY_ON, PcieAlibFeature},
#else
#define OPTION_PCIEALIBFEATURE_ENTRY
#endif
//---------------------------------------------------------------------------------------------------
#ifndef OPTION_IOMMU_ACPI_IVRS
#define OPTION_IOMMU_ACPI_IVRS TRUE
#endif
#define OPTIONIOMMUACPIIVRSLATE_ENTRY
//---------------------------------------------------------------------------------------------------
OPTION_GNB_CONFIGURATION GnbLateFeatureTable[] = {
OPTION_PCIEALIBFEATURE_ENTRY
OPTIONIOMMUACPIIVRSLATE_ENTRY
{0, NULL}
};
#endif
#if (GNB_TYPE_LN == TRUE || GNB_TYPE_ON == TRUE)
S3_DISPATCH_FUNCTION NbSmuServiceRequestS3Script;
S3_DISPATCH_FUNCTION PcieLateRestoreS3Script;
S3_DISPATCH_FUNCTION NbSmuIndirectWriteS3Script;
#define GNB_S3_DISPATCH_FUNCTION_TABLE \
{NbSmuIndirectWriteS3Script_ID, NbSmuIndirectWriteS3Script}, \
{NbSmuServiceRequestS3Script_ID, NbSmuServiceRequestS3Script}, \
{PcieLateRestoreS3Script_ID, PcieLateRestoreS3Script},
#endif
#endif
#endif // _OPTION_GNB_INSTALL_H_

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src/vendorcode/amd/agesa/f12/Include/OptionHtInstall.h Executable file
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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Ht
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_HT_INSTALL_H_
#define _OPTION_HT_INSTALL_H_
#include "Topology.h"
#include "htFeat.h"
#include "htInterface.h"
#include "htNb.h"
#include "htTopologies.h"
/*
* Advanced Option only, hardware socket naming is the preferred method.
*/
#ifdef BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP
#define CFG_SYSTEM_PHYSICAL_SOCKET_MAP (BLDCFG_SYSTEM_PHYSICAL_SOCKET_MAP)
#else
#define CFG_SYSTEM_PHYSICAL_SOCKET_MAP (NULL)
#endif
/*
* OPTION_IS_RECOVERY_HT is true if Basic API is being used.
*/
#ifndef OPTION_IS_RECOVERY_HT
#define OPTION_IS_RECOVERY_HT TRUE
#endif
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition.
*/
#ifndef OPTION_MULTISOCKET
#error BLDOPT: Option not defined: "OPTION_MULTISOCKET"
#endif
/*
* Based on user level options, set Ht internal options.
* For now, Family 10h support will assume single module. For multi module,
* this will have to be changed to not set non-coherent only.
*/
#define OPTION_HT_NON_COHERENT_ONLY FALSE
#if ((OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE) || (OPTION_FAMILY16H == TRUE))
/* Fusion Families do not need a non-coherent only option. */
#else
// Process Family 10h and 15h by socket, applying the MultiSocket option where it is allowable.
#if OPTION_G34_SOCKET_SUPPORT == FALSE
// Hydra has coherent support, other Family 10h should follow MultiSocket support.
#if OPTION_MULTISOCKET == FALSE
#undef OPTION_HT_NON_COHERENT_ONLY
#define OPTION_HT_NON_COHERENT_ONLY TRUE
#endif
#endif
#endif
/*
* Macros will generate the correct item reference based on options
*/
#if AGESA_ENTRY_INIT_EARLY == TRUE
// Select the interface and features
#if ((OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE) || (OPTION_FAMILY16H == TRUE))
#define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
#define INTERNAL_HT_OPTION_FEATURES &HtFeaturesNone
#define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceMapsOnly
#else
// Family 10h and 15h Models 00h-0Fh
#if OPTION_HT_NON_COHERENT_ONLY == FALSE
#define INTERNAL_HT_OPTION_FEATURES &HtFeaturesDefault
#define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceDefault
#else
#define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
#define INTERNAL_HT_OPTION_FEATURES &HtFeaturesNonCoherentOnly
#define INTERNAL_HT_OPTION_INTERFACE &HtInterfaceNonCoherentOnly
#endif
#endif
// Select Northbridge components
#if OPTION_FAMILY10H == TRUE
#if OPTION_HT_NON_COHERENT_ONLY == TRUE
#define INTERNAL_HT_OPTION_FAM10_NB &HtFam10NbNonCoherentOnly, &HtFam10RevDNbNonCoherentOnly,
#else
#define INTERNAL_HT_OPTION_FAM10_NB &HtFam10NbDefault, &HtFam10RevDNbDefault,
#endif
#else
#define INTERNAL_HT_OPTION_FAM10_NB
#endif
#if OPTION_FAMILY12H == TRUE
#define INTERNAL_HT_OPTION_FAM12_NB &HtFam12Nb,
#else
#define INTERNAL_HT_OPTION_FAM12_NB
#endif
#if OPTION_FAMILY14H == TRUE
#define INTERNAL_HT_OPTION_FAM14_NB &HtFam14Nb,
#else
#define INTERNAL_HT_OPTION_FAM14_NB
#endif
#if OPTION_FAMILY15H == TRUE
#if OPTION_HT_NON_COHERENT_ONLY == TRUE
#define INTERNAL_HT_OPTION_FAM15_NB &HtFam15NbNonCoherentOnly,
#else
#define INTERNAL_HT_OPTION_FAM15_NB &HtFam15NbDefault,
#endif
#else
#define INTERNAL_HT_OPTION_FAM15_NB
#endif
#define INTERNAL_ONLY_NB_LIST_ITEM INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS,
#ifndef INTERNAL_ONLY_HT_OPTION_SUPPORTED_NBS
#undef INTERNAL_ONLY_NB_LIST_ITEM
#define INTERNAL_ONLY_NB_LIST_ITEM
#endif
/* Install the correct set of northbridge implementations. Each item provides its own comma, the last item
* is ok to have a comma because the final item (NULL) is added below.
*/
#define INTERNAL_HT_OPTION_SUPPORTED_NBS \
INTERNAL_ONLY_NB_LIST_ITEM \
INTERNAL_HT_OPTION_FAM10_NB \
INTERNAL_HT_OPTION_FAM15_NB \
INTERNAL_HT_OPTION_FAM12_NB \
INTERNAL_HT_OPTION_FAM14_NB
#else
// Not Init Early
#define INTERNAL_HT_OPTION_FEATURES NULL
#define INTERNAL_HT_OPTION_INTERFACE NULL
#define INTERNAL_HT_OPTION_SUPPORTED_NBS NULL
#define HT_OPTIONS_PLATFORM NULL
#define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES NULL
#endif
#ifdef AGESA_ENTRY_INIT_EARLY
#if AGESA_ENTRY_INIT_EARLY == TRUE
extern HT_FEATURES HtFeaturesDefault;
extern HT_FEATURES HtFeaturesNonCoherentOnly;
extern HT_FEATURES HtFeaturesNone;
extern HT_INTERFACE HtInterfaceDefault;
extern HT_INTERFACE HtInterfaceNonCoherentOnly;
extern HT_INTERFACE HtInterfaceMapsOnly;
extern HT_INTERFACE HtInterfaceNone;
extern NORTHBRIDGE HtFam10NbDefault;
extern NORTHBRIDGE HtFam10RevDNbDefault;
extern NORTHBRIDGE HtFam10NbNonCoherentOnly;
extern NORTHBRIDGE HtFam10RevDNbNonCoherentOnly;
extern NORTHBRIDGE HtFam12Nb;
extern NORTHBRIDGE HtFam14Nb;
extern NORTHBRIDGE HtFam10NbNone;
extern NORTHBRIDGE HtFam15NbDefault;
extern NORTHBRIDGE HtFam15NbNonCoherentOnly;
CONST VOID * CONST ROMDATA HtInstalledFamilyNorthbridgeList[] = {
INTERNAL_HT_OPTION_SUPPORTED_NBS
NULL
};
STATIC CONST AMD_HT_INTERFACE ROMDATA HtOptionsPlatform =
{
CFG_STARTING_BUSNUM, CFG_MAXIMUM_BUSNUM, CFG_ALLOCATED_BUSNUM,
(MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST,
(DEVICE_CAP_OVERRIDE *)CFG_HTDEVICE_CAPABILITIES_OVERRIDE_LIST,
(CPU_TO_CPU_PCB_LIMITS *)CFG_HTFABRIC_LIMITS_LIST,
(IO_PCB_LIMITS *)CFG_HTCHAIN_LIMITS_LIST,
(OVERRIDE_BUS_NUMBERS *)CFG_BUS_NUMBERS_LIST,
(IGNORE_LINK *)CFG_IGNORE_LINK_LIST,
(SKIP_REGANG *)CFG_LINK_SKIP_REGANG_LIST,
(UINT8 **)CFG_ADDITIONAL_TOPOLOGIES_LIST,
(SYSTEM_PHYSICAL_SOCKET_MAP *)CFG_SYSTEM_PHYSICAL_SOCKET_MAP
};
#ifndef HT_OPTIONS_PLATFORM
#define HT_OPTIONS_PLATFORM &HtOptionsPlatform
#endif
/**
* A list of all the supported topologies.
*
*/
#ifndef INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES
CONST UINT8 *CONST ROMDATA AmdTopolist[] =
{
amdHtTopologySingleNode,
amdHtTopologyDualNode,
amdHtTopologyThreeLine,
amdHtTopologyTriangle,
amdHtTopologyFourLine,
amdHtTopologyFourStar,
amdHtTopologyFourDegenerate,
amdHtTopologyFourSquare,
amdHtTopologyFourKite,
amdHtTopologyFourFully,
amdHtTopologyFiveFully,
amdHtTopologyFiveTwistedLadder,
amdHtTopologySixFully,
amdHtTopologySixDoubloonLower,
amdHtTopologySixDoubloonUpper,
amdHtTopologySixTwistedLadder,
amdHtTopologySevenFully,
amdHtTopologySevenTwistedLadder,
amdHtTopologyEightFully,
amdHtTopologyEightDoubloon,
amdHtTopologyEightTwistedLadder,
amdHtTopologyEightStraightLadder,
amdHtTopologySixTwinTriangles,
amdHtTopologyEightTwinFullyFourWays,
NULL
};
#define INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES AmdTopolist
#endif
/**
* Declare the instance of the Ht option configuration structure
*/
CONST OPTION_HT_CONFIGURATION ROMDATA OptionHtConfiguration = {
OPTION_IS_RECOVERY_HT,
CFG_SET_HTCRC_SYNC_FLOOD,
CFG_USE_UNIT_ID_CLUMPING,
HT_OPTIONS_PLATFORM,
INTERNAL_HT_OPTION_INTERFACE,
INTERNAL_HT_OPTION_FEATURES,
&HtInstalledFamilyNorthbridgeList,
INTERNAL_HT_OPTION_BUILTIN_TOPOLOGIES
};
#endif
#endif
#ifndef OPTION_HT_INIIT_RESET_ENTRY
#define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset
#define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY AmdHtResetConstructor
#if (OPTION_FAMILY12H == TRUE) || (OPTION_FAMILY14H == TRUE)
#undef OPTION_HT_INIIT_RESET_ENTRY
#undef OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY
#define OPTION_HT_INIIT_RESET_ENTRY NULL
#define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY NULL
#endif
#if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H_OR == TRUE))
#undef OPTION_HT_INIIT_RESET_ENTRY
#undef OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY
#define OPTION_HT_INIIT_RESET_ENTRY AmdHtInitReset
#define OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY AmdHtResetConstructor
#endif
#endif
#ifdef AGESA_ENTRY_INIT_RESET
#if AGESA_ENTRY_INIT_RESET == TRUE
CONST AMD_HT_RESET_INTERFACE ROMDATA HtOptionResetDefaults = {
(MANUAL_BUID_SWAP_LIST *)CFG_BUID_SWAP_LIST,
0 // Unused by options
};
CONST OPTION_HT_INIT_RESET ROMDATA HtOptionInitReset = {
OPTION_HT_INIIT_RESET_ENTRY,
OPTION_HT_INIIT_RESET_CONSTRUCTOR_ENTRY
};
#endif
#endif
#endif // _OPTION_HT_INSTALL_H_

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src/vendorcode/amd/agesa/f12/Include/OptionHwC1eInstall.h Executable file
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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: HW C1e
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_HW_C1E_INSTALL_H_
#define _OPTION_HW_C1E_INSTALL_H_
#include "cpuHwC1e.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_HW_C1E_FEAT
#define F10_HW_C1E_SUPPORT
#if AGESA_ENTRY_INIT_EARLY == TRUE
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
#if (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) || (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_PH == TRUE)
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureHwC1e;
#undef OPTION_HW_C1E_FEAT
#define OPTION_HW_C1E_FEAT &CpuFeatureHwC1e,
extern CONST HW_C1E_FAMILY_SERVICES ROMDATA F10HwC1e;
#undef F10_HW_C1E_SUPPORT
#define F10_HW_C1E_SUPPORT {(AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_RB | AMD_FAMILY_10_PH), &F10HwC1e},
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA HwC1eFamilyServiceArray[] =
{
F10_HW_C1E_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA HwC1eFamilyServiceTable =
{
(sizeof (HwC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&HwC1eFamilyServiceArray[0]
};
#endif
#endif // _OPTION_HW_C1E_INSTALL_H_

414
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/* $NoKeywords:$ */
/**
* @file
*
* IDS Option Install File
*
* This file generates the defaults tables for family 10h model 5 processors.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 47940 $ @e \$Date: 2011-03-02 14:25:35 +0800 (Wed, 02 Mar 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_IDS_INSTALL_H_
#define _OPTION_IDS_INSTALL_H_
#include "Ids.h"
#include "IdsHt.h"
#include "IdsLib.h"
#ifdef __IDS_EXTENDED__
#include OPTION_IDS_EXT_INSTALL_FILE
#endif
#define IDS_LATE_RUN_AP_TASK
#define M_HTIDS_PORT_OVERRIDE_HOOK (PF_HtIdsGetPortOverride)CommonVoid
#if (IDSOPT_IDS_ENABLED == TRUE)
#if (IDSOPT_CONTROL_ENABLED == TRUE)
// Check for all families which include HT Features.
#if (OPTION_FAMILY10H == TRUE) && (AGESA_ENTRY_INIT_POST == TRUE)
#undef M_HTIDS_PORT_OVERRIDE_HOOK
#define M_HTIDS_PORT_OVERRIDE_HOOK HtIdsGetPortOverride
#endif
#endif
#endif // OPTION_IDS_LEVEL
CONST PF_HtIdsGetPortOverride ROMDATA pf_HtIdsGetPortOverride = M_HTIDS_PORT_OVERRIDE_HOOK;
#if (IDSOPT_IDS_ENABLED == TRUE)
#if (AGESA_ENTRY_INIT_LATE == TRUE)
#undef IDS_LATE_RUN_AP_TASK
#define IDS_LATE_RUN_AP_TASK
#endif
#endif // OPTION_IDS_LEVEL
#if (IDSOPT_TRACING_ENABLED == TRUE)
#if (AGESA_ENTRY_INIT_POST == TRUE)
#include <mu.h>
CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
{ (UINT32) (UINT64) MemUWriteCachelines, "WriteCl(PhyAddrLo,BufferAddr,ClCnt)"},
{ (UINT32) (UINT64) MemUReadCachelines, "ReadCl(BufferAddr,PhyAddrLo,ClCnt)"},
{ (UINT32) (UINT64) MemUFlushPattern, "FlushCl(PhyAddrLo,ClCnt)"}
};
#elif (AGESA_ENTRY_INIT_RECOVERY == TRUE)
#include <mru.h>
CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
{ (UINT32) (UINT64) MemRecUWrite1CL, "Write1Cl(PhyAddrLo,BufferAddr)"},
{ (UINT32) (UINT64) MemRecURead1CL, "Read1Cl(BufferAddr,PhyAddrLo)"},
{ (UINT32) (UINT64) MemRecUFlushPattern, "Flush1Cl(PhyAddrLo)"}
};
#else
CONST SCRIPT_FUNCTION ROMDATA ScriptFuncList[] = {
{ (UINT32) (UINT64) CommonReturnFalse, "DefRet()"},
{ (UINT32) (UINT64) CommonReturnFalse, "DefRet()"},
{ (UINT32) (UINT64) CommonReturnFalse, "DefRet()"}
};
#endif
#endif
///Ids Feat Options
#if (IDSOPT_IDS_ENABLED == TRUE)
#if (IDSOPT_CONTROL_ENABLED == TRUE)
#ifndef OPTION_IDS_EXTEND_FEATS
#define OPTION_IDS_EXTEND_FEATS
#endif
#define OPTION_IDS_FEAT_ECCCTRL\
OPTION_IDS_FEAT_ECCCTRL_F10 \
OPTION_IDS_FEAT_ECCCTRL_F12 \
OPTION_IDS_FEAT_ECCCTRL_F15_OR
#define OPTION_IDS_FEAT_GNB_PLATFORMCFG\
OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 \
OPTION_IDS_FEAT_GNB_PLATFORMCFGF14
#define OPTION_IDS_FEAT_CPB_CTRL\
OPTION_IDS_FEAT_CPB_CTRL_F12
#define OPTION_IDS_FEAT_HTC_CTRL\
OPTION_IDS_FEAT_HTC_CTRL_F15
#define OPTION_IDS_FEAT_MEMORY_MAPPING\
OPTION_IDS_FEAT_MEMORY_MAPPING_F12 \
OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR
#define OPTION_IDS_FEAT_HT_ASSIST\
OPTION_IDS_FEAT_HT_ASSIST_F10HY \
OPTION_IDS_FEAT_HT_ASSIST_F15_OR
#define OPTION_IDS_FEAT_ECCSYMBOLSIZE\
OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 \
OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR
/*----------------------------------------------------------------------------
* Family 10 feat blocks
*
*----------------------------------------------------------------------------
*/
#define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10
#define OPTION_IDS_FEAT_ECCCTRL_F10
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
//Ecc symbol size
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlockF10;
#undef OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10
#define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F10 &IdsFeatEccSymbolSizeBlockF10,
//ECC scrub control
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF10;
#undef OPTION_IDS_FEAT_ECCCTRL_F10
#define OPTION_IDS_FEAT_ECCCTRL_F10 &IdsFeatEccCtrlBlockF10,
#endif
#endif
//Misc Features
#define OPTION_IDS_FEAT_HT_ASSIST_F10HY
#ifdef OPTION_FAMILY10H_HY
#if OPTION_FAMILY10H_HY == TRUE
#undef OPTION_IDS_FEAT_HT_ASSIST_F10HY
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtAssistBlockPlatformCfgF10Hy;
#define OPTION_IDS_FEAT_HT_ASSIST_F10HY \
&IdsFeatHtAssistBlockPlatformCfgF10Hy,
#endif
#endif
/*----------------------------------------------------------------------------
* Family 12 feat blocks
*
*----------------------------------------------------------------------------
*/
#define OPTION_IDS_FEAT_GNB_PLATFORMCFGF12
#define OPTION_IDS_FEAT_ECCCTRL_F12
#define OPTION_IDS_FEAT_CPB_CTRL_F12
#ifdef OPTION_FAMILY12H
#if OPTION_FAMILY12H == TRUE
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF12;
#undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF12
#define OPTION_IDS_FEAT_GNB_PLATFORMCFGF12 &IdsFeatGnbPlatformCfgBlockF12,
//ECC scrub control
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF12;
#undef OPTION_IDS_FEAT_ECCCTRL_F12
#define OPTION_IDS_FEAT_ECCCTRL_F12 &IdsFeatEccCtrlBlockF12,
#undef OPTION_IDS_FEAT_CPB_CTRL_F12
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatCpbCtrlBlockF12;
#define OPTION_IDS_FEAT_CPB_CTRL_F12 &IdsFeatCpbCtrlBlockF12,
#endif
#endif
/*----------------------------------------------------------------------------
* Family 14 feat blocks
*
*----------------------------------------------------------------------------
*/
#define OPTION_IDS_FEAT_GNB_PLATFORMCFGF14
#ifdef OPTION_FAMILY14H
#if OPTION_FAMILY14H == TRUE
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatGnbPlatformCfgBlockF14;
#undef OPTION_IDS_FEAT_GNB_PLATFORMCFGF14
#define OPTION_IDS_FEAT_GNB_PLATFORMCFGF14 &IdsFeatGnbPlatformCfgBlockF14,
#endif
#endif
/*----------------------------------------------------------------------------
* Family 15 OR feat blocks
*
*----------------------------------------------------------------------------
*/
#define OPTION_IDS_FEAT_HTC_CTRL_F15_OR
#define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR
#define OPTION_IDS_FEAT_HT_ASSIST_F15_OR
#define OPTION_IDS_FEAT_ECCCTRL_F15_OR
#define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR
#ifdef OPTION_FAMILY15H_OR
#if OPTION_FAMILY15H_OR == TRUE
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtcControlBlockF15Or;
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtcControlLateBlockF15Or;
#undef OPTION_IDS_FEAT_HTC_CTRL_F15_OR
#define OPTION_IDS_FEAT_HTC_CTRL_F15_OR\
&IdsFeatHtcControlBlockF15Or,\
&IdsFeatHtcControlLateBlockF15Or,
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingPostBeforeBlockF15Or;
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatMemoryMappingChIntlvBlockF15Or;
#undef OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR
#define OPTION_IDS_FEAT_MEMORY_MAPPING_F15_OR\
&IdsFeatMemoryMappingPostBeforeBlockF15Or,\
&IdsFeatMemoryMappingChIntlvBlockF15Or,
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtAssistBlockPlatformCfgF15Or;
#undef OPTION_IDS_FEAT_HT_ASSIST_F15_OR
#define OPTION_IDS_FEAT_HT_ASSIST_F15_OR\
&IdsFeatHtAssistBlockPlatformCfgF15Or,
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccCtrlBlockF15Or;
#undef OPTION_IDS_FEAT_ECCCTRL_F15_OR
#define OPTION_IDS_FEAT_ECCCTRL_F15_OR &IdsFeatEccCtrlBlockF15Or,
extern CONST IDS_FEAT_STRUCT ROMDATA IdsFeatEccSymbolSizeBlockF15Or;
#undef OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR
#define OPTION_IDS_FEAT_ECCSYMBOLSIZE_F15_OR &IdsFeatEccSymbolSizeBlockF15Or,
#endif
#endif
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatUcodeBlock =
{
IDS_FEAT_UCODE_UPDATE,
IDS_ALL_CORES,
IDS_UCODE,
IDS_FAMILY_ALL,
IdsSubUCode
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatPowerPolicyBlock =
{
IDS_FEAT_POWER_POLICY,
IDS_ALL_CORES,
IDS_PLATFORMCFG_OVERRIDE,
IDS_FAMILY_ALL,
IdsSubPowerPolicyOverride
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatTargetPstateBlock =
{
IDS_FEAT_TARGET_PSTATE,
IDS_BSP_ONLY,
IDS_INIT_LATE_AFTER,
IDS_FAMILY_ALL,
IdsSubTargetPstate
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatPostPstateBlock =
{
IDS_FEAT_POSTPSTATE,
IDS_ALL_CORES,
IDS_CPU_Early_Override,
IDS_FAMILY_ALL,
IdsSubPostPState
};
//Dram controller Features
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctAllMemClkBlock =
{
IDS_FEAT_DCT_ALLMEMCLK,
IDS_BSP_ONLY,
IDS_ALL_MEMORY_CLOCK,
IDS_FAMILY_ALL,
IdsSubAllMemClkEn
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctGangModeBlock =
{
IDS_FEAT_DCT_GANGMODE,
IDS_BSP_ONLY,
IDS_GANGING_MODE,
IDS_FAMILY_ALL,
IdsSubGangingMode
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctBurstLengthBlock =
{
IDS_FEAT_DCT_BURSTLENGTH,
IDS_BSP_ONLY,
IDS_BURST_LENGTH32,
AMD_FAMILY_10,
IdsSubBurstLength32
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownCtrlBlock =
{
IDS_FEAT_DCT_POWERDOWN,
IDS_BSP_ONLY,
IDS_INIT_POST_BEFORE,
IDS_FAMILY_ALL,
IdsSubPowerDownCtrl
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctDllShutDownBlock =
{
IDS_FEAT_DCT_DLLSHUTDOWN,
IDS_BSP_ONLY,
IDS_DLL_SHUT_DOWN,
IDS_FAMILY_ALL,
IdsSubDllShutDownSR
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatDctPowerDownModeBlock =
{
IDS_FEAT_DCT_POWERDOWN,
IDS_BSP_ONLY,
IDS_POWERDOWN_MODE,
IDS_FAMILY_ALL,
IdsSubPowerDownMode
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHdtOutBlock =
{
IDS_FEAT_HDTOUT,
IDS_BSP_ONLY,
IDS_INIT_EARLY_BEFORE,
IDS_FAMILY_ALL,
IdsSubHdtOut
};
CONST IDS_FEAT_STRUCT ROMDATA IdsFeatHtSettingBlock =
{
IDS_FEAT_HT_SETTING,
IDS_BSP_ONLY,
IDS_HT_CONTROL,
IDS_FAMILY_ALL,
IdsSubHtLinkControl
};
CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] =
{
&IdsFeatUcodeBlock,
&IdsFeatPowerPolicyBlock,
&IdsFeatTargetPstateBlock,
&IdsFeatPostPstateBlock,
OPTION_IDS_FEAT_ECCSYMBOLSIZE
OPTION_IDS_FEAT_ECCCTRL
&IdsFeatDctAllMemClkBlock,
&IdsFeatDctGangModeBlock,
&IdsFeatDctBurstLengthBlock,
&IdsFeatDctPowerDownCtrlBlock,
&IdsFeatDctPowerDownModeBlock,
&IdsFeatDctPowerDownModeBlock,
OPTION_IDS_FEAT_HT_ASSIST
&IdsFeatHdtOutBlock,
&IdsFeatHtSettingBlock,
OPTION_IDS_FEAT_GNB_PLATFORMCFG
OPTION_IDS_FEAT_CPB_CTRL
OPTION_IDS_FEAT_HTC_CTRL
OPTION_IDS_FEAT_MEMORY_MAPPING
OPTION_IDS_EXTEND_FEATS
NULL
};
#else
CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] =
{
NULL
};
#endif//IDSOPT_CONTROL_ENABLED
#else
CONST IDS_FEAT_STRUCT* ROMDATA IdsCommonFeats[] =
{
NULL
};
#endif// IDSOPT_IDS_ENABLED
#endif

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src/vendorcode/amd/agesa/f12/Include/OptionIoCstateInstall.h Executable file
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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: IO C-state
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_IO_CSTATE_INSTALL_H_
#define _OPTION_IO_CSTATE_INSTALL_H_
#include "cpuIoCstate.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_IO_CSTATE_FEAT
#define F10_IO_CSTATE_SUPPORT
#define F12_IO_CSTATE_SUPPORT
#define F14_IO_CSTATE_SUPPORT
#define F15_OR_IO_CSTATE_SUPPORT
#if OPTION_IO_CSTATE == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
#if OPTION_FAMILY10H_PH == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
#undef OPTION_IO_CSTATE_FEAT
#define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F10IoCstateSupport;
#undef F10_IO_CSTATE_SUPPORT
#define F10_IO_CSTATE_SUPPORT {AMD_FAMILY_10_PH, &F10IoCstateSupport},
#endif
#endif
#endif
#ifdef OPTION_FAMILY12H
#if OPTION_FAMILY12H == TRUE
#if OPTION_FAMILY12H_LN == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
#undef OPTION_IO_CSTATE_FEAT
#define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F12IoCstateSupport;
#undef F12_IO_CSTATE_SUPPORT
#define F12_IO_CSTATE_SUPPORT {AMD_FAMILY_12_LN, &F12IoCstateSupport},
#endif
#endif
#endif
#ifdef OPTION_FAMILY14H
#if OPTION_FAMILY14H == TRUE
#if OPTION_FAMILY14H_ON == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
#undef OPTION_IO_CSTATE_FEAT
#define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F14IoCstateSupport;
#undef F14_IO_CSTATE_SUPPORT
#define F14_IO_CSTATE_SUPPORT {AMD_FAMILY_14, &F14IoCstateSupport},
#endif
#endif
#endif
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
#if OPTION_FAMILY15H_OR == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureIoCstate;
#undef OPTION_IO_CSTATE_FEAT
#define OPTION_IO_CSTATE_FEAT &CpuFeatureIoCstate,
extern CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F15OrIoCstateSupport;
#undef F15_OR_IO_CSTATE_SUPPORT
#define F15_OR_IO_CSTATE_SUPPORT {AMD_FAMILY_15_OR, &F15OrIoCstateSupport},
#endif
#endif
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA IoCstateFamilyServiceArray[] =
{
F10_IO_CSTATE_SUPPORT
F12_IO_CSTATE_SUPPORT
F14_IO_CSTATE_SUPPORT
F15_OR_IO_CSTATE_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA IoCstateFamilyServiceTable =
{
(sizeof (IoCstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&IoCstateFamilyServiceArray[0]
};
#endif // _OPTION_IO_CSTATE_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: L3 Dependent Features
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_L3_FEATURES_INSTALL_H_
#define _OPTION_L3_FEATURES_INSTALL_H_
#include "cpuL3Features.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_L3_FEAT
#define F10_L3_FEAT_SUPPORT
#define F15_L3_FEAT_SUPPORT
#define L3_FEAT_AP_DISABLE_CACHE
#define L3_FEAT_AP_ENABLE_CACHE
#if (OPTION_HT_ASSIST == TRUE || OPTION_ATM_MODE == TRUE)
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE) || (AGESA_ENTRY_INIT_LATE_RESTORE == TRUE)
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
#if OPTION_FAMILY10H_HY == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuL3Features;
#undef OPTION_L3_FEAT
#define OPTION_L3_FEAT &CpuL3Features,
extern CONST L3_FEATURE_FAMILY_SERVICES ROMDATA F10L3Features;
#undef F10_L3_FEAT_SUPPORT
#define F10_L3_FEAT_SUPPORT {AMD_FAMILY_10_HY, &F10L3Features},
#endif
#endif
#endif
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuL3Features;
#undef OPTION_L3_FEAT
#define OPTION_L3_FEAT &CpuL3Features,
extern CONST L3_FEATURE_FAMILY_SERVICES ROMDATA F15OrL3Features;
#undef F15_L3_FEAT_SUPPORT
#define F15_L3_FEAT_SUPPORT {AMD_FAMILY_15, &F15OrL3Features},
#endif
#endif
#undef AGESA_ENTRY_LATE_RUN_AP_TASK
#define AGESA_ENTRY_LATE_RUN_AP_TASK TRUE
#undef L3_FEAT_AP_DISABLE_CACHE
#define L3_FEAT_AP_DISABLE_CACHE {AP_LATE_TASK_DISABLE_CACHE, (IMAGE_ENTRY) DisableAllCaches},
#undef L3_FEAT_AP_ENABLE_CACHE
#define L3_FEAT_AP_ENABLE_CACHE {AP_LATE_TASK_ENABLE_CACHE, (IMAGE_ENTRY) EnableAllCaches},
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA L3FeatureFamilyServiceArray[] =
{
F10_L3_FEAT_SUPPORT
F15_L3_FEAT_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA L3FeatureFamilyServiceTable =
{
(sizeof (L3FeatureFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&L3FeatureFamilyServiceArray[0]
};
#endif // _OPTION_L3_FEATURES_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Low Power Pstate for PROCHOT_L Throttling.
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_LOW_PWR_PSTATE_INSTALL_H_
#define _OPTION_LOW_PWR_PSTATE_INSTALL_H_
#include "cpuLowPwrPstate.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT
#define F15_LOW_PWR_PSTATE_SUPPORT
#if OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE) || (AGESA_ENTRY_INIT_LATE == TRUE)
// Family 15h
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
#if OPTION_FAMILY15H_OR == TRUE
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureLowPwrPstate;
#undef OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT
#define OPTION_CPU_LOW_PWR_PSTATE_FOR_PROCHOT_FEAT &CpuFeatureLowPwrPstate,
extern CONST LOW_PWR_PSTATE_FAMILY_SERVICES ROMDATA F15OrLowPwrPstateSupport;
#undef F15_LOW_PWR_PSTATE_SUPPORT
#define F15_LOW_PWR_PSTATE_SUPPORT {AMD_FAMILY_15_OR, &F15OrLowPwrPstateSupport},
#endif
#endif
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA LowPwrPstateFamilyServiceArray[] =
{
F15_LOW_PWR_PSTATE_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA LowPwrPstateFamilyServiceTable =
{
(sizeof (LowPwrPstateFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&LowPwrPstateFamilyServiceArray[0]
};
#endif // _OPTION_LOW_PWR_PSTATE_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* AMD Memory option API.
*
* Contains structures and values used to control the Memory option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_MEMORY_H_
#define _OPTION_MEMORY_H_
/* Memory Includes */
#include "mm.h"
#include "mn.h"
#include "mt.h"
#include "ma.h"
#include "mp.h"
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
#define MAX_FF_TYPES 6 ///< Maximum number of DDR Form factors (UDIMMs, RDIMMMs, SODIMMS) supported
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/*
* STANDARD MEMORY FEATURE FUNCTION POINTER
*/
typedef BOOLEAN OPTION_MEM_FEATURE_NB (
IN OUT MEM_NB_BLOCK *NBPtr
);
typedef BOOLEAN MEM_TECH_FEAT (
IN OUT MEM_TECH_BLOCK *TechPtr
);
typedef UINT8 MEM_TABLE_FEAT (
IN OUT MEM_TABLE_ALIAS **MTPtr
);
#define MEM_FEAT_BLOCK_NB_STRUCT_VERSION 0x01
/**
* MEMORY FEATURE BLOCK - This structure serves as a vector table for standard
* memory feature implementation functions. It contains vectors for all of the
* features that are supported by the various Northbridge devices supported by
* AGESA.
*/
typedef struct _MEM_FEAT_BLOCK_NB {
UINT16 OptMemFeatVersion; ///< Version of memory feature block.
OPTION_MEM_FEATURE_NB *OnlineSpare; ///< Online spare support.
OPTION_MEM_FEATURE_NB *InterleaveBanks; ///< Bank (Chip select) interleaving support.
OPTION_MEM_FEATURE_NB *UndoInterleaveBanks; ///< Undo Bank (Chip Select) interleaving.
OPTION_MEM_FEATURE_NB *CheckInterleaveNodes; ///< Check for Node interleaving support.
OPTION_MEM_FEATURE_NB *InterleaveNodes; ///< Node interleaving support.
OPTION_MEM_FEATURE_NB *InterleaveChannels; ///< Channel interleaving support.
OPTION_MEM_FEATURE_NB *InterleaveRegion; ///< Interleave Region support.
OPTION_MEM_FEATURE_NB *CheckEcc; ///< Check for ECC support.
OPTION_MEM_FEATURE_NB *InitEcc; ///< ECC support.
OPTION_MEM_FEATURE_NB *Training; ///< Choose the type of training (Parallel, standard or hardcoded).
OPTION_MEM_FEATURE_NB *LvDdr3; ///< Low voltage DDR3 dimm support
OPTION_MEM_FEATURE_NB *OnDimmThermal; ///< On-Dimm thermal management
MEM_TECH_FEAT *DramInit; ///< Choose the type of Dram init (hardware based or software based).
OPTION_MEM_FEATURE_NB *ExcludeDIMM; ///< Exclude a dimm.
OPTION_MEM_FEATURE_NB *InitEarlySampleSupport; ///< Initialize early sample support.
OPTION_MEM_FEATURE_NB *InitCPG; ///< Continuous pattern generation.
OPTION_MEM_FEATURE_NB *InitHwRxEn; ///< Hardware Receiver Enable Training Initilization.
} MEM_FEAT_BLOCK_NB;
typedef AGESA_STATUS MEM_MAIN_FLOW_CONTROL (
IN OUT MEM_MAIN_DATA_BLOCK *MemMainPtr
);
typedef BOOLEAN OPTION_MEM_FEATURE_MAIN (
IN MEM_MAIN_DATA_BLOCK *MMPtr
);
typedef BOOLEAN MEM_NB_CONSTRUCTOR (
IN OUT MEM_NB_BLOCK *NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
IN MEM_FEAT_BLOCK_NB *FeatPtr,
IN MEM_SHARED_DATA *mmSharedPtr, ///< Pointer to Memory scratchpad
IN UINT8 NodeID
);
typedef BOOLEAN MEM_TECH_CONSTRUCTOR (
IN OUT MEM_TECH_BLOCK *TechPtr,
IN OUT MEM_NB_BLOCK *NBPtr
);
typedef VOID MEM_INITIALIZER (
IN OUT MEM_DATA_STRUCT *MemPtr
);
typedef AGESA_STATUS MEM_PLATFORM_CFG (
IN struct _MEM_DATA_STRUCT *MemData,
IN UINT8 SocketID,
IN CH_DEF_STRUCT *CurrentChannel
);
typedef BOOLEAN MEM_IDENDIMM_CONSTRUCTOR (
IN OUT MEM_NB_BLOCK *NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
IN UINT8 NodeID
);
typedef VOID MEM_TECH_TRAINING_FEAT (
IN OUT MEM_TECH_BLOCK *TechPtr,
IN UINT8 Pass
);
typedef BOOLEAN MEM_RESUME_CONSTRUCTOR (
IN OUT VOID *S3NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
IN UINT8 NodeID
);
typedef AGESA_STATUS MEM_PLAT_SPEC_CFG (
IN struct _MEM_DATA_STRUCT *MemData,
IN OUT CH_DEF_STRUCT *CurrentChannel,
IN OUT MEM_PS_BLOCK *PsPtr
);
typedef AGESA_STATUS MEM_FLOW_CFG (
IN OUT MEM_MAIN_DATA_BLOCK *MemData
);
#define MEM_FEAT_BLOCK_MAIN_STRUCT_VERSION 0x01
/**
* MAIN FEATURE BLOCK - This structure serves as vector table for memory features
* that shared between all northbridge devices.
*/
typedef struct _MEM_FEAT_BLOCK_MAIN {
UINT16 OptMemFeatVersion; ///< Version of main feature block.
OPTION_MEM_FEATURE_MAIN *Training; ///< Training features.
OPTION_MEM_FEATURE_MAIN *ExcludeDIMM; ///< Exclude a dimm.
OPTION_MEM_FEATURE_MAIN *OnlineSpare; ///< On-line spare.
OPTION_MEM_FEATURE_MAIN *InterleaveNodes; ///< Node interleave.
OPTION_MEM_FEATURE_MAIN *InitEcc; ///< Initialize ECC on all nodes if they all support it.
OPTION_MEM_FEATURE_MAIN *MemClr; ///< Memory Clear.
OPTION_MEM_FEATURE_MAIN *MemDmi; ///< Memory DMI Support.
OPTION_MEM_FEATURE_MAIN *LvDDR3; ///< Low voltage DDR3 support.
OPTION_MEM_FEATURE_MAIN *UmaAllocation; ///< Uma Allocation.
OPTION_MEM_FEATURE_MAIN *MemSave; ///< Memory Context Save
OPTION_MEM_FEATURE_MAIN *MemRestore; ///< Memory Context Restore
} MEM_FEAT_BLOCK_MAIN;
#define MEM_NB_SUPPORT_STRUCT_VERSION 0x01
#define MEM_TECH_FEAT_BLOCK_STRUCT_VERSION 0x01
#define MEM_TECH_TRAIN_SEQUENCE_STRUCT_VERSION 0x01
#define MEM_TECH_LRDIMM_STRUCT_VERSION 0x01
/**
* MEMORY TECHNOLOGY FEATURE BLOCK - This structure serves as a vector table for standard
* memory feature implementation functions. It contains vectors for all of the
* features that are supported by the various Technology features supported by
* AGESA.
*/
typedef struct _MEM_TECH_FEAT_BLOCK {
UINT16 OptMemTechFeatVersion; ///< Version of memory Tech feature block.
MEM_TECH_FEAT *EnterHardwareTraining; ///<Enter HW WL Training
MEM_TECH_FEAT *SwWLTraining; ///<SW Write Levelization training
MEM_TECH_FEAT *HwBasedWLTrainingPart1; ///<HW based write levelization Training Part 1
MEM_TECH_FEAT *HwBasedDQSReceiverEnableTrainingPart1; ///<HW based DQS receiver Enabled Training Part 1
MEM_TECH_FEAT *HwBasedWLTrainingPart2; ///<HW based write levelization Training Part 2
MEM_TECH_FEAT *HwBasedDQSReceiverEnableTrainingPart2; ///<HW based DQS receiver Enabled Training Part 2
MEM_TECH_FEAT *TrainExitHwTrn; ///<Exit HW WL Training
MEM_TECH_FEAT *NonOptimizedSWDQSRecEnTrainingPart1; ///< Non-Optimized Software based receiver Enable Training part 1
MEM_TECH_FEAT *OptimizedSwDqsRecEnTrainingPart1; ///< Optimized Software based receiver Enable Training part 1
MEM_TECH_FEAT *NonOptimizedSRdWrPosTraining; ///< Non-Optimized Rd Wr Position training
MEM_TECH_FEAT *OptimizedSRdWrPosTraining; ///< Optimized Rd Wr Position training
MEM_TECH_FEAT *MaxRdLatencyTraining; ///< MaxReadLatency Training
MEM_TECH_FEAT *RdPosTraining; ///< HW Rx En Seed Training
} MEM_TECH_FEAT_BLOCK;
/**
* MEMORY TECHNOLOGY LRDIMM BLOCK - This structure serves as a vector table for standard
* memory feature implementation functions. It contains vectors for all of the
* features that are supported by the various LRDIMM features supported by
* AGESA.
*/
typedef struct _MEM_TECH_LRDIMM {
UINT16 OptMemTechLrdimmVersion; ///< Version of memory Tech feature block.
MEM_TECH_FEAT *MemTInitializeLrdimm; ///< LRDIMM initialization
} MEM_TECH_LRDIMM;
/**
* MEMORY NORTHBRIDGE SUPPORT STRUCT - This structure groups the Northbridge dependent
* options together in a list to provide a single access point for all code to use
* and to ensure that everything corresponding to the same NB type is grouped together.
*
* The Technology Block pointers are not included in this structure because DRAM technology
* needs to be decoupled from the northbridge type.
*
*/
typedef struct _MEM_NB_SUPPORT {
UINT16 MemNBSupportVersion; ///< Version of northbridge support.
MEM_NB_CONSTRUCTOR *MemConstructNBBlock; ///< NorthBridge block constructor.
MEM_INITIALIZER *MemNInitDefaults; ///< Default value initialization for MEM_DATA_STRUCT.
MEM_FEAT_BLOCK_NB *MemFeatBlock; ///< Memory feature block.
MEM_RESUME_CONSTRUCTOR *MemS3ResumeConstructNBBlock; ///< S3 memory initialization northbridge block constructor.
MEM_IDENDIMM_CONSTRUCTOR *MemIdentifyDimmConstruct; ///< Constructor for address to dimm identification.
} MEM_NB_SUPPORT;
/*
* MEMORY Non-Training FEATURES - This structure serves as a vector table for standard
* memory non-training feature implementation functions. It contains vectors for all of the
* features that are supported by the various Technology devices supported by
* AGESA.
*/
/**
* MAIN TRAINING SEQUENCE LIST - This structure serves as vector table for memory features
* that shared between all northbridge devices.
*/
typedef struct _MEM_FEAT_TRAIN_SEQ {
UINT16 OptMemTrainingSequenceListVersion; ///< Version of main feature block.
OPTION_MEM_FEATURE_NB *TrainingSequence; ///< Training Sequence function.
OPTION_MEM_FEATURE_NB *TrainingSequenceEnabled; ///< Enable function.
MEM_TECH_FEAT_BLOCK *MemTechFeatBlock; ///< Memory feature block.
} MEM_FEAT_TRAIN_SEQ;
/**
* PLATFORM SPECIFIC CONFIGURATION BLOCK - This structure groups various PSC table
* entries which are used by PSC engine
*/
typedef struct _MEM_PSC_TABLE_BLOCK {
PSC_TBL_ENTRY **TblEntryOfMaxFreq; ///< Table entry of MaxFreq.
PSC_TBL_ENTRY **TblEntryOfDramTerm; ///< Table entry of Dram Term.
PSC_TBL_ENTRY **TblEntryOfODTPattern; ///< Table entry of ODT Pattern.
PSC_TBL_ENTRY **TblEntryOfSAO; ///< Table entry of Slow access mode, AddrTmg and ODC..
PSC_TBL_ENTRY **TblEntryOfMR0WR; ///< Table entry of MR0[WR].
PSC_TBL_ENTRY **TblEntryOfMR0CL; ///< Table entry of MR0[CL].
PSC_TBL_ENTRY **TblEntryOfRC2IBT; ///< Table entry of RC2 IBT.
PSC_TBL_ENTRY **TblEntryOfRC10OpSpeed; ///< Table entry of RC10[operating speed].
PSC_TBL_ENTRY **TblEntryOfLRIBT;///< Table entry of LRDIMM IBT
PSC_TBL_ENTRY **TblEntryOfLRNPR; ///< Table entry of LRDIMM F0RC13[NumPhysicalRanks].
PSC_TBL_ENTRY **TblEntryOfLRNLR; ///< Table entry of LRDIMM F0RC13[NumLogicalRanks].
PSC_TBL_ENTRY **TblEntryOfGen; ///< Table entry of CLKDis map and CKE, ODT as well as ChipSel tri-state map.
} MEM_PSC_TABLE_BLOCK;
typedef BOOLEAN MEM_PSC_FLOW (
IN OUT MEM_NB_BLOCK *NBPtr,
IN MEM_PSC_TABLE_BLOCK *EntryOfTables
);
/**
* PLATFORM SPECIFIC CONFIGURATION FLOW BLOCK - Pointers to the sub-engines of platform
* specific configuration.
*/
typedef struct _MEM_PSC_FLOW_BLOCK {
MEM_PSC_TABLE_BLOCK *EntryOfTables; ///<Entry of NB specific MEM_PSC_TABLE_BLOCK
MEM_PSC_FLOW *MaxFrequency; ///< Sub-engine which performs "Max Frequency" value extraction.
MEM_PSC_FLOW *DramTerm; ///< Sub-engine which performs "Dram Term" value extraction.
MEM_PSC_FLOW *ODTPattern; ///< Sub-engine which performs "ODT Pattern" value extraction.
MEM_PSC_FLOW *SAO; ///< Sub-engine which performs "Slow access mode, AddrTmg and ODC" value extraction.
MEM_PSC_FLOW *MR0WrCL; ///< Sub-engine which performs "MR0[WR] and MR0[CL]" value extraction.
MEM_PSC_FLOW *RC2IBT; ///< Sub-engine "RC2 IBT" value extraction.
MEM_PSC_FLOW *RC10OpSpeed; ///< Sub-engine "RC10[operating speed]" value extraction.
MEM_PSC_FLOW *LRIBT; ///< Sub-engine "LRDIMM IBT" value extraction.
MEM_PSC_FLOW *LRNPR; ///< Sub-engine "LRDIMM F0RC13[NumPhysicalRanks]" value extraction.
MEM_PSC_FLOW *LRNLR; ///< Sub-engine "LRDIMM F0RC13[NumLogicalRanks]" value extraction.
} MEM_PSC_FLOW_BLOCK;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
/* Feature Default Return */
BOOLEAN MemFDefRet (
IN OUT MEM_NB_BLOCK *NBPtr
);
BOOLEAN MemMDefRet (
IN MEM_MAIN_DATA_BLOCK *MMPtr
);
BOOLEAN MemMDefRetFalse (
IN MEM_MAIN_DATA_BLOCK *MMPtr
);
BOOLEAN MemNIdentifyDimmConstructorRetDef (
IN OUT MEM_NB_BLOCK *NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
IN UINT8 NodeID
);
/* Table Feature Default Return */
UINT8 MemFTableDefRet (
IN OUT MEM_TABLE_ALIAS **MTPtr
);
/* S3 Feature Default Return */
BOOLEAN MemFS3DefConstructorRet (
IN OUT VOID *S3NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
IN UINT8 NodeID
);
BOOLEAN
MemProcessConditionalOverrides (
IN PSO_TABLE *PlatformMemoryConfiguration,
IN OUT MEM_NB_BLOCK *NBPtr,
IN UINT8 PsoAction,
IN UINT8 Dimm
);
#endif // _OPTION_MEMORY_H_

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/* $NoKeywords:$ */
/**
* @file
*
* AMD Memory option API.
*
* Contains structures and values used to control the Memory option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_MEMORY_RECOVERY_H_
#define _OPTION_MEMORY_RECOVERY_H_
#include "mm.h"
#include "mn.h"
#include "mt.h"
typedef BOOLEAN MEM_REC_NB_CONSTRUCTOR (
IN OUT MEM_NB_BLOCK *NBPtr,
IN OUT MEM_DATA_STRUCT *MemPtr,
IN UINT8 NodeID
);
typedef VOID MEM_REC_TECH_CONSTRUCTOR (
IN OUT MEM_TECH_BLOCK *TechPtr,
IN OUT MEM_NB_BLOCK *NBPtr
);
#endif // _OPTION_MEMORY_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Memory
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 49896 $ @e \$Date: 2011-03-30 16:18:18 +0800 (Wed, 30 Mar 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_MEMORY_RECOVERY_INSTALL_H_
#define _OPTION_MEMORY_RECOVERY_INSTALL_H_
#if (AGESA_ENTRY_INIT_RECOVERY == TRUE)
#define MEM_REC_NB_SUPPORT_OR
#if (OPTION_MEMCTLR_DR == TRUE)
extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockDR;
#define MEM_REC_NB_SUPPORT_DR MemRecConstructNBBlockDR,
#else
#define MEM_REC_NB_SUPPORT_DR
#endif
#if (OPTION_MEMCTLR_RB == TRUE)
extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockRb;
#define MEM_REC_NB_SUPPORT_RB MemRecConstructNBBlockRb,
#else
#define MEM_REC_NB_SUPPORT_RB
#endif
#if (OPTION_MEMCTLR_DA == TRUE)
extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockDA;
#define MEM_REC_NB_SUPPORT_DA MemRecConstructNBBlockDA,
#else
#define MEM_REC_NB_SUPPORT_DA
#endif
#if (OPTION_MEMCTLR_NI == TRUE)
extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockNi;
#define MEM_REC_NB_SUPPORT_NI MemRecConstructNBBlockNi,
#else
#define MEM_REC_NB_SUPPORT_NI
#endif
#if (OPTION_MEMCTLR_PH == TRUE)
extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockPh;
#define MEM_REC_NB_SUPPORT_PH MemRecConstructNBBlockPh,
#else
#define MEM_REC_NB_SUPPORT_PH
#endif
#if (OPTION_MEMCTLR_HY == TRUE)
extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockHY;
#define MEM_REC_NB_SUPPORT_HY MemRecConstructNBBlockHY,
#else
#define MEM_REC_NB_SUPPORT_HY
#endif
#if (OPTION_MEMCTLR_C32 == TRUE)
extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockC32;
#define MEM_REC_NB_SUPPORT_C32 MemRecConstructNBBlockC32,
#else
#define MEM_REC_NB_SUPPORT_C32
#endif
#if (OPTION_MEMCTLR_LN == TRUE)
extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockLN;
#define MEM_REC_NB_SUPPORT_LN MemRecConstructNBBlockLN,
#else
#define MEM_REC_NB_SUPPORT_LN
#endif
#if (OPTION_MEMCTLR_ON == TRUE)
extern MEM_REC_NB_CONSTRUCTOR MemRecConstructNBBlockON;
#define MEM_REC_NB_SUPPORT_ON MemRecConstructNBBlockON,
#else
#define MEM_REC_NB_SUPPORT_ON
#endif
MEM_REC_NB_CONSTRUCTOR* MemRecNBInstalled[] = {
MEM_REC_NB_SUPPORT_DR
MEM_REC_NB_SUPPORT_RB
MEM_REC_NB_SUPPORT_DA
MEM_REC_NB_SUPPORT_PH
MEM_REC_NB_SUPPORT_HY
MEM_REC_NB_SUPPORT_C32
MEM_REC_NB_SUPPORT_LN
MEM_REC_NB_SUPPORT_OR
MEM_REC_NB_SUPPORT_ON
MEM_REC_NB_SUPPORT_NI
NULL
};
#define MEM_REC_TECH_CONSTRUCTOR_DDR2
#if (OPTION_DDR3 == TRUE)
extern MEM_REC_TECH_CONSTRUCTOR MemRecConstructTechBlock3;
#define MEM_REC_TECH_CONSTRUCTOR_DDR3 MemRecConstructTechBlock3,
#else
#define MEM_REC_TECH_CONSTRUCTOR_DDR3
#endif
MEM_REC_TECH_CONSTRUCTOR* MemRecTechInstalled[] = {
MEM_REC_TECH_CONSTRUCTOR_DDR3
MEM_REC_TECH_CONSTRUCTOR_DDR2
NULL
};
#if OPTION_MEMCTLR_DR
#define PSC_REC_DR_UDIMM_DDR2
#define PSC_REC_DR_UDIMM_DDR3 MemRecNGetPsCfgUDIMM3Nb,
#define PSC_REC_DR_RDIMM_DDR2
#define PSC_REC_DR_RDIMM_DDR3 MemRecNGetPsCfgRDIMM3Nb,
#define PSC_REC_DR_SODIMM_DDR2
#define PSC_REC_DR_SODIMM_DDR3 MemRecNGetPsCfgSODIMM3Nb,
#endif
#if ((OPTION_MEMCTLR_DA == TRUE) || (OPTION_MEMCTLR_Ni == TRUE) || (OPTION_MEMCTLR_PH == TRUE) || (OPTION_MEMCTLR_RB == TRUE))
#define PSC_REC_DA_UDIMM_DDR3 MemRecNGetPsCfgUDIMM3Nb,
#define PSC_REC_DA_SODIMM_DDR2
#define PSC_REC_DA_SODIMM_DDR3 MemRecNGetPsCfgSODIMM3Nb,
#endif
#if OPTION_MEMCTLR_HY
#define PSC_REC_HY_UDIMM_DDR3 MemRecNGetPsCfgUDIMM3Nb,
#define PSC_REC_HY_RDIMM_DDR3 MemRecNGetPsCfgRDIMM3Nb,
#endif
#if OPTION_MEMCTLR_C32
#define PSC_REC_C32_UDIMM_DDR3 MemRecNGetPsCfgUDIMM3Nb,
#define PSC_REC_C32_RDIMM_DDR3 MemRecNGetPsCfgRDIMM3Nb,
#endif
#if OPTION_MEMCTLR_OR
#define PSC_REC_OR_UDIMM_DDR3 //MemRecNGetPsCfgUDIMM3OR,
#define PSC_REC_OR_RDIMM_DDR3 //MemRecNGetPsCfgRDIMM3OR,
#endif
#ifndef PSC_REC_DR_UDIMM_DDR2
#define PSC_REC_DR_UDIMM_DDR2
#endif
#ifndef PSC_REC_DR_UDIMM_DDR3
#define PSC_REC_DR_UDIMM_DDR3
#endif
#ifndef PSC_REC_DR_RDIMM_DDR2
#define PSC_REC_DR_RDIMM_DDR2
#endif
#ifndef PSC_REC_DR_RDIMM_DDR3
#define PSC_REC_DR_RDIMM_DDR3
#endif
#ifndef PSC_REC_DR_SODIMM_DDR2
#define PSC_REC_DR_SODIMM_DDR2
#endif
#ifndef PSC_REC_DR_SODIMM_DDR3
#define PSC_REC_DR_SODIMM_DDR3
#endif
#ifndef PSC_REC_DA_UDIMM_DDR3
#define PSC_REC_DA_UDIMM_DDR3
#endif
#ifndef PSC_REC_DA_SODIMM_DDR2
#define PSC_REC_DA_SODIMM_DDR2
#endif
#ifndef PSC_REC_DA_SODIMM_DDR3
#define PSC_REC_DA_SODIMM_DDR3
#endif
#ifndef PSC_REC_HY_UDIMM_DDR3
#define PSC_REC_HY_UDIMM_DDR3
#endif
#ifndef PSC_REC_HY_RDIMM_DDR3
#define PSC_REC_HY_RDIMM_DDR3
#endif
#ifndef PSC_REC_C32_UDIMM_DDR3
#define PSC_REC_C32_UDIMM_DDR3
#endif
#ifndef PSC_REC_C32_RDIMM_DDR3
#define PSC_REC_C32_RDIMM_DDR3
#endif
#ifndef PSC_REC_OR_UDIMM_DDR3
#define PSC_REC_OR_UDIMM_DDR3
#endif
#ifndef PSC_REC_OR_RDIMM_DDR3
#define PSC_REC_OR_RDIMM_DDR3
#endif
MEM_PLATFORM_CFG* memRecPlatformTypeInstalled[] = {
PSC_REC_DR_UDIMM_DDR2
PSC_REC_DR_RDIMM_DDR2
PSC_REC_DR_SODIMM_DDR2
PSC_REC_DR_UDIMM_DDR3
PSC_REC_DR_RDIMM_DDR3
PSC_REC_DR_SODIMM_DDR3
PSC_REC_DA_SODIMM_DDR2
PSC_REC_DA_UDIMM_DDR3
PSC_REC_DA_SODIMM_DDR3
PSC_REC_HY_UDIMM_DDR3
PSC_REC_HY_RDIMM_DDR3
PSC_REC_C32_UDIMM_DDR3
PSC_REC_C32_RDIMM_DDR3
PSC_REC_OR_UDIMM_DDR3
PSC_REC_OR_RDIMM_DDR3
NULL
};
/*---------------------------------------------------------------------------------------------------
* EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
*
*
*---------------------------------------------------------------------------------------------------
*/
#define MEM_PSC_REC_FLOW_BLOCK_END NULL
#define PSC_REC_TBL_END NULL
#define MEM_REC_PSC_FLOW_DEFTRUE (BOOLEAN (*) (MEM_NB_BLOCK*, MEM_PSC_TABLE_BLOCK *)) memDefTrue
#if OPTION_MEMCTLR_OR
#if OPTION_UDIMMS
#if OPTION_AM3_SOCKET_SUPPORT
extern PSC_TBL_ENTRY RecDramTermTblEntUAM3;
#define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_AM3 &RecDramTermTblEntUAM3,
extern PSC_TBL_ENTRY RecOdtPat1DTblEntUAM3;
#define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3 &RecOdtPat1DTblEntUAM3,
extern PSC_TBL_ENTRY RecOdtPat2DTblEntUAM3;
#define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3 &RecOdtPat2DTblEntUAM3,
extern PSC_TBL_ENTRY RecOdtPat3DTblEntUAM3;
#define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3 &RecOdtPat3DTblEntUAM3,
extern PSC_TBL_ENTRY RecSAOTblEntUAM3;
#define PSC_REC_TBL_OR_UDIMM3_SAO_AM3 &RecSAOTblEntUAM3,
#endif
#if OPTION_C32_SOCKET_SUPPORT
extern PSC_TBL_ENTRY RecDramTermTblEntUC32;
#define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_C32 &RecDramTermTblEntUC32,
extern PSC_TBL_ENTRY RecOdtPat1DTblEntUC32;
#define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_C32 &RecOdtPat1DTblEntUC32,
extern PSC_TBL_ENTRY RecOdtPat2DTblEntUC32;
#define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_C32 &RecOdtPat2DTblEntUC32,
extern PSC_TBL_ENTRY RecOdtPat3DTblEntUC32;
#define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_C32 &RecOdtPat3DTblEntUC32,
extern PSC_TBL_ENTRY RecSAOTblEntUC32;
#define PSC_REC_TBL_OR_UDIMM3_SAO_C32 &RecSAOTblEntUC32,
#endif
#if OPTION_G34_SOCKET_SUPPORT
extern PSC_TBL_ENTRY RecDramTermTblEntUG34;
#define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_G34 &RecDramTermTblEntUG34,
extern PSC_TBL_ENTRY RecOdtPat1DTblEntUG34;
#define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_G34 &RecOdtPat1DTblEntUG34,
extern PSC_TBL_ENTRY RecOdtPat2DTblEntUG34;
#define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_G34 &RecOdtPat2DTblEntUG34,
extern PSC_TBL_ENTRY RecOdtPat3DTblEntUG34;
#define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_G34 &RecOdtPat3DTblEntUG34,
extern PSC_TBL_ENTRY RecSAOTblEntUG34;
#define PSC_REC_TBL_OR_UDIMM3_SAO_G34 &RecSAOTblEntUG34,
#endif
#endif
#if OPTION_RDIMMS
#if OPTION_C32_SOCKET_SUPPORT
extern PSC_TBL_ENTRY RecDramTermTblEntRC32;
#define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_C32 &RecDramTermTblEntRC32,
extern PSC_TBL_ENTRY RecOdtPat1DTblEntRC32;
#define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_C32 &RecOdtPat1DTblEntRC32,
extern PSC_TBL_ENTRY RecOdtPat2DTblEntRC32;
#define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_C32 &RecOdtPat2DTblEntRC32,
extern PSC_TBL_ENTRY RecOdtPat3DTblEntRC32;
#define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_C32 &RecOdtPat3DTblEntRC32,
extern PSC_TBL_ENTRY RecSAOTblEntRC32;
#define PSC_REC_TBL_OR_RDIMM3_SAO_C32 &RecSAOTblEntRC32,
extern PSC_TBL_ENTRY RecRC2IBTTblEntRC32;
#define PSC_REC_TBL_OR_RDIMM3_RC2IBT_C32 &RecRC2IBTTblEntRC32,
#endif
#if OPTION_G34_SOCKET_SUPPORT
extern PSC_TBL_ENTRY RecDramTermTblEntRG34;
#define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_G34 &RecDramTermTblEntRG34,
extern PSC_TBL_ENTRY RecOdtPat1DTblEntRG34;
#define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_G34 &RecOdtPat1DTblEntRG34,
extern PSC_TBL_ENTRY RecOdtPat2DTblEntRG34;
#define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_G34 &RecOdtPat2DTblEntRG34,
extern PSC_TBL_ENTRY RecOdtPat3DTblEntRG34;
#define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_G34 &RecOdtPat3DTblEntRG34,
extern PSC_TBL_ENTRY RecSAOTblEntRG34;
#define PSC_REC_TBL_OR_RDIMM3_SAO_G34 &RecSAOTblEntRG34,
extern PSC_TBL_ENTRY RecRC2IBTTblEntRG34;
#define PSC_REC_TBL_OR_RDIMM3_RC2IBT_G34 &RecRC2IBTTblEntRG34,
#endif
#endif
//#if OPTION_SODIMMS
//#endif
//#if OPTION_LRDIMMS
//#endif
extern PSC_TBL_ENTRY RecMR0WrTblEntry;
#define PSC_REC_TBL_OR_MR0_WR &RecMR0WrTblEntry,
extern PSC_TBL_ENTRY RecMR0CLTblEntry;
#define PSC_REC_TBL_OR_MR0_CL &RecMR0CLTblEntry,
#ifndef PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_AM3
#define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_AM3
#endif
#ifndef PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_C32
#define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_C32
#endif
#ifndef PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_G34
#define PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_G34
#endif
#ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3
#define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3
#endif
#ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_C32
#define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_C32
#endif
#ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_G34
#define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_G34
#endif
#ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3
#define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3
#endif
#ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_C32
#define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_C32
#endif
#ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_G34
#define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_G34
#endif
#ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
#define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
#endif
#ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
#define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
#endif
#ifndef PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
#define PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
#endif
#ifndef PSC_REC_TBL_OR_UDIMM3_SAO_AM3
#define PSC_REC_TBL_OR_UDIMM3_SAO_AM3
#endif
#ifndef PSC_REC_TBL_OR_UDIMM3_SAO_C32
#define PSC_REC_TBL_OR_UDIMM3_SAO_C32
#endif
#ifndef PSC_REC_TBL_OR_UDIMM3_SAO_G34
#define PSC_REC_TBL_OR_UDIMM3_SAO_G34
#endif
#ifndef PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_AM3
#define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_AM3
#endif
#ifndef PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_C32
#define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_C32
#endif
#ifndef PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_G34
#define PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_G34
#endif
#ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3
#define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3
#endif
#ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_C32
#define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_C32
#endif
#ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_G34
#define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_G34
#endif
#ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3
#define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3
#endif
#ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_C32
#define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_C32
#endif
#ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_G34
#define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_G34
#endif
#ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3
#define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3
#endif
#ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_C32
#define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_C32
#endif
#ifndef PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_G34
#define PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_G34
#endif
#ifndef PSC_REC_TBL_OR_RDIMM3_SAO_AM3
#define PSC_REC_TBL_OR_RDIMM3_SAO_AM3
#endif
#ifndef PSC_REC_TBL_OR_RDIMM3_SAO_C32
#define PSC_REC_TBL_OR_RDIMM3_SAO_C32
#endif
#ifndef PSC_REC_TBL_OR_RDIMM3_SAO_G34
#define PSC_REC_TBL_OR_RDIMM3_SAO_G34
#endif
#ifndef PSC_REC_TBL_OR_RDIMM3_RC2IBT_AM3
#define PSC_REC_TBL_OR_RDIMM3_RC2IBT_AM3
#endif
#ifndef PSC_REC_TBL_OR_RDIMM3_RC2IBT_C32
#define PSC_REC_TBL_OR_RDIMM3_RC2IBT_C32
#endif
#ifndef PSC_REC_TBL_OR_RDIMM3_RC2IBT_G34
#define PSC_REC_TBL_OR_RDIMM3_RC2IBT_G34
#endif
#ifndef PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_AM3
#define PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_AM3
#endif
#ifndef PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_C32
#define PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_C32
#endif
#ifndef PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_G34
#define PSC_REC_TBL_OR_RDIMM3_RC10OPSPD_G34
#endif
PSC_TBL_ENTRY* memRecPSCTblDramTermArrayOR[] = {
PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_AM3
PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_C32
PSC_REC_TBL_OR_UDIMM3_DRAM_TERM_G34
PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_AM3
PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_C32
PSC_REC_TBL_OR_RDIMM3_DRAM_TERM_G34
PSC_REC_TBL_END
};
PSC_TBL_ENTRY* memRecPSCTblODTPatArrayOR[] = {
PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_AM3
PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_AM3
PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_AM3
PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_AM3
PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_AM3
PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_AM3
PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_C32
PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_C32
PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_C32
PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_C32
PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_C32
PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_C32
PSC_REC_TBL_OR_UDIMM3_ODT_PAT_1D_G34
PSC_REC_TBL_OR_UDIMM3_ODT_PAT_2D_G34
PSC_REC_TBL_OR_UDIMM3_ODT_PAT_3D_G34
PSC_REC_TBL_OR_RDIMM3_ODT_PAT_1D_G34
PSC_REC_TBL_OR_RDIMM3_ODT_PAT_2D_G34
PSC_REC_TBL_OR_RDIMM3_ODT_PAT_3D_G34
PSC_REC_TBL_END
};
PSC_TBL_ENTRY* memRecPSCTblSAOArrayOR[] = {
PSC_REC_TBL_OR_UDIMM3_SAO_AM3
PSC_REC_TBL_OR_UDIMM3_SAO_C32
PSC_REC_TBL_OR_UDIMM3_SAO_G34
PSC_REC_TBL_OR_RDIMM3_SAO_AM3
PSC_REC_TBL_OR_RDIMM3_SAO_C32
PSC_REC_TBL_OR_RDIMM3_SAO_G34
PSC_REC_TBL_END
};
PSC_TBL_ENTRY* memRecPSCTblMR0WRArrayOR[] = {
PSC_REC_TBL_OR_MR0_WR
PSC_REC_TBL_END
};
PSC_TBL_ENTRY* memRecPSCTblMR0CLArrayOR[] = {
PSC_REC_TBL_OR_MR0_CL
PSC_REC_TBL_END
};
PSC_TBL_ENTRY* memRecPSCTblRC2IBTArrayOR[] = {
PSC_REC_TBL_OR_RDIMM3_RC2IBT_AM3
PSC_REC_TBL_OR_RDIMM3_RC2IBT_C32
PSC_REC_TBL_OR_RDIMM3_RC2IBT_G34
PSC_REC_TBL_END
};
MEM_PSC_TABLE_BLOCK memRecPSCTblBlockOr = {
NULL,
(PSC_TBL_ENTRY **)&memRecPSCTblDramTermArrayOR,
(PSC_TBL_ENTRY **)&memRecPSCTblODTPatArrayOR,
(PSC_TBL_ENTRY **)&memRecPSCTblSAOArrayOR,
(PSC_TBL_ENTRY **)&memRecPSCTblMR0WRArrayOR,
(PSC_TBL_ENTRY **)&memRecPSCTblMR0CLArrayOR,
(PSC_TBL_ENTRY **)&memRecPSCTblRC2IBTArrayOR,
NULL,
NULL,
NULL,
NULL,
NULL
};
extern MEM_PSC_FLOW MemPRecGetRttNomWr;
#define PSC_REC_FLOW_OR_DRAM_TERM MemPRecGetRttNomWr
extern MEM_PSC_FLOW MemPRecGetODTPattern;
#define PSC_REC_FLOW_OR_ODT_PATTERN MemPRecGetODTPattern
extern MEM_PSC_FLOW MemPRecGetSAO;
#define PSC_REC_FLOW_OR_SAO MemPRecGetSAO
extern MEM_PSC_FLOW MemPRecGetMR0WrCL;
#define PSC_REC_FLOW_OR_MR0_WRCL MemPRecGetMR0WrCL
#if OPTION_RDIMMS
extern MEM_PSC_FLOW MemPRecGetRC2IBT;
#define PSC_REC_FLOW_OR_RC2_IBT MemPRecGetRC2IBT
#endif
//#if OPTION_LRDIMMS
extern MEM_PSC_FLOW MemPRecGetLRIBT;
#define PSC_REC_FLOW_OR_LR_IBT MemPRecGetLRIBT
extern MEM_PSC_FLOW MemPRecGetLRNPR;
#define PSC_REC_FLOW_OR_LR_NPR MemPRecGetLRNPR
extern MEM_PSC_FLOW MemPRecGetLRNLR;
#define PSC_REC_FLOW_OR_LR_NLR MemPRecGetLRNLR
//#endif
#ifndef PSC_REC_FLOW_OR_DRAM_TERM
#define PSC_REC_FLOW_OR_DRAM_TERM MEM_REC_PSC_FLOW_DEFTRUE
#endif
#ifndef PSC_REC_FLOW_OR_ODT_PATTERN
#define PSC_REC_FLOW_OR_ODT_PATTERN MEM_REC_PSC_FLOW_DEFTRUE
#endif
#ifndef PSC_REC_FLOW_OR_SAO
#define PSC_REC_FLOW_OR_SAO MEM_REC_PSC_FLOW_DEFTRUE
#endif
#ifndef PSC_REC_FLOW_OR_MR0_WRCL
#define PSC_REC_FLOW_OR_MR0_WRCL MEM_REC_PSC_FLOW_DEFTRUE
#endif
#ifndef PSC_REC_FLOW_OR_RC2_IBT
#define PSC_REC_FLOW_OR_RC2_IBT MEM_REC_PSC_FLOW_DEFTRUE
#endif
#ifndef PSC_REC_FLOW_OR_LR_IBT
#define PSC_REC_FLOW_OR_LR_IBT MEM_REC_PSC_FLOW_DEFTRUE
#endif
#ifndef PSC_REC_FLOW_OR_LR_NPR
#define PSC_REC_FLOW_OR_LR_NPR MEM_REC_PSC_FLOW_DEFTRUE
#endif
#ifndef PSC_REC_FLOW_OR_LR_NLR
#define PSC_REC_FLOW_OR_LR_NLR MEM_REC_PSC_FLOW_DEFTRUE
#endif
MEM_PSC_FLOW_BLOCK memRecPlatSpecFlowOR = {
&memRecPSCTblBlockOr,
NULL,
PSC_REC_FLOW_OR_DRAM_TERM,
PSC_REC_FLOW_OR_ODT_PATTERN,
PSC_REC_FLOW_OR_SAO,
PSC_REC_FLOW_OR_MR0_WRCL,
PSC_REC_FLOW_OR_RC2_IBT,
NULL,
PSC_REC_FLOW_OR_LR_IBT,
PSC_REC_FLOW_OR_LR_NPR,
PSC_REC_FLOW_OR_LR_NLR
};
#define MEM_PSC_REC_FLOW_BLOCK_OR &memRecPlatSpecFlowOR,
#else
#define MEM_PSC_REC_FLOW_BLOCK_OR
#endif
MEM_PSC_FLOW_BLOCK* memRecPlatSpecFlowArray[] = {
MEM_PSC_REC_FLOW_BLOCK_OR
MEM_PSC_REC_FLOW_BLOCK_END
};
#else
/*---------------------------------------------------------------------------------------------------
* DEFAULT TECHNOLOGY BLOCK
*
*
*---------------------------------------------------------------------------------------------------
*/
MEM_TECH_CONSTRUCTOR* MemRecTechInstalled[] = { // Types of technology installed
NULL
};
/*---------------------------------------------------------------------------------------------------
* DEFAULT NORTHBRIDGE SUPPORT LIST
*
*
*---------------------------------------------------------------------------------------------------
*/
MEM_NB_SUPPORT* MemRecNBInstalled[] = {
NULL
};
/*----------------------------------------------------------------------
* DEFAULT PSCFG DEFINITIONS
*
*----------------------------------------------------------------------
*/
MEM_PLATFORM_CFG* memRecPlatformTypeInstalled[] = {
NULL
};
/*----------------------------------------------------------------------
* EXTRACTABLE PLATFORM SPECIFIC CONFIGURATION
*
*----------------------------------------------------------------------
*/
MEM_PSC_FLOW_BLOCK* memRecPlatSpecFlowArray[] = {
NULL
};
#endif
#endif // _OPTION_MEMORY_RECOVERY_INSTALL_H_

116
src/vendorcode/amd/agesa/f12/Include/OptionMsgBasedC1eInstall.h Executable file
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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Message-Based C1e
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_MSG_BASED_C1E_INSTALL_H_
#define _OPTION_MSG_BASED_C1E_INSTALL_H_
#include "cpuMsgBasedC1e.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_MSG_BASED_C1E_FEAT
#define F10_MSG_BASED_C1E_SUPPORT
#define F15_MSG_BASED_C1E_SUPPORT
#if OPTION_MSG_BASED_C1E == TRUE
#if (AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE) || (AGESA_ENTRY_INIT_RESUME == TRUE)
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
#if OPTION_FAMILY10H_HY == TRUE
#if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE)
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e;
#undef OPTION_MSG_BASED_C1E_FEAT
#define OPTION_MSG_BASED_C1E_FEAT &CpuFeatureMsgBasedC1e,
#endif
#endif
#endif
#endif
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
#if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE || OPTION_AM3_SOCKET_SUPPORT == TRUE)
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureMsgBasedC1e;
#undef OPTION_MSG_BASED_C1E_FEAT
#define OPTION_MSG_BASED_C1E_FEAT &CpuFeatureMsgBasedC1e,
#endif
#endif
#endif
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
#if OPTION_FAMILY10H_HY == TRUE
#if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE)
extern CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F10MsgBasedC1e;
#undef F10_MSG_BASED_C1E_SUPPORT
#define F10_MSG_BASED_C1E_SUPPORT {AMD_FAMILY_10_HY, &F10MsgBasedC1e},
#endif
#endif
#endif
#endif
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
#if (OPTION_G34_SOCKET_SUPPORT == TRUE) || (OPTION_C32_SOCKET_SUPPORT == TRUE || OPTION_AM3_SOCKET_SUPPORT == TRUE)
extern CONST MSG_BASED_C1E_FAMILY_SERVICES ROMDATA F15OrMsgBasedC1e;
#undef F15_MSG_BASED_C1E_SUPPORT
#define F15_MSG_BASED_C1E_SUPPORT {AMD_FAMILY_15, &F15OrMsgBasedC1e},
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA MsgBasedC1eFamilyServiceArray[] =
{
F10_MSG_BASED_C1E_SUPPORT
F15_MSG_BASED_C1E_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA MsgBasedC1eFamilyServiceTable =
{
(sizeof (MsgBasedC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&MsgBasedC1eFamilyServiceArray[0]
};
#endif
#endif
#endif // _OPTION_MSG_BASED_C1E_INSTALL_H_

184
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/* $NoKeywords:$ */
/**
* @file
*
* AMD Multi-socket option API.
*
* Contains structures and values used to control the multi-socket option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 48937 $ @e \$Date: 2011-03-15 03:37:15 +0800 (Tue, 15 Mar 2011) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_MULTISOCKET_H_
#define _OPTION_MULTISOCKET_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/**
* This function loops through all possible socket locations, gathering the number
* of power management steps each populated socket requires, and returns the
* highest number.
*
* @param[out] NumSystemSteps Maximum number of system steps required
* @param[in] StdHeader Config handle for library and services
*
*/
typedef VOID OPTION_MULTISOCKET_PM_STEPS (
OUT UINT8 *NumSystemSteps,
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function loops through all possible socket locations, starting core 0 of
* each populated socket to perform the passed in AP_TASK. After starting all
* other core 0s, the BSC will perform the AP_TASK as well. This must be run by
* the system BSC only.
*
* @param[in] TaskPtr Function descriptor
* @param[in] StdHeader Config handle for library and services
* @param[in] ConfigParams AMD entry point's CPU parameter structure
*
*/
typedef VOID OPTION_MULTISOCKET_PM_CORE0_TASK (
IN VOID *TaskPtr,
IN AMD_CONFIG_PARAMS *StdHeader,
IN VOID *ConfigParams
);
/**
* This function loops through all possible socket locations, comparing the
* maximum NB frequencies to determine the slowest. This function also
* determines if all coherent NB frequencies are equivalent.
*
* @param[in] NbPstate NB P-state number to check (0 = fastest)
* @param[in] PlatformConfig Platform profile/build option config structure.
* @param[out] SystemNbCofNumerator NB frequency numerator for the system in MHz
* @param[out] SystemNbCofDenominator NB frequency denominator for the system
* @param[out] SystemNbCofsMatch Whether or not all NB frequencies are equivalent
* @param[out] NbPstateIsEnabledOnAllCPUs Whether or not NbPstate is valid on all CPUs
* @param[in] StdHeader Config handle for library and services
*
* @retval TRUE At least one processor has NbPstate enabled.
* @retval FALSE NbPstate is disabled on all CPUs
*/
typedef BOOLEAN OPTION_MULTISOCKET_PM_NB_COF (
IN UINT32 NbPstate,
IN PLATFORM_CONFIGURATION *PlatformConfig,
OUT UINT32 *SystemNbCofNumerator,
OUT UINT32 *SystemNbCofDenominator,
OUT BOOLEAN *SystemNbCofsMatch,
OUT BOOLEAN *NbPstateIsEnabledOnAllCPUs,
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function loops through all possible socket locations, checking whether
* any populated sockets require NB COF VID programming.
*
* @param[in] StdHeader Config handle for library and services
*
*/
typedef BOOLEAN OPTION_MULTISOCKET_PM_NB_COF_UPDATE (
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function loops through all possible socket locations, collecting any
* power management initialization errors that may have occurred. These errors
* are transferred from the core 0s of the socket in which the errors occurred
* to the BSC's heap. The BSC's heap is then searched for the most severe error
* that occurred, and returns it. This function must be called by the BSC only.
*
* @param[in] StdHeader Config handle for library and services
*
*/
typedef AGESA_STATUS OPTION_MULTISOCKET_PM_GET_EVENTS (
IN AMD_CONFIG_PARAMS *StdHeader
);
/**
* This function loops through all possible socket locations and Nb Pstates,
* comparing the NB frequencies to determine the slowest NB P0 and NB Pmin in
* the system.
*
* @param[in] PlatformConfig Platform profile/build option config structure.
* @param[out] MinSysNbFreq NB frequency numerator for the system in MHz
* @param[out] MinP0NbFreq NB frequency numerator for P0 in MHz
* @param[in] StdHeader Config handle for library and services
*/
typedef VOID OPTION_MULTISOCKET_PM_NB_MIN_COF (
IN PLATFORM_CONFIGURATION *PlatformConfig,
OUT UINT32 *MinSysNbFreq,
OUT UINT32 *MinP0NbFreq,
IN AMD_CONFIG_PARAMS *StdHeader
);
#define MULTISOCKET_STRUCT_VERSION 0x01
/**
* Provide build configuration of cpu multi-socket or single socket support.
*
*/
typedef struct {
UINT16 OptMultiSocketVersion; ///< Table version
OPTION_MULTISOCKET_PM_STEPS *GetNumberOfSystemPmSteps; ///< Method: Get number of power mgt tasks
OPTION_MULTISOCKET_PM_CORE0_TASK *BscRunCodeOnAllSystemCore0s; ///< Method: Perform tasks on Core 0 of each processor
OPTION_MULTISOCKET_PM_NB_COF *GetSystemNbPstateSettings; ///< Method: Find the Northbridge frequency for the specified Nb Pstate in the system.
OPTION_MULTISOCKET_PM_NB_COF_UPDATE *GetSystemNbCofVidUpdate; ///< Method: Determine if any Northbridges in the system need to update their COF/VID.
OPTION_MULTISOCKET_PM_GET_EVENTS *BscRetrievePmEarlyInitErrors; ///< Method: Gathers error information from all Core 0s.
OPTION_MULTISOCKET_PM_NB_MIN_COF *GetMinNbCof; ///< Method: Get the minimum system and minimum P0 Northbridge frequency.
} OPTION_MULTISOCKET_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_MULTISOCKET_H_

94
src/vendorcode/amd/agesa/f12/Include/OptionMultiSocketInstall.h Executable file
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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Multiple Socket Support
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 48937 $ @e \$Date: 2011-03-15 03:37:15 +0800 (Tue, 15 Mar 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_MULTISOCKET_INSTALL_H_
#define _OPTION_MULTISOCKET_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#ifndef OPTION_MULTISOCKET
#error BLDOPT: Option not defined: "OPTION_MULTISOCKET"
#endif
#if OPTION_MULTISOCKET == TRUE
OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrMulti;
#define GET_NUM_PM_STEPS GetNumberOfSystemPmStepsPtrMulti
OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sMulti;
#define CORE0_PM_TASK RunCodeOnAllSystemCore0sMulti
OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofMulti;
#define GET_SYS_NB_COF GetSystemNbCofMulti
OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti;
#define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateMulti
OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsMulti;
#define GET_EARLY_PM_ERRORS GetEarlyPmErrorsMulti
OPTION_MULTISOCKET_PM_NB_MIN_COF GetMinNbCofMulti;
#define GET_MIN_NB_COF GetMinNbCofMulti
#else
OPTION_MULTISOCKET_PM_STEPS GetNumberOfSystemPmStepsPtrSingle;
#define GET_NUM_PM_STEPS GetNumberOfSystemPmStepsPtrSingle
OPTION_MULTISOCKET_PM_CORE0_TASK RunCodeOnAllSystemCore0sSingle;
#define CORE0_PM_TASK RunCodeOnAllSystemCore0sSingle
OPTION_MULTISOCKET_PM_NB_COF GetSystemNbCofSingle;
#define GET_SYS_NB_COF GetSystemNbCofSingle
OPTION_MULTISOCKET_PM_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle;
#define GET_SYS_NB_COF_UPDATE GetSystemNbCofVidUpdateSingle
OPTION_MULTISOCKET_PM_GET_EVENTS GetEarlyPmErrorsSingle;
#define GET_EARLY_PM_ERRORS GetEarlyPmErrorsSingle
OPTION_MULTISOCKET_PM_NB_MIN_COF GetMinNbCofSingle;
#define GET_MIN_NB_COF GetMinNbCofSingle
#endif
/* Declare the instance of the DMI option configuration structure */
OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration = {
MULTISOCKET_STRUCT_VERSION,
GET_NUM_PM_STEPS,
CORE0_PM_TASK,
GET_SYS_NB_COF,
GET_SYS_NB_COF_UPDATE,
GET_EARLY_PM_ERRORS,
GET_MIN_NB_COF
};
#endif // _OPTION_MULTISOCKET_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: Preserve Mailbox
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 50096 $ @e \$Date: 2011-04-02 06:17:10 +0800 (Sat, 02 Apr 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_PRESERVE_MAILBOX_INSTALL_H_
#define _OPTION_PRESERVE_MAILBOX_INSTALL_H_
#include "PreserveMailbox.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_PRESERVE_MAILBOX_FEAT
#define F10_PRESERVE_MAILBOX_SUPPORT
#define F15_PRESERVE_MAILBOX_SUPPORT
#if ((AGESA_ENTRY_INIT_EARLY == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE))
#if ((OPTION_FAMILY10H == TRUE) || (OPTION_FAMILY15H == TRUE))
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeaturePreserveAroundMailbox;
#undef OPTION_PRESERVE_MAILBOX_FEAT
#define OPTION_PRESERVE_MAILBOX_FEAT &CpuFeaturePreserveAroundMailbox,
#endif
#if OPTION_FAMILY10H == TRUE
CONST PRESERVE_MAILBOX_FAMILY_REGISTER ROMDATA F10PreserveMailboxRegisters [] = {
{
MAKE_SBDFO (0, 0, 0, 3, 0x168),
0x00000FFF
},
{
MAKE_SBDFO (0, 0, 0, 3, 0x170),
0x00000FFF
},
{
ILLEGAL_SBDFO,
0
}
};
CONST PRESERVE_MAILBOX_FAMILY_SERVICES ROMDATA F10PreserveMailboxServices = {
0,
TRUE,
(PRESERVE_MAILBOX_FAMILY_REGISTER *)&F10PreserveMailboxRegisters
};
#undef F10_PRESERVE_MAILBOX_SUPPORT
#define F10_PRESERVE_MAILBOX_SUPPORT {AMD_FAMILY_10, &F10PreserveMailboxServices},
#endif
#if OPTION_FAMILY15H == TRUE
CONST PRESERVE_MAILBOX_FAMILY_REGISTER ROMDATA F15PreserveMailboxRegisters [] = {
{
MAKE_SBDFO (0, 0, 0, 3, 0x168),
0x00000FFF
},
{
MAKE_SBDFO (0, 0, 0, 3, 0x170),
0x00000FFF
},
{
ILLEGAL_SBDFO,
0
}
};
CONST PRESERVE_MAILBOX_FAMILY_SERVICES ROMDATA F15PreserveMailboxServices = {
0,
TRUE,
(PRESERVE_MAILBOX_FAMILY_REGISTER *)&F15PreserveMailboxRegisters
};
#undef F15_PRESERVE_MAILBOX_SUPPORT
#define F15_PRESERVE_MAILBOX_SUPPORT {AMD_FAMILY_15, &F15PreserveMailboxServices},
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PreserveMailboxFamilyServiceArray[] =
{
F10_PRESERVE_MAILBOX_SUPPORT
F15_PRESERVE_MAILBOX_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PreserveMailboxFamilyServiceTable =
{
(sizeof (PreserveMailboxFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&PreserveMailboxFamilyServiceArray[0]
};
#endif
#endif // _OPTION_PRESERVE_MAILBOX_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* AMD ACPI PState option API.
*
* Contains structures and values used to control the PStates option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_PSTATE_H_
#define _OPTION_PSTATE_H_
#include "cpuPstateTables.h"
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_SSDT_FEATURE (
IN AMD_CONFIG_PARAMS *StdHeader,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN OUT VOID **AcpiPstatePtr
);
typedef UINT32 OPTION_ACPI_FEATURE (
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN PSTATE_LEVELING *PStateLevelingBuffer,
IN OUT VOID **AcpiPStatePtr,
IN UINT8 LocalApicId,
IN AMD_CONFIG_PARAMS *StdHeader
);
typedef AGESA_STATUS OPTION_PSTATE_GATHER (
IN AMD_CONFIG_PARAMS *StdHeader,
IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr
);
typedef AGESA_STATUS OPTION_PSTATE_LEVELING (
IN OUT S_CPU_AMD_PSTATE *PStateStrucPtr,
IN AMD_CONFIG_PARAMS *StdHeader
);
#define PSTATE_STRUCT_VERSION 0x01
/// Indirection vectors for POST/PEI PState code
typedef struct {
UINT16 OptPstateVersion; ///< revision of this structure
OPTION_PSTATE_GATHER *PstateGather; ///< vector for data gathering routine
OPTION_PSTATE_LEVELING *PstateLeveling; ///< vector for leveling routine
} OPTION_PSTATE_POST_CONFIGURATION;
/// Indirection vectors for LATE/DXE PState code
typedef struct {
UINT16 OptPstateVersion; ///< revision of this structure
OPTION_SSDT_FEATURE *SsdtFeature; ///< vector for routine to generate SSDT
OPTION_ACPI_FEATURE *PstateFeature; ///< vector for routine to generate ACPI PState Objects
OPTION_ACPI_FEATURE *CstateFeature; ///< vector for routine to generate ACPI CState Objects
BOOLEAN CfgPstatePpc; ///< boolean for creating _PPC method
BOOLEAN CfgPstatePct; ///< boolean for creating _PCT method
BOOLEAN CfgPstatePsd; ///< boolean for creating _PSD method
BOOLEAN CfgPstatePss; ///< boolean for creating _PSS method
BOOLEAN CfgPstateXpss; ///< boolean for creating _XPSS method
} OPTION_PSTATE_LATE_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_PSTATE_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: PState
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_PSTATE_INSTALL_H_
#define _OPTION_PSTATE_INSTALL_H_
#include "cpuPstateTables.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define F10_PSTATE_SERVICE_SUPPORT
#define F12_PSTATE_SERVICE_SUPPORT
#define F14_PSTATE_SERVICE_SUPPORT
#define F15_OR_PSTATE_SERVICE_SUPPORT
#define F15_TN_PSTATE_SERVICE_SUPPORT
#if ((AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_POST == TRUE))
//
//Define Pstate CPU Family service
//
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F10PstateServices;
#undef F10_PSTATE_SERVICE_SUPPORT
#define F10_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_10, &F10PstateServices},
#endif
#endif
#ifdef OPTION_FAMILY12H
#if OPTION_FAMILY12H == TRUE
extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F12PstateServices;
#undef F12_PSTATE_SERVICE_SUPPORT
#define F12_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_12, &F12PstateServices},
#endif
#endif
#ifdef OPTION_FAMILY14H
#if OPTION_FAMILY14H == TRUE
extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F14PstateServices;
#undef F14_PSTATE_SERVICE_SUPPORT
#define F14_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_14, &F14PstateServices},
#endif
#endif
#ifdef OPTION_FAMILY15H
#if OPTION_FAMILY15H == TRUE
#ifdef OPTION_FAMILY15H_OR
#if OPTION_FAMILY15H_OR == TRUE
extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15OrPstateServices;
#undef F15_OR_PSTATE_SERVICE_SUPPORT
#define F15_OR_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_15_OR, &F15OrPstateServices},
#endif
#endif
#ifdef OPTION_FAMILY15H_TN
#if OPTION_FAMILY15H_TN == TRUE
extern CONST PSTATE_CPU_FAMILY_SERVICES ROMDATA F15TnPstateServices;
#undef F15_TN_PSTATE_SERVICE_SUPPORT
#define F15_TN_PSTATE_SERVICE_SUPPORT {AMD_FAMILY_15_TN, &F15TnPstateServices},
#endif
#endif
#endif
#endif
//
//Define ACPI Pstate objects.
//
#ifndef OPTION_ACPI_PSTATES
#error BLDOPT: Option not defined: "OPTION_ACPI_PSTATES"
#endif
#if (OPTION_ACPI_PSTATES == TRUE)
// OPTION_SSDT_FEATURE GenerateSsdt;
#define USER_SSDT_MAIN GenerateSsdt
#ifndef OPTION_MULTISOCKET
#error BLDOPT: Option not defined: "OPTION_MULTISOCKET"
#endif
// OPTION_ACPI_FEATURE CreatePStateAcpiTables;
OPTION_PSTATE_GATHER PStateGatherMain;
#if ((OPTION_MULTISOCKET == TRUE) && (AGESA_ENTRY_INIT_POST == TRUE))
OPTION_PSTATE_LEVELING PStateLevelingMain;
#define USER_PSTATE_OPTION_LEVEL PStateLevelingMain
#else
OPTION_PSTATE_LEVELING PStateLevelingStub;
#define USER_PSTATE_OPTION_LEVEL PStateLevelingStub
#endif
#if AGESA_ENTRY_INIT_LATE == TRUE
#define USER_PSTATE_OPTION_MAIN CreatePStateAcpiTables
#else
OPTION_ACPI_FEATURE CreateAcpiTablesStub;
#define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub
#endif
#if AGESA_ENTRY_INIT_POST == TRUE
#define USER_PSTATE_OPTION_GATHER PStateGatherMain
#else
OPTION_PSTATE_GATHER PStateGatherStub;
#define USER_PSTATE_OPTION_GATHER PStateGatherStub
#endif
#if CFG_ACPI_PSTATES_PPC == TRUE
#define USER_PSTATE_CFG_PPC TRUE
#else
#define USER_PSTATE_CFG_PPC FALSE
#endif
#if CFG_ACPI_PSTATES_PCT == TRUE
#define USER_PSTATE_CFG_PCT TRUE
#else
#define USER_PSTATE_CFG_PCT FALSE
#endif
#if CFG_ACPI_PSTATES_PSD == TRUE
#define USER_PSTATE_CFG_PSD TRUE
#else
#define USER_PSTATE_CFG_PSD FALSE
#endif
#if CFG_ACPI_PSTATES_PSS == TRUE
#define USER_PSTATE_CFG_PSS TRUE
#else
#define USER_PSTATE_CFG_PSS FALSE
#endif
#if CFG_ACPI_PSTATES_XPSS == TRUE
#define USER_PSTATE_CFG_XPSS TRUE
#else
#define USER_PSTATE_CFG_XPSS FALSE
#endif
#if OPTION_IO_CSTATE == TRUE
// OPTION_ACPI_FEATURE CreateCStateAcpiTables;
#define USER_CSTATE_OPTION_MAIN CreateCStateAcpiTables
#else
OPTION_ACPI_FEATURE CreateAcpiTablesStub;
#define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub
#endif
#else
OPTION_SSDT_FEATURE GenerateSsdtStub;
OPTION_ACPI_FEATURE CreateAcpiTablesStub;
OPTION_PSTATE_GATHER PStateGatherStub;
OPTION_PSTATE_LEVELING PStateLevelingStub;
#define USER_SSDT_MAIN GenerateSsdtStub
#define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub
#define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub
#define USER_PSTATE_OPTION_GATHER PStateGatherStub
#define USER_PSTATE_OPTION_LEVEL PStateLevelingStub
#define USER_PSTATE_CFG_PPC FALSE
#define USER_PSTATE_CFG_PCT FALSE
#define USER_PSTATE_CFG_PSD FALSE
#define USER_PSTATE_CFG_PSS FALSE
#define USER_PSTATE_CFG_XPSS FALSE
// If ACPI Objects are disabled for PStates, we still need to check
// whether ACPI Objects are enabled for CStates
#if OPTION_IO_CSTATE == TRUE
OPTION_SSDT_FEATURE GenerateSsdt;
OPTION_PSTATE_GATHER PStateGatherMain;
OPTION_ACPI_FEATURE CreateCStateAcpiTables;
#undef USER_SSDT_MAIN
#define USER_SSDT_MAIN GenerateSsdt
#undef USER_PSTATE_OPTION_GATHER
#define USER_PSTATE_OPTION_GATHER PStateGatherMain
#undef USER_CSTATE_OPTION_MAIN
#define USER_CSTATE_OPTION_MAIN CreateCStateAcpiTables
#endif
#endif
#else
OPTION_SSDT_FEATURE GenerateSsdtStub;
OPTION_ACPI_FEATURE CreateAcpiTablesStub;
OPTION_PSTATE_GATHER PStateGatherStub;
OPTION_PSTATE_LEVELING PStateLevelingStub;
#define USER_SSDT_MAIN GenerateSsdtStub
#define USER_PSTATE_OPTION_MAIN CreateAcpiTablesStub
#define USER_CSTATE_OPTION_MAIN CreateAcpiTablesStub
#define USER_PSTATE_OPTION_GATHER PStateGatherStub
#define USER_PSTATE_OPTION_LEVEL PStateLevelingStub
#define USER_PSTATE_CFG_PPC FALSE
#define USER_PSTATE_CFG_PCT FALSE
#define USER_PSTATE_CFG_PSD FALSE
#define USER_PSTATE_CFG_PSS FALSE
#define USER_PSTATE_CFG_XPSS FALSE
#endif
/* Declare the instance of the PSTATE option configuration structure */
OPTION_PSTATE_POST_CONFIGURATION OptionPstatePostConfiguration = {
PSTATE_STRUCT_VERSION,
USER_PSTATE_OPTION_GATHER,
USER_PSTATE_OPTION_LEVEL
};
OPTION_PSTATE_LATE_CONFIGURATION OptionPstateLateConfiguration = {
PSTATE_STRUCT_VERSION,
USER_SSDT_MAIN,
USER_PSTATE_OPTION_MAIN,
USER_CSTATE_OPTION_MAIN,
USER_PSTATE_CFG_PPC,
USER_PSTATE_CFG_PCT,
USER_PSTATE_CFG_PSD,
USER_PSTATE_CFG_PSS,
USER_PSTATE_CFG_XPSS
};
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA PstateCpuFamilyServiceArray[] =
{
F10_PSTATE_SERVICE_SUPPORT
F12_PSTATE_SERVICE_SUPPORT
F14_PSTATE_SERVICE_SUPPORT
F15_OR_PSTATE_SERVICE_SUPPORT
F15_TN_PSTATE_SERVICE_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA PstateFamilyServiceTable =
{
(sizeof (PstateCpuFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&PstateCpuFamilyServiceArray[0]
};
#endif // _OPTION_PSTATE_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: S3SCRIPT
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_S3SCRIPT_INSTALL_H_
#define _OPTION_S3SCRIPT_INSTALL_H_
#include "S3SaveState.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#ifndef OPTION_S3SCRIPT
#define OPTION_S3SCRIPT FALSE //if not define assume PI not use script
#endif
#if (AGESA_ENTRY_INIT_LATE == TRUE) || (AGESA_ENTRY_INIT_ENV == TRUE) || (AGESA_ENTRY_INIT_MID == TRUE)
#if OPTION_S3SCRIPT == TRUE
#define P_S3_SCRIPT_INIT S3ScriptInitState
#endif
#endif
#if AGESA_ENTRY_INIT_LATE_RESTORE == TRUE
#if OPTION_S3SCRIPT == TRUE
#define P_S3_SCRIPT_RESTORE S3ScriptRestoreState
#endif
#endif
#ifndef P_S3_SCRIPT_INIT
#define P_S3_SCRIPT_INIT S3ScriptInitStateStub
#endif
#ifndef P_S3_SCRIPT_RESTORE
#define P_S3_SCRIPT_RESTORE S3ScriptInitStateStub
#undef GNB_S3_DISPATCH_FUNCTION_TABLE
#endif
#ifndef GNB_S3_DISPATCH_FUNCTION_TABLE
#define GNB_S3_DISPATCH_FUNCTION_TABLE
#endif
/* Declare the instance of the S3SCRIPT option configuration structure */
S3_SCRIPT_CONFIGURATION OptionS3ScriptConfiguration = {
P_S3_SCRIPT_INIT,
P_S3_SCRIPT_RESTORE
};
S3_DISPATCH_FUNCTION_ENTRY S3DispatchFunctionTable [] = {
GNB_S3_DISPATCH_FUNCTION_TABLE
{0, NULL}
};
#endif // _OPTION_S3SCRIPT_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* AMD SLIT option API.
*
* Contains structures and values used to control the SLIT option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_SLIT_H_
#define _OPTION_SLIT_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/**
* Create the ACPI System Locality Distance Information Table.
*
*/
typedef AGESA_STATUS OPTION_SLIT_FEATURE (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN OUT VOID **SlitPtr
);
/**
* Clean up DRAM used during SLIT creation.
*
*/
typedef AGESA_STATUS OPTION_SLIT_RELEASE_BUFFER (
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
#define SLIT_STRUCT_VERSION 0x01
/// The Option Configuration of SLIT
typedef struct {
UINT16 OptSlitVersion; ///< The version number of SLIT
OPTION_SLIT_FEATURE *SlitFeature; ///< The Option Feature of SLIT
OPTION_SLIT_RELEASE_BUFFER *SlitReleaseBuffer; ///< Release buffer
} OPTION_SLIT_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_SLIT_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: SLIT
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_SLIT_INSTALL_H_
#define _OPTION_SLIT_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#if AGESA_ENTRY_INIT_LATE == TRUE
#ifndef OPTION_SLIT
#error BLDOPT: Option not defined: "OPTION_SLIT"
#endif
#if OPTION_SLIT == TRUE
OPTION_SLIT_FEATURE GetAcpiSlitMain;
OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBuffer;
#define USER_SLIT_OPTION GetAcpiSlitMain
#define USER_SLIT_RELEASE_BUFFER ReleaseSlitBuffer
#else
OPTION_SLIT_FEATURE GetAcpiSlitStub;
OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub;
#define USER_SLIT_OPTION GetAcpiSlitStub
#define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub
#endif
#else
OPTION_SLIT_FEATURE GetAcpiSlitStub;
OPTION_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub;
#define USER_SLIT_OPTION GetAcpiSlitStub
#define USER_SLIT_RELEASE_BUFFER ReleaseSlitBufferStub
#endif
/* Declare the instance of the SLIT option configuration structure */
OPTION_SLIT_CONFIGURATION OptionSlitConfiguration = {
SLIT_STRUCT_VERSION,
USER_SLIT_OPTION,
USER_SLIT_RELEASE_BUFFER
};
#endif // _OPTION_SLIT_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* AMD SRAT option API.
*
* Contains structures and values used to control the SRAT option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_SRAT_H_
#define _OPTION_SRAT_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_SRAT_FEATURE (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN OUT VOID **SratPtr
);
#define SRAT_STRUCT_VERSION 0x01
/// The Option Configuration of SRAT
typedef struct {
UINT16 OptSratVersion; ///< The version number of SRAT
OPTION_SRAT_FEATURE *SratFeature; ///< The Option Feature of SRAT
} OPTION_SRAT_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_SRAT_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: SRAT
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_SRAT_INSTALL_H_
#define _OPTION_SRAT_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#if AGESA_ENTRY_INIT_LATE == TRUE
#ifndef OPTION_SRAT
#error BLDOPT: Option not defined: "OPTION_SRAT"
#endif
#if OPTION_SRAT == TRUE
OPTION_SRAT_FEATURE GetAcpiSratMain;
#define USER_SRAT_OPTION GetAcpiSratMain
#else
OPTION_SRAT_FEATURE GetAcpiSratStub;
#define USER_SRAT_OPTION GetAcpiSratStub
#endif
#else
OPTION_SRAT_FEATURE GetAcpiSratStub;
#define USER_SRAT_OPTION GetAcpiSratStub
#endif
/* Declare the instance of the WHEA option configuration structure */
OPTION_SRAT_CONFIGURATION OptionSratConfiguration = {
SRAT_STRUCT_VERSION,
USER_SRAT_OPTION
};
#endif // _OPTION_WHEA_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: SW C1e
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_SW_C1E_INSTALL_H_
#define _OPTION_SW_C1E_INSTALL_H_
#include "cpuSwC1e.h"
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#define OPTION_SW_C1E_FEAT
#define F10_SW_C1E_SUPPORT
#if AGESA_ENTRY_INIT_EARLY == TRUE
#ifdef OPTION_FAMILY10H
#if OPTION_FAMILY10H == TRUE
#if (OPTION_FAMILY10H_BL == TRUE) || (OPTION_FAMILY10H_DA == TRUE) || (OPTION_FAMILY10H_RB == TRUE) || (OPTION_FAMILY10H_PH == TRUE)
extern CONST CPU_FEATURE_DESCRIPTOR ROMDATA CpuFeatureSwC1e;
#undef OPTION_SW_C1E_FEAT
#define OPTION_SW_C1E_FEAT &CpuFeatureSwC1e,
extern CONST SW_C1E_FAMILY_SERVICES ROMDATA F10SwC1e;
#undef F10_SW_C1E_SUPPORT
#define F10_SW_C1E_SUPPORT {(AMD_FAMILY_10_BL | AMD_FAMILY_10_DA | AMD_FAMILY_10_RB | AMD_FAMILY_10_PH), &F10SwC1e},
#endif
#endif
#endif
CONST CPU_SPECIFIC_SERVICES_XLAT ROMDATA SwC1eFamilyServiceArray[] =
{
F10_SW_C1E_SUPPORT
{0, NULL}
};
CONST CPU_FAMILY_SUPPORT_TABLE ROMDATA SwC1eFamilyServiceTable =
{
(sizeof (SwC1eFamilyServiceArray) / sizeof (CPU_SPECIFIC_SERVICES_XLAT)),
&SwC1eFamilyServiceArray[0]
};
#endif
#endif // _OPTION_SW_C1E_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* AMD WHEA option API.
*
* Contains structures and values used to control the WHEA option code.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_WHEA_H_
#define _OPTION_WHEA_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
typedef AGESA_STATUS OPTION_WHEA_FEATURE (
IN OUT AMD_CONFIG_PARAMS *StdHeader,
IN OUT VOID **WheaMcePtr,
IN OUT VOID **WheaCmcPtr
);
#define WHEA_STRUCT_VERSION 0x01
/// The Option Configuration of WHEA
typedef struct {
UINT16 OptWheaVersion; ///< The version number of WHEA
OPTION_WHEA_FEATURE *WheaFeature; ///< The Option Feature of WHEA
} OPTION_WHEA_CONFIGURATION;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_WHEA_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build option: WHEA
*
* Contains AMD AGESA install macros and test conditions. Output is the
* defaults tables reflecting the User's build options selection.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Options
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTION_WHEA_INSTALL_H_
#define _OPTION_WHEA_INSTALL_H_
/* This option is designed to be included into the platform solution install
* file. The platform solution install file will define the options status.
* Check to validate the definition
*/
#if AGESA_ENTRY_INIT_LATE == TRUE
#ifndef OPTION_WHEA
#error BLDOPT: Option not defined: "OPTION_WHEA"
#endif
#if OPTION_WHEA == TRUE
OPTION_WHEA_FEATURE GetAcpiWheaMain;
#define USER_WHEA_OPTION GetAcpiWheaMain
#else
OPTION_WHEA_FEATURE GetAcpiWheaStub;
#define USER_WHEA_OPTION GetAcpiWheaStub
#endif
#else
OPTION_WHEA_FEATURE GetAcpiWheaStub;
#define USER_WHEA_OPTION GetAcpiWheaStub
#endif
/* Declare the instance of the WHEA option configuration structure */
OPTION_WHEA_CONFIGURATION OptionWheaConfiguration = {
WHEA_STRUCT_VERSION,
USER_WHEA_OPTION
};
#endif // _OPTION_WHEA_INSTALL_H_

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/* $NoKeywords:$ */
/**
* @file
*
* AGESA options structures
*
* Contains options control structures for the AGESA build options
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _OPTIONS_H_
#define _OPTIONS_H_
/**
* Provide topology limits for loops and runtime, based on supported families.
*/
typedef struct {
UINT32 PlatformNumberOfSockets; ///< The limit to the number of processors based on
///< supported families and other build options.
UINT32 PlatformNumberOfModules; ///< The limit to the number of modules in a processor, based
///< on supported families.
} OPTIONS_CONFIG_TOPOLOGY;
/**
* Dispatch Table.
*
* The push high dispatcher uses this table to find what entries are currently in the build image.
*/
typedef struct {
UINT32 FunctionId; ///< The function id specified.
IMAGE_ENTRY EntryPoint; ///< The corresponding entry point to call.
} DISPATCH_TABLE;
#ifdef BLDCFG_PLATFORM_POWER_POLICY_MODE
#define CFG_PLATFORM_POWER_POLICY_MODE (BLDCFG_PLATFORM_POWER_POLICY_MODE)
#else
#define CFG_PLATFORM_POWER_POLICY_MODE (Performance)
#endif
#ifdef BLDCFG_PCI_MMIO_BASE
#define CFG_PCI_MMIO_BASE (BLDCFG_PCI_MMIO_BASE)
#else
#define CFG_PCI_MMIO_BASE (0)
#endif
#ifdef BLDCFG_PCI_MMIO_SIZE
#define CFG_PCI_MMIO_SIZE (BLDCFG_PCI_MMIO_SIZE)
#else
#define CFG_PCI_MMIO_SIZE (0)
#endif
#ifdef BLDCFG_AP_MTRR_SETTINGS_LIST
#define CFG_AP_MTRR_SETTINGS_LIST (BLDCFG_AP_MTRR_SETTINGS_LIST)
#else
#define CFG_AP_MTRR_SETTINGS_LIST (NULL)
#endif
#endif // _OPTIONS_H_

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/* $NoKeywords:$ */
/**
* @file
*
* AMD HyperTransport option API.
*
* Contains option pre-compile logic. This file is used by the options
* installer and internally by the HT code initializers.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _OPTION_HT_H_
#define _OPTION_HT_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/**
* Provide HT build option results
*/
typedef struct {
CONST BOOLEAN IsUsingRecoveryHt; ///< Manual BUID Swap List processing should assume that HT Recovery was used.
CONST BOOLEAN IsSetHtCrcFlood; ///< Enable setting of HT CRC Flood.
///< Build-time only customizable - @BldCfgItem{BLDCFG_SET_HTCRC_SYNC_FLOOD}
CONST BOOLEAN IsUsingUnitIdClumping; ///< Enable automatically HT Spec compliant Unit Id Clumping.
///< Build-time only customizable - @BldCfgItem{BLDCFG_USE_UNIT_ID_CLUMPING}
CONST AMD_HT_INTERFACE *HtOptionPlatformDefaults; ///< A set of build time options for HT constructor.
CONST VOID *HtOptionInternalInterface; ///< Use this internal interface initializer.
CONST VOID *HtOptionInternalFeatures; ///< Use this internal feature set initializer.
CONST VOID *HtOptionFamilyNorthbridgeList; ///< Use this list of northbridge initializers.
CONST UINT8 *CONST *HtOptionBuiltinTopologies; ///< Use this list of built-in topologies.
} OPTION_HT_CONFIGURATION;
typedef AGESA_STATUS
F_OPTION_HT_INIT_RESET (
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
);
typedef F_OPTION_HT_INIT_RESET *PF_OPTION_HT_INIT_RESET;
typedef AGESA_STATUS
F_OPTION_HT_RESET_CONSTRUCTOR (
IN AMD_CONFIG_PARAMS *StdHeader,
IN AMD_HT_RESET_INTERFACE *AmdHtResetInterface
);
typedef F_OPTION_HT_RESET_CONSTRUCTOR *PF_OPTION_HT_RESET_CONSTRUCTOR;
/**
* Provide HT reset initialization build option results
*/
typedef struct {
PF_OPTION_HT_INIT_RESET HtInitReset; ///< Method: HT reset initialization.
PF_OPTION_HT_RESET_CONSTRUCTOR HtResetConstructor; ///< Method: HT reset initialization.
} OPTION_HT_INIT_RESET;
/*----------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*----------------------------------------------------------------------------------------
*/
#endif // _OPTION_HT_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Create outline and references for Build Configuration and Options Component mainpage documentation.
*
* Design guides, maintenance guides, and general documentation, are
* collected using this file onto the documentation mainpage.
* This file contains doxygen comment blocks, only.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Documentation
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/**
* @page optionmain Build Configuration and Options Documentation
*
* Additional documentation for the Build Configuration and Options component consists of
*
* - Introduction and Overview to Build Options
* - @subpage platforminstall "Platform Build Options"
* - @subpage bldcfg "Build Configuration Item Cross Reference"
* - @subpage examplecustomizations "Customization Examples"
* - Maintenance Guides:
* - For debug of the Options system, use compiler options
* @n <tt> /P /EP /C /FAs </tt> @n
* PreProcessor output is produced in an .i file in the directory where the project
* file is located.
* - Design Guides:
* - add here >>>
*
*/
/**
* @page platforminstall Platform Build Options.
*
* Build options are boolean constants. The purpose of build options is to remove code
* from the build to reduce the overall code size present in the ROM image. Unless
* otherwise specified, the default action is to include all options. If a build option is
* not specifically listed as disabled, then it is included into the build.
*
* The documented build options are imported from a user controlled file for
* processing. The build options for all platform solutions are listed below:
*
* @anchor BLDOPT_REMOVE_UDIMMS_SUPPORT
* @li @e BLDOPT_REMOVE_UDIMMS_SUPPORT @n
* If unbuffered DIMMs are NOT expected to be required in the system, the code that
* handles unbuffered DIMMs can be removed from the build.
*
* @anchor BLDOPT_REMOVE_RDIMMS_SUPPORT
* @li @e BLDOPT_REMOVE_RDIMMS_SUPPORT @n
* If registered DIMMs are NOT expected to be required in the system, the code
* that handles registered DIMMs can be removed from the build.
*
* @anchor BLDOPT_REMOVE_LRDIMMS_SUPPORT
* @li @e BLDOPT_REMOVE_LRDIMMS_SUPPORT @n
* If Load Reduced DIMMs are NOT expected to be required in the system, the code
* that handles Load Reduced DIMMs can be removed from the build.
*
* @note The above three options operate independently from each other; however, at
* least one of the unbuffered , registered or load reduced DIMM options must be present in the build.
*
* @anchor BLDOPT_REMOVE_ECC_SUPPORT
* @li @e BLDOPT_REMOVE_ECC_SUPPORT @n
* Use this option to remove the code for Error Checking & Correction.
*
* @anchor BLDOPT_REMOVE_BANK_INTERLEAVE
* @li @e BLDOPT_REMOVE_BANK_INTERLEAVE @n
* Interleaving is a mechanism to do performance fine tuning. This option
* interleaves memory between banks on a DIMM.
*
* @anchor BLDOPT_REMOVE_DCT_INTERLEAVE
* @li @e BLDOPT_REMOVE_DCT_INTERLEAVE @n
* Interleaving is a mechanism to do performance fine tuning. This option
* interleaves memory from two DRAM controllers.
*
* @anchor BLDOPT_REMOVE_NODE_INTERLEAVE
* @li @e BLDOPT_REMOVE_NODE_INTERLEAVE @n
* Interleaving is a mechanism to do performance fine tuning. This option
* interleaves memory from two HyperTransport nodes.
*
* @anchor BLDOPT_REMOVE_PARALLEL_TRAINING
* @li @e BLDOPT_REMOVE_PARALLEL_TRAINING @n
* For multi-socket systems, training memory in parallel can reduce the time
* needed to boot.
*
* @anchor BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT
* @li @e BLDOPT_REMOVE_ONLINE_SPARE_SUPPORT @n
* Online Spare support is removed by this option.
*
* @anchor BLDOPT_REMOVE_MULTISOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_MULTISOCKET_SUPPORT @n
* Many systems use only a single socket and may benefit in code space to remove
* this code. However, certain processors have multiple HyperTransport nodes
* within a single socket. For these processors, the multi-node support is
* required and this option has no effect.
*
* @anchor BLDOPT_REMOVE_ACPI_PSTATES
* @li @e BLDOPT_REMOVE_ACPI_PSTATES @n
* This option removes the code that generates the ACPI tables used in power
* management.
*
* @anchor BLDOPT_REMOVE_SRAT
* @li @e BLDOPT_REMOVE_SRAT @n
* This option removes the code that generates the SRAT tables used in performance
* tuning.
*
* @anchor BLDOPT_REMOVE_SLIT
* @li @e BLDOPT_REMOVE_SLIT @n
* This option removes the code that generates the SLIT tables used in performance
* tuning.
*
* @anchor BLDOPT_REMOVE_WHEA
* @li @e BLDOPT_REMOVE_WHEA @n
* This option removes the code that generates the WHEA tables used in error
* handling and reporting.
*
* @anchor BLDOPT_REMOVE_DMI
* @li @e BLDOPT_REMOVE_DMI @n
* This option removes the code that generates the DMI tables used in system
* management.
*
* @anchor BLDOPT_REMOVE_DQS_TRAINING
* @li @e BLDOPT_REMOVE_DQS_TRAINING @n
* This option removes the code used in memory performance tuning.
*
* @anchor BLDOPT_REMOVE_EARLY_SAMPLES
* @li @e BLDOPT_REMOVE_EARLY_SAMPLES @n
* Special support for Early Samples is included. Default setting is FALSE.
*
* @anchor BLDOPT_REMOVE_HT_ASSIST
* @li @e BLDOPT_REMOVE_HT_ASSIST @n
* This option removes the code which implements the HT Assist feature.
*
* @anchor BLDOPT_REMOVE_ATM_MODE
* @li @e BLDOPT_REMOVE_ATM_MODE @n
* This option removes the code which implements the ATM feature.
*
* @anchor BLDOPT_REMOVE_MSG_BASED_C1E
* @li @e BLDOPT_REMOVE_MSG_BASED_C1E @n
* This option removes the code which implements the Message Based C1e feature.
*
* @anchor BLDOPT_REMOVE_C6_STATE
* @li @e BLDOPT_REMOVE_C6_STATE @n
* This option removes the code which implements the C6 C-state feature.
*
* @anchor BLDOPT_REMOVE_MEM_RESTORE_SUPPORT
* @li @e BLDOPT_REMOVE_MEM_RESTORE_SUPPORT @n
* This option removes the memory context restore feature.
*
* @anchor BLDOPT_REMOVE_FAMILY_10_SUPPORT
* @li @e BLDOPT_REMOVE_FAMILY_10_SUPPORT @n
* If the package contains support for family 10h processors, remove that support.
*
* @anchor BLDOPT_REMOVE_FAMILY_12_SUPPORT
* @li @e BLDOPT_REMOVE_FAMILY_12_SUPPORT @n
* If the package contains support for family 10h processors, remove that support.
*
* @anchor BLDOPT_REMOVE_FAMILY_14_SUPPORT
* @li @e BLDOPT_REMOVE_FAMILY_14_SUPPORT @n
* If the package contains support for family 14h processors, remove that support.
*
* @anchor BLDOPT_REMOVE_FAMILY_15_SUPPORT
* @li @e BLDOPT_REMOVE_FAMILY_15_SUPPORT @n
* If the package contains support for family 15h processors, remove that support.
*
* @anchor BLDOPT_REMOVE_AM3_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_AM3_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for AM3 sockets.
*
* @anchor BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_ASB2_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for ASB2 sockets.
*
* @anchor BLDOPT_REMOVE_C32_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_C32_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for C32 sockets.
*
* @anchor BLDOPT_REMOVE_FM1_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_FM1_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for FM1 sockets.
*
* @anchor BLDOPT_REMOVE_FP1_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_FP1_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for FP1 sockets.
*
* @anchor BLDOPT_REMOVE_FS1_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_FS1_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for FS1 sockets.
*
* @anchor BLDOPT_REMOVE_FT1_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_FT1_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for FT1 sockets.
*
* @anchor BLDOPT_REMOVE_G34_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_G34_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for G34 sockets.
*
* @anchor BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_S1G3_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for S1G3 sockets.
*
* @anchor BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT
* @li @e BLDOPT_REMOVE_S1G4_SOCKET_SUPPORT @n
* This option removes the code which implements support for processors packaged for S1G4 sockets.
*/
/**
* @page examplecustomizations Customization Examples
*
* The Addendum \<plat\>Options.c file for each platform contains the minimum required
* customizations for that platform. That is, it contains settings which would be needed
* to boot a SimNow! bsd for that platform.
* However, each individual product based on that platform will have customizations necessary for
* that hardware. Since the actual customizations needed vary so much, they are not included in
* the \<plat\>Options.c. This section provides examples of useful customizations that you can use or
* modify to suit your needs.
*
* @par
*
* Source for the examples shown can be found at Addendum\\Examples. @n
*
* - @ref DeemphasisExamples "Deemphasis List Examples"
* - @ref FrequencyLimitExamples "Frequency Limit Examples"
* - @ref PerfPerWattHt "A performance-per-watt optimization Example"
*
* @anchor DeemphasisExamples
* @par Deemphasis List Examples
*
* These examples customize PLATFORM_CONFIGURATION.PlatformDeemphasisList.
* Source for the deemphasis list examples can be found in DeemphasisExamples.c. @n
* @dontinclude DeemphasisExamples.c
* <ul>
* <li>
* The following deemphasis list provides an example for a 2P MCM Max Performance configuration.
* High Speed HT frequencies are supported. There is only one non-coherent chain. Note the technique of
* putting specified link matches before all uses of match any. It often works well to specify the non-coherent links
* and use match any for the coherent links.
* @skip DinarDeemphasisList
* @until {
* The non-coherent chain can run up to 2600 MHz. The chain is located on Socket 0, package Link 2.
* @until {
* @line }
* @line {
* @line }
* The coherent links can run up to 3200 MHz.
* @until HT_FREQUENCY_MAX
* @line }
* end of list:
* @until }
* Make this list the build time customized deemphasis list.
* @line define
*
* </li><li>
*
* The following deemphasis list provides an example for a 4P MCM Max Performance configuration.
* This system has a backplane with connectors for CPU cards and an IO board. So trace lengths are long.
* There can be one to four IO Chains, depending on the IO board.
* @skipline DoubloonDeemphasisList
* @until DoubloonDeemphasisList
*
* </li><li>
*
* The following deemphasis list further illustrates complex coherent system deemphasis. This is the same
* Dinar system as in an earlier example, but this time all the coherent links are explicitly customized (as
* might be needed if each link has unique characterization). For this example, we skip the non-coherent chains.
* (A real system would have to include them, see example above.)
* @skip DinarPerLinkDeemphasisList
* @until {
* Provide deemphasis settings for the 16 bit, ganged, links, Socket 0 links 0, 1 and Socket 1 links 1 and 2.
* Provide entries to customize all HT3 frequencies at which the links may run. This example covers all HT3 speeds.
* @until {
* @until DcvLevelMinus6
* @until DcvLevelMinus6
* @until DcvLevelMinus6
* @until DcvLevelMinus6
* Link 3 on both sockets connects different internal die: sublink 0 connects the internal node zeroes, and
* sublink 1 connects the internal node ones. So the link is unganged and both sublinks must be specifically
* customized.
* @until {
* @until DcvLevelMinus6
* @until DcvLevelMinus6
* @until DcvLevelMinus6
* @until DcvLevelMinus6
* end of list:
* @until define
*
* </ul>
*
* @anchor FrequencyLimitExamples
* @par Frequency Limit Examples
*
* These examples customize AMD_HT_INTERFACE.CpuToCpuPcbLimitsList and AMD_HT_INTERFACE.IoPcbLimitsList.
* Source for the frequency limit examples can be found in FrequencyLimitExamples.c. @n
* @dontinclude FrequencyLimitExamples.c
* <ul>
* <li>
* The following list provides an example for limiting all coherent links to non-extended frequencies,
* that is, to 2600 MHz or less.
* @skipline NonExtendedCpuToCpuLimitList
* @until {
* Provide the limit customization. Match links from any socket, any package link, to any socket, any package link. Width is not limited.
* @until HT_FREQUENCY_LIMIT_2600M
* End of list:
* @until ;
* Customize the build to use this cpu to cpu frequency limit.
* @until NonExtendedCpuToCpuLimitList
* @n </li>
* <li>
* The following list provides an example for limiting all coherent links to HT 1 frequencies,
* that is, to 1000 MHz or less. This is sometimes useful for test and debug.
* @skipline Ht1CpuToCpuLimitList
* @until Ht1CpuToCpuLimitList
* @n </li>
* <li>
* The following list provides an example for limiting all non-coherent links to 2400 MHz or less.
* The chain is matched by host processor Socket and package Link. The depth can be used to select a particular device
* to device link on the chain. In this example, the chain consists of a single cave device and depth can be set to match any.
* @skipline No2600MhzIoLimitList
* @until No2600MhzIoLimitList
* @n </li>
* <li>
* The following list provides an example for limiting all non-coherent links to the minimum HT 3 frequency,
* that is, to 1200 MHz or less. This can be useful for test and debug.
* @skipline MinHt3IoLimitList
* @until MinHt3IoLimitList
* @n </li>
*
* </ul>
*
* @anchor PerfPerWattHt
* @par Performance-per-Watt Optimization Example
*
* This example customizes AMD_HT_INTERFACE.SkipRegangList.
* Source for the Performance-per-watt Optimization example can be found in PerfPerWatt.c. @n
* @dontinclude PerfPerWatt.c
* To implement a performance-per-watt optimization for MCM processors, use the skip regang structure shown. @n
* @skipline PerfPerWatt
* @until PerfPerWatt
*
*/

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/* $NoKeywords:$ */
/**
* @file
*
* AMD Platform Specific Memory Configuration
*
* Contains Definitions and Macros for control of AGESA Memory code on a per platform basis
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: OPTION
* @e \$Revision: 47408 $ @e \$Date: 2011-02-19 00:56:31 +0800 (Sat, 19 Feb 2011) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _PLATFORM_MEMORY_CONFIGURATION_H_
#define _PLATFORM_MEMORY_CONFIGURATION_H_
/*----------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*----------------------------------------------------------------------------------------
*/
#ifndef PSO_ENTRY
#define PSO_ENTRY UINT8
#endif
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* PLATFORM SPECIFIC MEMORY DEFINITIONS
*----------------------------------------------------------------------------------------
*/
///
/// Memory Speed and DIMM Population Masks
///
///< DDR Speed Masks
///< Specifies the DDR Speed on a memory channel
///
#define ANY_SPEED 0xFFFFFFFF
#define DDR400 ((UINT32) 1 << (DDR400_FREQUENCY / 66))
#define DDR533 ((UINT32) 1 << (DDR533_FREQUENCY / 66))
#define DDR667 ((UINT32) 1 << (DDR667_FREQUENCY / 66))
#define DDR800 ((UINT32) 1 << (DDR800_FREQUENCY / 66))
#define DDR1066 ((UINT32) 1 << (DDR1066_FREQUENCY / 66))
#define DDR1333 ((UINT32) 1 << (DDR1333_FREQUENCY / 66))
#define DDR1600 ((UINT32) 1 << (DDR1600_FREQUENCY / 66))
#define DDR1866 ((UINT32) 1 << (DDR1866_FREQUENCY / 66))
#define DDR2133 ((UINT32) 1 << (DDR2133_FREQUENCY / 66))
#define DDR2400 ((UINT32) 1 << (DDR2400_FREQUENCY / 66))
///
///< DIMM POPULATION MASKS
///< Specifies the DIMM Population on a channel (can be added together to specify configuration).
///< ex. SR_DIMM0 + SR_DIMM1 : Single Rank Dimm in slot 0 AND Slot 1
///< SR_DIMM0 + DR_DIMM0 + SR_DIMM1 +DR_DIMM1 : Single OR Dual rank in Slot 0 AND Single OR Dual rank in Slot 1
///
#define ANY_ 0xFF ///< Any dimm configuration the current channel
#define SR_DIMM0 0x0001 ///< Single rank dimm in slot 0 on the current channel
#define SR_DIMM1 0x0010 ///< Single rank dimm in slot 1 on the current channel
#define SR_DIMM2 0x0100 ///< Single rank dimm in slot 2 on the current channel
#define SR_DIMM3 0x1000 ///< Single rank dimm in slot 3 on the current channel
#define DR_DIMM0 0x0002 ///< Dual rank dimm in slot 0 on the current channel
#define DR_DIMM1 0x0020 ///< Dual rank dimm in slot 1 on the current channel
#define DR_DIMM2 0x0200 ///< Dual rank dimm in slot 2 on the current channel
#define DR_DIMM3 0x2000 ///< Dual rank dimm in slot 3 on the current channel
#define QR_DIMM0 0x0004 ///< Quad rank dimm in slot 0 on the current channel
#define QR_DIMM1 0x0040 ///< Quad rank dimm in slot 1 on the current channel
#define QR_DIMM2 0x0400 ///< Quad rank dimm in slot 2 on the current channel
#define QR_DIMM3 0x4000 ///< Quad rank dimm in slot 3 on the current channel
#define ANY_DIMM0 0x000F ///< Any Dimm combination in slot 0 on the current channel
#define ANY_DIMM1 0x00F0 ///< Any Dimm combination in slot 1 on the current channel
#define ANY_DIMM2 0x0F00 ///< Any Dimm combination in slot 2 on the current channel
#define ANY_DIMM3 0xF000 ///< Any Dimm combination in slot 3 on the current channel
///
///< Number of Dimms on the current channel
///< This is a mask used to indicate the number of dimms in a channel
///< They can be added to indicate multiple conditions (i.e 1 OR 2 Dimms)
///
#define ANY_NUM 0xFF ///< Any number of Dimms
#define NO_DIMM 0x00 ///< No Dimms present
#define ONE_DIMM 0x01 ///< One dimm Poulated on the current channel
#define TWO_DIMM 0x02 ///< Two dimms Poulated on the current channel
#define THREE_DIMM 0x04 ///< Three dimms Poulated on the current channel
#define FOUR_DIMM 0x08 ///< Four dimms Poulated on the current channel
/*----------------------------------------------------------------------------------------
*
* Platform Specific Override Definitions for Socket, Channel and Dimm
* This indicates where a platform override will be applied.
*
*----------------------------------------------------------------------------------------
*/
///
///< SOCKET MASKS
///< Indicates associated processor sockets to apply override settings
///
#define ANY_SOCKET 0xFF ///< Apply to all sockets
#define SOCKET0 0x01 ///< Apply to socket 0
#define SOCKET1 0x02 ///< Apply to socket 1
#define SOCKET2 0x04 ///< Apply to socket 2
#define SOCKET3 0x08 ///< Apply to socket 3
#define SOCKET4 0x10 ///< Apply to socket 4
#define SOCKET5 0x20 ///< Apply to socket 5
#define SOCKET6 0x40 ///< Apply to socket 6
#define SOCKET7 0x80 ///< Apply to socket 7
///
///< CHANNEL MASKS
///< Indicates Memory channels where override should be applied
///
#define ANY_CHANNEL 0xFF ///< Apply to all Memory channels
#define CHANNEL_A 0x01 ///< Apply to Channel A
#define CHANNEL_B 0x02 ///< Apply to Channel B
#define CHANNEL_C 0x04 ///< Apply to Channel C
#define CHANNEL_D 0x08 ///< Apply to Channel D
///
/// DIMM MASKS
/// Indicates Dimm Slots where override should be applied
///
#define ALL_DIMMS 0xFF ///< Apply to all dimm slots
#define DIMM0 0x01 ///< Apply to Dimm Slot 0
#define DIMM1 0x02 ///< Apply to Dimm Slot 1
#define DIMM2 0x04 ///< Apply to Dimm Slot 2
#define DIMM3 0x08 ///< Apply to Dimm Slot 3
///
/// REGISTER ACCESS MASKS
/// Not supported as an at this time
///
#define ACCESS_NB0 0x0
#define ACCESS_NB1 0x1
#define ACCESS_NB2 0x2
#define ACCESS_NB3 0x3
#define ACCESS_NB4 0x4
#define ACCESS_PHY 0x5
#define ACCESS_DCT_XT 0x6
/*----------------------------------------------------------------------------------------
*
* Platform Specific Overriding Table Definitions
*
*----------------------------------------------------------------------------------------
*/
#define PSO_END 0 ///< Table End
#define PSO_CKE_TRI 1 ///< CKE Tristate Map
#define PSO_ODT_TRI 2 ///< ODT Tristate Map
#define PSO_CS_TRI 3 ///< CS Tristate Map
#define PSO_MAX_DIMMS 4 ///< Max Dimms per channel
#define PSO_CLK_SPEED 5 ///< Clock Speed
#define PSO_DIMM_TYPE 6 ///< Dimm Type
#define PSO_MEMCLK_DIS 7 ///< MEMCLK Disable Map
#define PSO_MAX_CHNLS 8 ///< Max Channels per Socket
#define PSO_BUS_SPEED 9 ///< Max Memory Bus Speed
#define PSO_MAX_CHIPSELS 10 ///< Max Chipsel per Channel
#define PSO_MEM_TECH 11 ///< Channel Memory Type
#define PSO_WL_SEED 12 ///< DDR3 Write Levelization Seed delay
#define PSO_RXEN_SEED 13 ///< Hardwared based RxEn seed
#define PSO_NO_LRDIMM_CS67_ROUTING 14 ///< CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs
#define PSO_SOLDERED_DOWN_SODIMM_TYPE 15 ///< Soldered down SODIMM type
#define PSO_LVDIMM_VOLT1_5_SUPPORT 16 ///< Force LvDimm voltage to 1.5V
/*----------------------------------
* CONDITIONAL PSO SPECIFIC ENTRIES
*---------------------------------*/
// Condition Types
#define CONDITIONAL_PSO_MIN 100 ///< Start of Conditional Entry Types
#define PSO_CONDITION_AND 100 ///< And Block - Start of Conditional block
#define PSO_CONDITION_LOC 101 ///< Location - Specify Socket, Channel, Dimms to be affected
#define PSO_CONDITION_SPD 102 ///< SPD - Specify a specific SPD value on a Dimm on the channel
#define PSO_CONDITION_REG 103 // Reserved
#define PSO_CONDITION_MAX 103 ///< End Of Condition Entry Types
// Action Types
#define PSO_ACTION_MIN 120 ///< Start of Action Entry Types
#define PSO_ACTION_ODT 120 ///< ODT values to override
#define PSO_ACTION_ADDRTMG 121 ///< Address/Timing values to override
#define PSO_ACTION_ODCCONTROL 122 ///< ODC Control values to override
#define PSO_ACTION_SLEWRATE 123 ///< Slew Rate value to override
#define PSO_ACTION_REG 124 // Reserved
#define PSO_ACTION_SPEEDLIMIT 125 ///< Memory Bus speed Limit based on configuration
#define PSO_ACTION_MAX 125 ///< End of Action Entry Types
#define CONDITIONAL_PSO_MAX 139 ///< End of Conditional Entry Types
/*----------------------------------------------------------------------------------------
* CONDITIONAL OVERRIDE TABLE MACROS
*----------------------------------------------------------------------------------------
*/
#define MEMCLK_DIS_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \
PSO_MEMCLK_DIS, 10, SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map
#define CKE_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map) \
PSO_CKE_TRI, 4, SocketID, ChannelID, Bit0Map, Bit1Map
#define ODT_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map) \
PSO_ODT_TRI, 6, SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map
#define CS_TRI_MAP(SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map) \
PSO_CS_TRI, 10, SocketID, ChannelID, Bit0Map, Bit1Map, Bit2Map, Bit3Map, Bit4Map, Bit5Map, Bit6Map, Bit7Map
#define NUMBER_OF_DIMMS_SUPPORTED(SocketID, ChannelID, NumberOfDimmSlotsPerChannel) \
PSO_MAX_DIMMS, 3, SocketID, ChannelID, NumberOfDimmSlotsPerChannel
#define NUMBER_OF_CHIP_SELECTS_SUPPORTED(SocketID, ChannelID, NumberOfChipSelectsPerChannel) \
PSO_MAX_CHIPSELS, 3, SocketID, ChannelID, NumberOfChipSelectsPerChannel
#define NUMBER_OF_CHANNELS_SUPPORTED(SocketID, NumberOfChannelsPerSocket) \
PSO_MAX_CHNLS, 3, SocketID, ANY_CHANNEL, NumberOfChannelsPerSocket
#define OVERRIDE_DDR_BUS_SPEED(SocketID, ChannelID, TimingMode, BusSpeed) \
PSO_BUS_SPEED, 10, SocketID, ChannelID, TimingMode, (TimingMode >> 8), (TimingMode >> 16), (TimingMode >> 24), \
BusSpeed, (BusSpeed >> 8), (BusSpeed >> 16), (BusSpeed >> 24)
#define DRAM_TECHNOLOGY(SocketID, MemTechType) \
PSO_MEM_TECH, 6, SocketID, ANY_CHANNEL, MemTechType, (MemTechType >> 8), (MemTechType >> 16), (MemTechType >> 24)
#define WRITE_LEVELING_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
Byte6Seed, Byte7Seed, ByteEccSeed) \
PSO_WL_SEED, 11, SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
Byte6Seed, Byte7Seed, ByteEccSeed
#define HW_RXEN_SEED(SocketID, ChannelID, Byte0Seed, Byte1Seed, Byte2Seed, Byte3Seed, Byte4Seed, Byte5Seed, \
Byte6Seed, Byte7Seed, ByteEccSeed) \
PSO_RXEN_SEED, 20, SocketID, ChannelID, Byte0Seed, (Byte0Seed >> 8), Byte1Seed, (Byte1Seed >> 8), Byte2Seed, (Byte2Seed >> 8), \
Byte3Seed, (Byte3Seed >> 8), Byte4Seed, (Byte4Seed >> 8), Byte5Seed, (Byte5Seed >> 8), Byte6Seed, (Byte6Seed >> 8), \
Byte7Seed, (Byte7Seed >> 8), ByteEccSeed, (ByteEccSeed >> 8)
#define NO_LRDIMM_CS67_ROUTING(SocketID, ChannelID) \
PSO_NO_LRDIMM_CS67_ROUTING, 3, SocketID, ChannelID, TRUE
#define SOLDERED_DOWN_SODIMM_TYPE(SocketID, ChannelID) \
PSO_SOLDERED_DOWN_SODIMM_TYPE, 3, SocketID, ChannelID, TRUE
#define LVDIMM_FORCE_VOLT1_5_FOR_D0 \
PSO_LVDIMM_VOLT1_5_SUPPORT, 3, ANY_SOCKET, ANY_CHANNEL, TRUE
/*----------------------------------------------------------------------------------------
* CONDITIONAL OVERRIDE TABLE MACROS
*----------------------------------------------------------------------------------------
*/
#define CONDITION_AND \
PSO_CONDITION_AND, 0
#define COND_LOC(SocketMsk, ChannelMsk, DimmMsk) \
PSO_CONDITION_LOC, 3, SocketMsk, ChannelMsk, DimmMsk
#define COND_SPD(Byte, Mask, Value) \
PSO_CONDITION_SPD, 3, Byte, Mask, Value
#define COND_REG(Access, Offset, Mask, Value) \
PSO_CONDITION_REG, 11, Access, (Offset & 0x0FF), (Offset >> 8), \
((Mask) & 0x0FF), (((Mask) >> 8) & 0x0FF), (((Mask) >> 16) & 0x0FF), (((Mask) >> 24) & 0x0FF), \
((Value) & 0x0FF), (((Value) >> 8) & 0x0FF), (((Value) >> 16) & 0x0FF), (((Value) >> 24) & 0x0FF)
#define ACTION_ODT(Frequency, Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt) \
PSO_ACTION_ODT, 9, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), ((Frequency >> 24)& 0x0FF), \
Dimms, QrDimms, DramOdt, QrDramOdt, DramDynOdt
#define ACTION_ADDRTMG(Frequency, DimmConfig, AddrTmg) \
PSO_ACTION_ADDRTMG, 10, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
(AddrTmg & 0x0FF), ((AddrTmg >> 8)& 0x0FF), ((AddrTmg >> 16)& 0x0FF), ((AddrTmg >> 24)& 0x0FF)
#define ACTION_ODCCTRL(Frequency, DimmConfig, OdcCtrl) \
PSO_ACTION_ODCCONTROL, 10, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
(OdcCtrl & 0x0FF), ((OdcCtrl >> 8)& 0x0FF), ((OdcCtrl >> 16)& 0x0FF), ((OdcCtrl >> 24)& 0x0FF)
#define ACTION_SLEWRATE(Frequency, DimmConfig, SlewRate) \
PSO_ACTION_SLEWRATE, 10, \
((Frequency) & 0x0FF), (((Frequency) >> 8)& 0x0FF), (((Frequency) >> 16)& 0x0FF), (((Frequency) >> 24)& 0x0FF), \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), \
(SlewRate & 0x0FF), ((SlewRate >> 8)& 0x0FF), ((SlewRate >> 16)& 0x0FF), ((SlewRate >> 24)& 0x0FF)
#define ACTION_SPEEDLIMIT(DimmConfig, Dimms, SpeedLimit15, SpeedLimit135, SpeedLimit125) \
PSO_ACTION_SPEEDLIMIT, 9, \
((DimmConfig) & 0x0FF), (((DimmConfig) >> 8) & 0x0FF), Dimms, \
(SpeedLimit15 & 0x0FF), ((SpeedLimit15 >> 8)& 0x0FF), \
(SpeedLimit135 & 0x0FF), ((SpeedLimit135 >> 8)& 0x0FF), \
(SpeedLimit125 & 0x0FF), ((SpeedLimit125 >> 8)& 0x0FF)
/*----------------------------------------------------------------------------------------
* END OF CONDITIONAL OVERRIDE TABLE MACROS
*----------------------------------------------------------------------------------------
*/
#endif // _PLATFORM_MEMORY_CONFIGURATION_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build options for a Sabine platform solution
*
* This file generates the defaults tables for the "Sabine" platform solution
* set of processors. The documented build options are imported from a user
* controlled file for processing.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 52040 $ @e \$Date: 2011-04-30 05:56:20 +0800 (Sat, 30 Apr 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#include "cpuRegisters.h"
#include "cpuFamRegisters.h"
#include "cpuFamilyTranslation.h"
#include "AdvancedApi.h"
#include "heapManager.h"
#include "CreateStruct.h"
#include "cpuFeatures.h"
#include "Table.h"
#include "CommonReturns.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "GnbInterface.h"
/*****************************************************************************
* Define the RELEASE VERSION string
*
* The Release Version string should identify the next planned release.
* When a branch is made in preparation for a release, the release manager
* should change/confirm that the branch version of this file contains the
* string matching the desired version for the release. The trunk version of
* the file should always contain a trailing 'X'. This will make sure that a
* development build from trunk will not be confused for a released version.
* The release manager will need to remove the trailing 'X' and update the
* version string as appropriate for the release. The trunk copy of this file
* should also be updated/incremented for the next expected version, + trailing 'X'
****************************************************************************/
// This is the delivery package title, "LlanoPI "
// This string MUST be exactly 8 characters long
#define AGESA_PACKAGE_STRING {'L', 'l', 'a', 'n', 'o', 'P', 'I', ' '}
// This is the release version number of the AGESA component
// This string MUST be exactly 12 characters long
#define AGESA_VERSION_STRING {'V', '1', '.', '1', '.', '0', '.', '0', ' ', ' ', ' ', ' '}
// The Sabine solution is defined to be family 0x12 in the FS1 and FP1 sockets.
#define INSTALL_FS1_SOCKET_SUPPORT TRUE
#define INSTALL_FP1_SOCKET_SUPPORT TRUE
#define INSTALL_FAMILY_12_SUPPORT TRUE
#ifdef BLDOPT_REMOVE_FS1_SOCKET_SUPPORT
#if BLDOPT_REMOVE_FS1_SOCKET_SUPPORT == TRUE
#undef INSTALL_FS1_SOCKET_SUPPORT
#define INSTALL_FS1_SOCKET_SUPPORT FALSE
#endif
#endif
#ifdef BLDOPT_REMOVE_FP1_SOCKET_SUPPORT
#if BLDOPT_REMOVE_FP1_SOCKET_SUPPORT == TRUE
#undef INSTALL_FP1_SOCKET_SUPPORT
#define INSTALL_FP1_SOCKET_SUPPORT FALSE
#endif
#endif
// The following definitions specify the default values for various parameters in which there are
// no clearly defined defaults to be used in the common file. The values below are based on product
// and BKDG content, please consult the AGESA Memory team for consultation.
#define DFLT_SCRUB_DRAM_RATE (0)
#define DFLT_SCRUB_L2_RATE (0)
#define DFLT_SCRUB_L3_RATE (0)
#define DFLT_SCRUB_IC_RATE (0)
#define DFLT_SCRUB_DC_RATE (0)
#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
#define DFLT_VRM_SLEW_RATE (5000)
// Instantiate all solution relevant data.
#include "PlatformInstall.h"

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build options for a SanMarino platform solution
*
* This file generates the defaults tables for the "San Marino" platform solution
* set of processors. The documented build options are imported from a user
* controlled file for processing.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 48494 $ @e \$Date: 2011-03-10 02:53:08 +0800 (Thu, 10 Mar 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "cpuFamRegisters.h"
#include "cpuFamilyTranslation.h"
#include "AdvancedApi.h"
#include "heapManager.h"
#include "CreateStruct.h"
#include "cpuFeatures.h"
#include "Table.h"
#include "CommonReturns.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "GnbInterfaceStub.h"
/*****************************************************************************
* Define the RELEASE VERSION string
*
* The Release Version string should identify the next planned release.
* When a branch is made in preparation for a release, the release manager
* should change/confirm that the branch version of this file contains the
* string matching the desired version for the release. The trunk version of
* the file should always contain a trailing 'X'. This will make sure that a
* development build from trunk will not be confused for a released version.
* The release manager will need to remove the trailing 'X' and update the
* version string as appropriate for the release. The trunk copy of this file
* should also be updated/incremented for the next expected version, + trailing 'X'
****************************************************************************/
// This is the delivery package title, "OrochiPI"
// This string MUST be exactly 8 characters long
#define AGESA_PACKAGE_STRING {'O', 'r', 'o', 'c', 'h', 'i', 'P', 'I'}
// This is the release version number of the AGESA component
// This string MUST be exactly 12 characters long
#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '7', '.', '5', 'X', ' ', ' ', ' '}
// The San Marino solution is defined to be families 0x10 and 0x15 in the C32 socket.
#define INSTALL_C32_SOCKET_SUPPORT TRUE
#define INSTALL_FAMILY_10_SUPPORT TRUE
#define INSTALL_FAMILY_15_SUPPORT TRUE
#ifdef BLDOPT_REMOVE_FAMILY_10_SUPPORT
#if BLDOPT_REMOVE_FAMILY_10_SUPPORT == TRUE
#undef INSTALL_FAMILY_10_SUPPORT
#define INSTALL_FAMILY_10_SUPPORT FALSE
#endif
#endif
#ifdef BLDOPT_REMOVE_FAMILY_15_SUPPORT
#if BLDOPT_REMOVE_FAMILY_15_SUPPORT == TRUE
#undef INSTALL_FAMILY_15_SUPPORT
#define INSTALL_FAMILY_15_SUPPORT FALSE
#endif
#endif
// The following definitions specify the default values for various parameters in which there are
// no clearly defined defaults to be used in the common file. The values below are based on product
// and BKDG content, please consult the AGESA Memory team for consultation.
#define DFLT_SCRUB_DRAM_RATE (0xFF)
#define DFLT_SCRUB_L2_RATE (0x10)
#define DFLT_SCRUB_L3_RATE (0x10)
#define DFLT_SCRUB_IC_RATE (0)
#define DFLT_SCRUB_DC_RATE (0x12)
#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
#define DFLT_VRM_SLEW_RATE (2500)
// Instantiate all solution relevant data.
#include "PlatformInstall.h"

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build options for a Scorpius platform solution
*
* This file generates the defaults tables for the "Scorpius" platform solution
* set of processors. The documented build options are imported from a user
* controlled file for processing.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 48494 $ @e \$Date: 2011-03-10 02:53:08 +0800 (Thu, 10 Mar 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#include "cpuRegisters.h"
#include "cpuFamRegisters.h"
#include "cpuFamilyTranslation.h"
#include "AdvancedApi.h"
#include "heapManager.h"
#include "CreateStruct.h"
#include "cpuFeatures.h"
#include "Table.h"
#include "CommonReturns.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "GnbInterfaceStub.h"
/*****************************************************************************
* Define the RELEASE VERSION string
*
* The Release Version string should identify the next planned release.
* When a branch is made in preparation for a release, the release manager
* should change/confirm that the branch version of this file contains the
* string matching the desired version for the release. The trunk version of
* the file should always contain a trailing 'X'. This will make sure that a
* development build from trunk will not be confused for a released version.
* The release manager will need to remove the trailing 'X' and update the
* version string as appropriate for the release. The trunk copy of this file
* should also be updated/incremented for the next expected version, + trailing 'X'
****************************************************************************/
// This is the delivery package title, "OrochiPI"
// This string MUST be exactly 8 characters long
#define AGESA_PACKAGE_STRING {'O', 'r', 'o', 'c', 'h', 'i', 'P', 'I'}
// This is the release version number of the AGESA component
// This string MUST be exactly 12 characters long
#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '7', '.', '5', 'X', ' ', ' ', ' '}
// The Scorpius solution is defined to be families 0x10 and 0x15 in the AM3 socket.
#define INSTALL_AM3_SOCKET_SUPPORT TRUE
#define INSTALL_FAMILY_10_SUPPORT TRUE
#define INSTALL_FAMILY_15_SUPPORT TRUE
#ifdef BLDOPT_REMOVE_FAMILY_10_SUPPORT
#if BLDOPT_REMOVE_FAMILY_10_SUPPORT == TRUE
#undef INSTALL_FAMILY_10_SUPPORT
#define INSTALL_FAMILY_10_SUPPORT FALSE
#endif
#endif
#ifdef BLDOPT_REMOVE_FAMILY_15_SUPPORT
#if BLDOPT_REMOVE_FAMILY_15_SUPPORT == TRUE
#undef INSTALL_FAMILY_15_SUPPORT
#define INSTALL_FAMILY_15_SUPPORT FALSE
#endif
#endif
// The following definitions specify the default values for various parameters in which there are
// no clearly defined defaults to be used in the common file. The values below are based on product
// and BKDG content, please consult the AGESA Memory team for consultation.
#define DFLT_SCRUB_DRAM_RATE (0xFF)
#define DFLT_SCRUB_L2_RATE (0x10)
#define DFLT_SCRUB_L3_RATE (0x10)
#define DFLT_SCRUB_IC_RATE (0)
#define DFLT_SCRUB_DC_RATE (0x12)
#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
#define DFLT_VRM_SLEW_RATE (2500)
// Instantiate all solution relevant data.
#include "PlatformInstall.h"

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build options for a Tigris platform solution
*
* This file generates the defaults tables for the "Tigris" platform solution
* set of processors. The documented build options are imported from a user
* controlled file for processing.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#include "cpuRegisters.h"
#include "cpuFamRegisters.h"
#include "cpuFamilyTranslation.h"
#include "AdvancedApi.h"
#include "heapManager.h"
#include "CreateStruct.h"
#include "cpuFeatures.h"
#include "Table.h"
#include "CommonReturns.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "GnbInterfaceStub.h"
/*****************************************************************************
* Define the RELEASE VERSION string
*
* The Release Version string should identify the next planned release.
* When a branch is made in preparation for a release, the release manager
* should change/confirm that the branch version of this file contains the
* string matching the desired version for the release. The trunk version of
* the file should always contain a trailing 'X'. This will make sure that a
* development build from trunk will not be confused for a released version.
* The release manager will need to remove the trailing 'X' and update the
* version string as appropriate for the release. The trunk copy of this file
* should also be updated/incremented for the next expected version, + trailing 'X'
****************************************************************************/
// This is the delivery package title, "TigrisPI"
// This string MUST be exactly 8 characters long
#define AGESA_PACKAGE_STRING {'T', 'i', 'g', 'r', 'i', 's', 'P', 'I'}
// This is the release version number of the AGESA component
// This string MUST be exactly 12 characters long
#define AGESA_VERSION_STRING {'V', '0', '.', '1', '.', '2', '.', '3', 'X', ' ', ' ', ' '}
// The Tigris solution is defined to be family 0x10 in the S1g3 socket.
#define INSTALL_S1G3_SOCKET_SUPPORT TRUE
#define INSTALL_FAMILY_10_SUPPORT TRUE
// The following definitions specify the default values for various parameters in which there are
// no clearly defined defaults to be used in the common file. The values below are based on product
// and BKDG content, please consult the AGESA Memory team for consultation.
#define DFLT_SCRUB_DRAM_RATE (0)
#define DFLT_SCRUB_L2_RATE (0)
#define DFLT_SCRUB_L3_RATE (0)
#define DFLT_SCRUB_IC_RATE (0)
#define DFLT_SCRUB_DC_RATE (0)
#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_REGISTERED
#define DFLT_VRM_SLEW_RATE (5000)
// Instantiate all solution relevant data.
#include "PlatformInstall.h"

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/* $NoKeywords:$ */
/**
* @file
*
* Topology interface definitions.
*
* Contains AMD AGESA internal interface for topology related data which
* is consumed by code other than HyperTransport init (and produced by
* HyperTransport init.)
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#ifndef _TOPOLOGY_H_
#define _TOPOLOGY_H_
// Defines for limiting data structure maximum allocation and limit checking.
#define MAX_NODES 8
#define MAX_SOCKETS MAX_NODES
#define MAX_DIES 2
// Defines useful with package link
#define HT_LIST_MATCH_INTERNAL_LINK_0 0xFA
#define HT_LIST_MATCH_INTERNAL_LINK_1 0xFB
#define HT_LIST_MATCH_INTERNAL_LINK_2 0xFC
/**
* Hop Count Table.
* This is a heap data structure. The Hops array is filled as a size x size matrix.
* The unused space, if any, is all at the end.
*/
typedef struct {
UINT8 Size; ///< The row and column size of actual hop count data */
UINT8 Hops[MAX_NODES * MAX_NODES]; ///< Room for a dynamic two dimensional array of [size][size] */
} HOP_COUNT_TABLE;
/**
* Socket and Module to Node Map Item.
* Provide the Node Id and core id range for each module in each processor.
*/
typedef struct {
UINT8 Node; ///< The module's Node id.
UINT8 LowCore; ///< The lowest processor core id for this module.
UINT8 HighCore; ///< The highest processor core id for this module.
UINT8 EnabledComputeUnits; ///< The value of Enabled for this processor module.
UINT8 DualCoreComputeUnits; ///< The value of DualCore for this processor module.
} SOCKET_DIE_TO_NODE_ITEM;
/**
* Socket and Module to Node Map.
* This type is a pointer to the actual map, it can be used for a struct item or
* for typecasting a heap buffer pointer.
*/
typedef SOCKET_DIE_TO_NODE_ITEM (*SOCKET_DIE_TO_NODE_MAP)[MAX_SOCKETS][MAX_DIES];
/**
* Node id to Socket Die Map Item.
*/
typedef struct {
UINT8 Socket; ///< socket of the processor containing the Node.
UINT8 Die; ///< the module in the processor which is Node.
} NODE_TO_SOCKET_DIE_ITEM;
/**
* Node id to Socket Die Map.
*/
typedef NODE_TO_SOCKET_DIE_ITEM (*NODE_TO_SOCKET_DIE_MAP)[MAX_NODES];
/**
* Provide AP core with socket and node context at start up.
* This information is posted to the AP cores using a register as a mailbox.
*/
typedef struct {
UINT32 Node:4; ///< The node id of Core's node.
UINT32 Socket:4; ///< The socket of this Core's node.
UINT32 Module:2; ///< The internal module number for Core's node.
UINT32 ModuleType:2; ///< Single Module = 0, Multi-module = 1.
UINT32 :20; ///< Reserved
} AP_MAIL_INFO_FIELDS;
/**
* AP info fields can be written and read to a register.
*/
typedef union {
UINT32 Info; ///< Just a number for register access, or opaque passing.
AP_MAIL_INFO_FIELDS Fields; ///< access to the info fields.
} AP_MAIL_INFO;
/**
* Provide AP core with system degree and system core number at start up.
* This information is posted to the AP cores using a register as a mailbox.
*/
typedef struct {
UINT32 SystemDegree:3; ///< The number of connected links
UINT32 :3; ///< Reserved
UINT32 HeapIndex:6; ///< The zero-based system core number
UINT32 :20; ///< Reserved
} AP_MAIL_EXT_INFO_FIELDS;
/**
* AP info fields can be written and read to a register.
*/
typedef union {
UINT32 Info; ///< Just a number for register access, or opaque passing.
AP_MAIL_EXT_INFO_FIELDS Fields; ///< access to the info fields.
} AP_MAIL_EXT_INFO;
/**
* AP Info mailbox set.
*/
typedef struct {
AP_MAIL_INFO ApMailInfo; ///< The AP mail info
AP_MAIL_EXT_INFO ApMailExtInfo; ///< The extended AP mail info
} AP_MAILBOXES;
/**
* Provide a northbridge to package mapping for link assignments.
*
*/
typedef struct {
UINT8 Link; ///< The Node's link
UINT8 Module; ///< The internal module position of Node
UINT8 PackageLink; ///< The corresponding package link
} PACKAGE_HTLINK_MAP_ITEM;
/**
* A Processor's complete set of link assignments
*/
typedef PACKAGE_HTLINK_MAP_ITEM (*PACKAGE_HTLINK_MAP)[];
#endif // _TOPOLOGY_H_

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/* $NoKeywords:$ */
/**
* @file
*
* Install of build options for a Virgo platform solution
*
* This file generates the defaults tables for the "Virgo" platform solution
* set of processors. The documented build options are imported from a user
* controlled file for processing.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Core
* @e \$Revision: 49803 $ @e \$Date: 2011-03-29 15:20:04 +0800 (Tue, 29 Mar 2011) $
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
***************************************************************************/
#include "cpuRegisters.h"
#include "cpuFamRegisters.h"
#include "cpuFamilyTranslation.h"
#include "AdvancedApi.h"
#include "heapManager.h"
#include "CreateStruct.h"
#include "cpuFeatures.h"
#include "Table.h"
#include "CommonReturns.h"
#include "cpuEarlyInit.h"
#include "cpuLateInit.h"
#include "GnbInterface.h"
/*****************************************************************************
* Define the RELEASE VERSION string
*
* The Release Version string should identify the next planned release.
* When a branch is made in preparation for a release, the release manager
* should change/confirm that the branch version of this file contains the
* string matching the desired version for the release. The trunk version of
* the file should always contain a trailing 'X'. This will make sure that a
* development build from trunk will not be confused for a released version.
* The release manager will need to remove the trailing 'X' and update the
* version string as appropriate for the release. The trunk copy of this file
* should also be updated/incremented for the next expected version, + trailing 'X'
****************************************************************************/
// This is the delivery package title, "TrinyPI "
// This string MUST be exactly 8 characters long
#define AGESA_PACKAGE_STRING {'T', 'r', 'i', 'n', 'y', 'P', 'I', ' '}
// This is the release version number of the AGESA component
// This string MUST be exactly 12 characters long
#define AGESA_VERSION_STRING {'V', '0', '.', '0', '.', '6', '.', '0', 'X', ' ', ' ', ' '}
// The Virgo solution is defined to be family 0x15 in the FM2 socket.
#define INSTALL_FM2_SOCKET_SUPPORT TRUE
#define INSTALL_FAMILY_15_SUPPORT TRUE
// The following definitions specify the default values for various parameters in which there are
// no clearly defined defaults to be used in the common file. The values below are based on product
// and BKDG content, please consult the AGESA Memory team for consultation.
#define DFLT_SCRUB_DRAM_RATE (0)
#define DFLT_SCRUB_L2_RATE (0)
#define DFLT_SCRUB_L3_RATE (0)
#define DFLT_SCRUB_IC_RATE (0)
#define DFLT_SCRUB_DC_RATE (0)
#define DFLT_MEMORY_QUADRANK_TYPE QUADRANK_UNBUFFERED
#define DFLT_VRM_SLEW_RATE (5000)
#define DFLT_SMBUS0_BASE_ADDRESS 0xB00
#define DFLT_SMBUS1_BASE_ADDRESS 0xB20
#define DFLT_SIO_PME_BASE_ADDRESS 0xE00
#define DFLT_ACPI_PM1_EVT_BLOCK_ADDRESS 0x400
#define DFLT_ACPI_PM1_CNT_BLOCK_ADDRESS 0x404
#define DFLT_ACPI_PM_TMR_BLOCK_ADDRESS 0x408
#define DFLT_ACPI_CPU_CNT_BLOCK_ADDRESS 0x410
#define DFLT_ACPI_GPE0_BLOCK_ADDRESS 0x420
#define DFLT_SPI_BASE_ADDRESS 0xFEC10000
#define DFLT_WATCHDOG_TIMER_BASE_ADDRESS 0xFEC00000
#define DFLT_HPET_BASE_ADDRESS 0xFED00000
#define DFLT_SMI_CMD_PORT 0xB0
#define DFLT_ACPI_PMA_CNT_BLK_ADDRESS 0xFE00
#define DFLT_GEC_BASE_ADDRESS 0xFED61000
#define DFLT_AZALIA_SSID 0x780D1022
#define DFLT_SMBUS_SSID 0x780B1022
#define DFLT_IDE_SSID 0x780C1022
#define DFLT_SATA_AHCI_SSID 0x78011022
#define DFLT_SATA_IDE_SSID 0x78001022
#define DFLT_SATA_RAID5_SSID 0x78031022
#define DFLT_SATA_RAID_SSID 0x78021022
#define DFLT_EHCI_SSID 0x78081022
#define DFLT_OHCI_SSID 0x78071022
#define DFLT_LPC_SSID 0x780E1022
#define DFLT_FCH_GPP_LINK_CONFIG PortA4
#define DFLT_FCH_GPP_PORT0_PRESENT FALSE
#define DFLT_FCH_GPP_PORT1_PRESENT FALSE
#define DFLT_FCH_GPP_PORT2_PRESENT FALSE
#define DFLT_FCH_GPP_PORT3_PRESENT FALSE
#define DFLT_FCH_GPP_PORT0_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT1_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT2_HOTPLUG FALSE
#define DFLT_FCH_GPP_PORT3_HOTPLUG FALSE
// Instantiate all solution relevant data.
#include "PlatformInstall.h"

630
src/vendorcode/amd/agesa/f12/Include/gcc-intrin.h Executable file
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@ -0,0 +1,630 @@
/*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
*/
#if defined (__GNUC__)
/* I/O intrin functions. */
static __inline__ __attribute__((always_inline)) unsigned char __inbyte(unsigned short Port)
{
unsigned char value;
__asm__ __volatile__ (
"in %%dx, %%al"
: "=a" (value)
: "d" (Port)
);
return value;
}
static __inline__ __attribute__((always_inline)) unsigned short __inword(unsigned short Port)
{
unsigned short value;
__asm__ __volatile__ (
"in %%dx, %%ax"
: "=a" (value)
: "d" (Port)
);
return value;
}
static __inline__ __attribute__((always_inline)) unsigned long __indword(unsigned short Port)
{
unsigned long value;
__asm__ __volatile__ (
"in %%dx, %%eax"
: "=a" (value)
: "d" (Port)
);
return value;
}
static __inline__ __attribute__((always_inline)) void __outbyte(unsigned short Port,unsigned char Data)
{
__asm__ __volatile__ (
"out %%al, %%dx"
:
: "a" (Data), "d" (Port)
);
}
static __inline__ __attribute__((always_inline)) void __outword(unsigned short Port,unsigned short Data)
{
__asm__ __volatile__ (
"out %%ax, %%dx"
:
: "a" (Data), "d" (Port)
);
}
static __inline__ __attribute__((always_inline)) void __outdword(unsigned short Port,unsigned long Data)
{
__asm__ __volatile__ (
"out %%eax, %%dx"
:
: "a" (Data), "d" (Port)
);
}
static __inline__ __attribute__((always_inline)) void __inbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"cld ; rep ; insb "
: "=D" (Buffer), "=c" (Count)
: "d"(Port), "0"(Buffer), "1" (Count)
);
}
static __inline__ __attribute__((always_inline)) void __inwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"cld ; rep ; insw "
: "=D" (Buffer), "=c" (Count)
: "d"(Port), "0"(Buffer), "1" (Count)
);
}
static __inline__ __attribute__((always_inline)) void __indwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"cld ; rep ; insl "
: "=D" (Buffer), "=c" (Count)
: "d"(Port), "0"(Buffer), "1" (Count)
);
}
static __inline__ __attribute__((always_inline)) void __outbytestring(unsigned short Port,unsigned char *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"cld ; rep ; outsb "
: "=S" (Buffer), "=c" (Count)
: "d"(Port), "0"(Buffer), "1" (Count)
);
}
static __inline__ __attribute__((always_inline)) void __outwordstring(unsigned short Port,unsigned short *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"cld ; rep ; outsw "
: "=S" (Buffer), "=c" (Count)
: "d"(Port), "0"(Buffer), "1" (Count)
);
}
static __inline__ __attribute__((always_inline)) void __outdwordstring(unsigned short Port,unsigned long *Buffer,unsigned long Count)
{
__asm__ __volatile__ (
"cld ; rep ; outsl "
: "=S" (Buffer), "=c" (Count)
: "d"(Port), "0"(Buffer), "1" (Count)
);
}
static __inline__ __attribute__((always_inline)) unsigned long __readdr0(void)
{
unsigned long value;
__asm__ __volatile__ (
"mov %%dr0, %[value]"
: [value] "=a" (value)
);
return value;
}
static __inline__ __attribute__((always_inline)) unsigned long __readdr1(void)
{
unsigned long value;
__asm__ __volatile__ (
"mov %%dr1, %[value]"
: [value] "=a" (value)
);
return value;
}
static __inline__ __attribute__((always_inline)) unsigned long __readdr2(void)
{
unsigned long value;
__asm__ __volatile__ (
"mov %%dr2, %[value]"
: [value] "=a" (value)
);
return value;
}
static __inline__ __attribute__((always_inline)) unsigned long __readdr3(void)
{
unsigned long value;
__asm__ __volatile__ (
"mov %%dr3, %[value]"
: [value] "=a" (value)
);
return value;
}
static __inline__ __attribute__((always_inline)) unsigned long __readdr7(void)
{
unsigned long value;
__asm__ __volatile__ (
"mov %%dr7, %[value]"
: [value] "=a" (value)
);
return value;
}
static __inline__ __attribute__((always_inline)) unsigned long __readdr(unsigned long reg)
{
switch (reg){
case 0:
return __readdr0 ();
break;
case 1:
return __readdr1 ();
break;
case 2:
return __readdr2 ();
break;
case 3:
return __readdr3 ();
break;
case 7:
return __readdr7 ();
break;
default:
return -1;
}
}
static __inline__ __attribute__((always_inline)) void __writedr0(unsigned long Data)
{
__asm__ __volatile__ (
"mov %%eax, %%dr0"
:
: "a" (Data)
);
}
static __inline__ __attribute__((always_inline)) void __writedr1(unsigned long Data)
{
__asm__ __volatile__ (
"mov %%eax, %%dr1"
:
: "a" (Data)
);
}
static __inline__ __attribute__((always_inline)) void __writedr2(unsigned long Data)
{
__asm__ __volatile__ (
"mov %%eax, %%dr2"
:
: "a" (Data)
);
}
static __inline__ __attribute__((always_inline)) void __writedr3(unsigned long Data)
{
__asm__ __volatile__ (
"mov %%eax, %%dr3"
:
: "a" (Data)
);
}
static __inline__ __attribute__((always_inline)) void __writedr7(unsigned long Data)
{
__asm__ __volatile__ (
"mov %%eax, %%dr7"
:
: "a" (Data)
);
}
static __inline__ __attribute__((always_inline)) void __writedr(unsigned long reg, unsigned long Data)
{
switch (reg){
case 0:
__writedr0 (Data);
break;
case 1:
__writedr1 (Data);
break;
case 2:
__writedr2 (Data);
break;
case 3:
__writedr3 (Data);
break;
case 7:
__writedr7 (Data);
break;
default:
;
}
}
static __inline__ __attribute__((always_inline)) unsigned long __readcr0(void)
{
unsigned long value;
__asm__ __volatile__ (
"mov %%cr0, %[value]"
: [value] "=a" (value));
return value;
}
static __inline__ __attribute__((always_inline)) unsigned long __readcr2(void)
{
unsigned long value;
__asm__ __volatile__ (
"mov %%cr2, %[value]"
: [value] "=a" (value));
return value;
}
static __inline__ __attribute__((always_inline)) unsigned long __readcr3(void)
{
unsigned long value;
__asm__ __volatile__ (
"mov %%cr3, %[value]"
: [value] "=a" (value));
return value;
}
static __inline__ __attribute__((always_inline)) unsigned long __readcr4(void)
{
unsigned long value;
__asm__ __volatile__ (
"mov %%cr4, %[value]"
: [value] "=a" (value));
return value;
}
static __inline__ __attribute__((always_inline)) unsigned long __readcr8(void)
{
unsigned long value;
__asm__ __volatile__ (
"mov %%cr8, %[value]"
: [value] "=a" (value));
return value;
}
static __inline__ __attribute__((always_inline)) unsigned long __readcr(unsigned long reg)
{
switch (reg){
case 0:
return __readcr0 ();
break;
case 2:
return __readcr2 ();
break;
case 3:
return __readcr3 ();
break;
case 4:
return __readcr4 ();
break;
case 8:
return __readcr8 ();
break;
default:
return -1;
}
}
static __inline__ __attribute__((always_inline)) void __writecr0(unsigned long Data)
{
__asm__ __volatile__ (
"mov %%eax, %%cr0"
:
: "a" (Data)
);
}
static __inline__ __attribute__((always_inline)) void __writecr2(unsigned long Data)
{
__asm__ __volatile__ (
"mov %%eax, %%cr2"
:
: "a" (Data)
);
}
static __inline__ __attribute__((always_inline)) void __writecr3(unsigned long Data)
{
__asm__ __volatile__ (
"mov %%eax, %%cr3"
:
: "a" (Data)
);
}
static __inline__ __attribute__((always_inline)) void __writecr4(unsigned long Data)
{
__asm__ __volatile__ (
"mov %%eax, %%cr4"
:
: "a" (Data)
);
}
static __inline__ __attribute__((always_inline)) void __writecr8(unsigned long Data)
{
__asm__ __volatile__ (
"mov %%eax, %%cr8"
:
: "a" (Data)
);
}
static __inline__ __attribute__((always_inline)) void __writecr(unsigned long reg, unsigned long Data)
{
switch (reg){
case 0:
__writecr0 (Data);
break;
case 2:
__writecr2 (Data);
break;
case 3:
__writecr3 (Data);
break;
case 4:
__writecr4 (Data);
break;
case 8:
__writecr8 (Data);
break;
default:
;
}
}
static __inline__ __attribute__((always_inline)) UINT64 __readmsr(UINT32 msr)
{
UINT64 retval;
__asm__ __volatile__(
"rdmsr\n\t"
: "=A" (retval)
: "c" (msr)
);
return retval;
}
static __inline__ __attribute__((always_inline)) void __writemsr (UINT32 msr, UINT64 Value)
{
__asm__ __volatile__ (
"wrmsr\n\t"
:
: "c" (msr), "A" (Value)
);
}
static __inline__ __attribute__((always_inline)) UINT64 __rdtsc(void)
{
UINT64 retval;
__asm__ __volatile__ (
"rdtsc"
: "=A" (retval));
return retval;
}
static __inline__ __attribute__((always_inline)) void __cpuid(int CPUInfo[], const int InfoType)
{
__asm__ __volatile__(
"cpuid"
:"=a" (CPUInfo[0]), "=b" (CPUInfo[1]), "=c" (CPUInfo[2]), "=d" (CPUInfo[3])
: "a" (InfoType)
);
}
static __inline__ __attribute__((always_inline)) void _disable(void)
{
__asm__ __volatile__ ("cli");
}
static __inline__ __attribute__((always_inline)) void _enable(void)
{
__asm__ __volatile__ ("sti");
}
static __inline__ __attribute__((always_inline)) void __halt(void)
{
__asm__ __volatile__ ("hlt");
}
static __inline__ __attribute__((always_inline)) void __debugbreak(void)
{
__asm__ __volatile__ ("int3");
}
static __inline__ __attribute__((always_inline)) void __wbinvd(void)
{
__asm__ __volatile__ ("wbinvd");
}
static __inline__ __attribute__((always_inline)) void __lidt(void *Source)
{
__asm__ __volatile__("lidt %0" : : "m"(*(short*)Source));
}
static __inline__ __attribute__((always_inline)) void __writefsbyte(const unsigned long Offset, const unsigned char Data)
{
__asm__("movb %b[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data));
}
static __inline__ __attribute__((always_inline)) void __writefsword(const unsigned long Offset, const unsigned short Data)
{
__asm__("movw %w[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data));
}
static __inline__ __attribute__((always_inline)) void __writefsdword(const unsigned long Offset, const unsigned long Data)
{
__asm__("movl %k[Data], %%fs:%a[Offset]" : : [Offset] "ir" (Offset), [Data] "iq" (Data));
}
static __inline__ __attribute__((always_inline)) unsigned char __readfsbyte(const unsigned long Offset)
{
unsigned char value;
__asm__("movb %%fs:%a[Offset], %b[value]" : [value] "=q" (value) : [Offset] "irm" (Offset));
return value;
}
static __inline__ __attribute__((always_inline)) unsigned short __readfsword(const unsigned long Offset)
{
unsigned short value;
__asm__("movw %%fs:%a[Offset], %w[value]" : [value] "=q" (value) : [Offset] "irm" (Offset));
return value;
}
static __inline__ __attribute__((always_inline)) unsigned long long __readfsdword(unsigned long long Offset)
{
unsigned long long value;
__asm__("movl %%fs:%a[Offset], %k[value]" : [value] "=q" (value) : [Offset] "irm" (Offset));
return value;
}
#ifdef __SSE3__
typedef long long __v2di __attribute__ ((__vector_size__ (16)));
typedef long long __m128i __attribute__ ((__vector_size__ (16), __may_alias__));
static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs2 (void *__A, __m128i __B)
{
__asm__(".byte 0x64"); // fs prefix
__builtin_ia32_movntdq ((__v2di *)__A, (__v2di)__B);
}
static __inline__ __attribute__((always_inline)) void _mm_stream_si128_fs (void *__A, void *__B)
{
__m128i data;
data = (__m128i) __builtin_ia32_lddqu ((char const *)__B);
_mm_stream_si128_fs2 (__A, data);
}
static __inline__ __attribute__((always_inline)) void _mm_clflush_fs (void *__A)
{
__asm__(".byte 0x64"); // fs prefix
__builtin_ia32_clflush (__A);
}
static __inline __attribute__(( __always_inline__)) void _mm_mfence (void)
{
__builtin_ia32_mfence ();
}
static __inline __attribute__(( __always_inline__)) void _mm_sfence (void)
{
__builtin_ia32_sfence ();
}
#endif
static __inline__ __attribute__((always_inline)) void __stosb(unsigned char *dest, unsigned char data, size_t count)
{
__asm__ __volatile__ (
"cld ; rep ; stosb "
: "=D" (dest), "=c" (count)
: "a"(data), "0"(dest), "1" (count)
);
}
static __inline__ __attribute__((always_inline)) void __movsb(unsigned char *dest, unsigned char *data, size_t count)
{
__asm__ __volatile__ (
"cld ; rep ; movsb "
: "=D" (dest), "=S"(data), "=c" (count)
: "S"(data), "0"(dest), "1" (count)
);
}
static __inline__ __attribute__((always_inline))
void debug_point ( unsigned short Port, unsigned long Data )
{
__outdword (Port, Data);
__asm__ __volatile__ (".word 0xfeeb");
}
static __inline__ __attribute__((always_inline))
void delay_point ( unsigned short Port, unsigned long Data, unsigned long delayTime )
{
UINTN Index;
Index = 0;
__outdword (Port, Data);
while (Index < delayTime * 600000) {
__outdword (0xE0, 0);
Index ++;
}
}
#endif // defined (__GNUC__)

420
src/vendorcode/amd/agesa/f12/Legacy/PlatformMemoryConfiguration.inc Executable file
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; ****************************************************************************
; *
; * @file
; *
; * AMD Platform Specific Memory Configuration
; *
; * Contains AMD AGESA Memory Configuration Override Interface
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Include
; * @e \$Revision: 22910 $ @e \$Date: 2009-11-27 04:50:20 -0600 (Fri, 27 Nov 2009) $
;
; ****************************************************************************
; *
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
; *
; **************************************************************************
IFNDEF PSO_ENTRY
PSO_ENTRY TEXTEQU <UINT8>; < Platform Configuration Table Entry
ENDIF
; *****************************************************************************************
; *
; * PLATFORM SPECIFIC MEMORY DEFINITIONS
; *
; *****************************************************************************************
; */
;
; < Memory Speed and DIMM Population Masks
;
; < DDR Speed Masks
;
ANY_SPEED EQU 0FFFFFFFFh
DDR400 EQU ( 1 SHL (DDR400_FREQUENCY / 66))
DDR533 EQU ( 1 SHL (DDR533_FREQUENCY / 66))
DDR667 EQU ( 1 SHL (DDR667_FREQUENCY / 66))
DDR800 EQU ( 1 SHL (DDR800_FREQUENCY / 66))
DDR1066 EQU ( 1 SHL (DDR1066_FREQUENCY / 66))
DDR1333 EQU ( 1 SHL (DDR1333_FREQUENCY / 66))
DDR1600 EQU ( 1 SHL (DDR1600_FREQUENCY / 66))
DDR1866 EQU ( 1 SHL (DDR1866_FREQUENCY / 66))
DDR2133 EQU ( 1 SHL (DDR2133_FREQUENCY / 66))
DDR2400 EQU ( 1 SHL (DDR2400_FREQUENCY / 66))
; <
; < DIMM POPULATION MASKS
;
ANY_ EQU 0FFh
SR_DIMM0 EQU 0001h
SR_DIMM1 EQU 0010h
SR_DIMM2 EQU 0100h
SR_DIMM3 EQU 1000h
DR_DIMM0 EQU 0002h
DR_DIMM1 EQU 0020h
DR_DIMM2 EQU 0200h
DR_DIMM3 EQU 2000h
QR_DIMM0 EQU 0004h
QR_DIMM1 EQU 0040h
QR_DIMM2 EQU 0400h
QR_DIMM3 EQU 4000h
ANY_DIMM0 EQU 000Fh
ANY_DIMM1 EQU 00F0h
ANY_DIMM2 EQU 0F00h
ANY_DIMM3 EQU 0F000h
;
; Number of Dimms
;
ANY_NUM EQU 0FFh
NO_DIMM EQU 00h
ONE_DIMM EQU 01h
TWO_DIMM EQU 02h
THREE_DIMM EQU 04h
FOUR_DIMM EQU 08h
; *****************************************************************************************
; *
; * Platform Specific Override Definitions for Socket, Channel and Dimm
; * This indicates where a platform override will be applied.
; *
; *****************************************************************************************
;
; SOCKET MASKS
;
ANY_SOCKET EQU 0FFh
SOCKET0 EQU 01h
SOCKET1 EQU 02h
SOCKET2 EQU 04h
SOCKET3 EQU 08h
SOCKET4 EQU 10h
SOCKET5 EQU 20h
SOCKET6 EQU 40h
SOCKET7 EQU 80h
;
; CHANNEL MASKS
;
ANY_CHANNEL EQU 0FFh
CHANNEL_A EQU 01h
CHANNEL_B EQU 02h
CHANNEL_C EQU 04h
CHANNEL_D EQU 08h
;
; DIMM MASKS
;
ALL_DIMMS EQU 0FFh
DIMM0 EQU 01h
DIMM1 EQU 02h
DIMM2 EQU 04h
DIMM3 EQU 08h
;
; REGISTER ACCESS MASKS
;
ACCESS_NB0 EQU 0h
ACCESS_NB1 EQU 01h
ACCESS_NB2 EQU 02h
ACCESS_NB3 EQU 03h
ACCESS_NB4 EQU 04h
ACCESS_PHY EQU 05h
ACCESS_DCT_XT EQU 06h
; *****************************************************************************************
; *
; * Platform Specific Overriding Table Definitions
; *
; *****************************************************************************************
PSO_END EQU 0 ; < Table End
PSO_CKE_TRI EQU 1 ; < CKE Tristate Map
PSO_ODT_TRI EQU 2 ; < ODT Tristate Map
PSO_CS_TRI EQU 3 ; < CS Tristate Map
PSO_MAX_DIMMS EQU 4 ; < Max Dimms per channel
PSO_CLK_SPEED EQU 5 ; < Clock Speed
PSO_DIMM_TYPE EQU 6 ; < Dimm Type
PSO_MEMCLK_DIS EQU 7 ; < MEMCLK Disable Map
PSO_MAX_CHNLS EQU 8 ; < Max Channels per Socket
PSO_BUS_SPEED EQU 9 ; < Max Memory Bus Speed
PSO_MAX_CHIPSELS EQU 10 ; < Max Chipsel per Channel
PSO_MEM_TECH EQU 11 ; < Channel Memory Type
PSO_WL_SEED EQU 12 ; < DDR3 Write Levelization Seed delay
PSO_RXEN_SEED EQU 13 ; < Hardwared based RxEn seed
PSO_NO_LRDIMM_CS67_ROUTING EQU 14 ; < CS6 and CS7 are not Routed to all Memoy slots on a channel for LRDIMMs
PSO_SOLDERED_DOWN_SODIMM_TYPE EQU 15 ; < Soldered down SODIMM type
PSO_LVDIMM_VOLT1_5_SUPPORT EQU 16 ; < Force LvDimm voltage to 1.5V
; **********************************
; * CONDITIONAL PSO SPECIFIC ENTRIES
; **********************************
; Condition Types
CONDITIONAL_PSO_MIN EQU 100 ; < Start of Conditional Entry Types
PSO_CONDITION_AND EQU 100 ; < And Block - Start of Conditional block
PSO_CONDITION_LOC EQU 101 ; < Location - Specify Socket, Channel, Dimms to be affected
PSO_CONDITION_SPD EQU 102 ; < SPD - Specify a specific SPD value on a Dimm on the channel
PSO_CONDITION_REG EQU 103 ; Reserved
PSO_CONDITION_MAX EQU 103 ; < End Of Condition Entry Types
; Action Types
PSO_ACTION_MIN EQU 120 ; < Start of Action Entry Types
PSO_ACTION_ODT EQU 120 ; < ODT values to override
PSO_ACTION_ADDRTMG EQU 121 ; < Address/Timing values to override
PSO_ACTION_ODCCONTROL EQU 122 ; < ODC Control values to override
PSO_ACTION_SLEWRATE EQU 123 ; < Slew Rate value to override
PSO_ACTION_REG EQU 124 ; Reserved
PSO_ACTION_SPEEDLIMIT EQU 125 ; < Memory Bus speed Limit based on configuration
PSO_ACTION_MAX EQU 125 ; < End of Action Entry Types
CONDITIONAL_PSO_MAX EQU 139 ; < End of Conditional Entry Types
; *****************************************************************************************
; *
; * CONDITIONAL OVERRIDE TABLE MACROS
; *
; *****************************************************************************************
MEMCLK_DIS_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
DB PSO_MEMCLK_DIS
DB 10
DB SocketID
DB ChannelID
DB Bit0Map
DB Bit1Map
DB Bit2Map
DB Bit3Map
DB Bit4Map
DB Bit5Map
DB Bit6Map
DB Bit7Map
ENDM
CKE_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ
DB PSO_CKE_TRI
DB 4
DB SocketID
DB ChannelID
DB Bit0Map
DB Bit1Map
ENDM
ODT_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ
DB PSO_ODT_TRI
DB 6
DB SocketID
DB ChannelID
DB Bit0Map
DB Bit1Map
DB Bit2Map
DB Bit3Map
ENDM
CS_TRI_MAP MACRO SocketID:REQ, ChannelID:REQ, Bit0Map:REQ, Bit1Map:REQ, Bit2Map:REQ, Bit3Map:REQ, Bit4Map:REQ, Bit5Map:REQ, Bit6Map:REQ, Bit7Map:REQ
DB PSO_CS_TRI
DB 10
DB SocketID
DB ChannelID
DB Bit0Map
DB Bit1Map
DB Bit2Map
DB Bit3Map
DB Bit4Map
DB Bit5Map
DB Bit6Map
DB Bit7Map
ENDM
NUMBER_OF_DIMMS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfDimmSlotsPerChannel:REQ
DB PSO_MAX_DIMMS
DB 3
DB SocketID
DB ChannelID
DB NumberOfDimmSlotsPerChannel
ENDM
NUMBER_OF_CHIP_SELECTS_SUPPORTED MACRO SocketID:REQ, ChannelID:REQ, NumberOfChipSelectsPerChannel:REQ
DB PSO_MAX_CHIPSELS
DB 3
DB SocketID
DB ChannelID
DB NumberOfChipSelectsPerChannel
ENDM
NUMBER_OF_CHANNELS_SUPPORTED MACRO SocketID:REQ, NumberOfChannelsPerSocket:REQ
DB PSO_MAX_CHNLS
DB 3
DB SocketID
DB ANY_CHANNEL
DB NumberOfChannelsPerSocket
ENDM
OVERRIDE_DDR_BUS_SPEED MACRO SocketID:REQ, ChannelID:REQ, TimingMode:REQ, BusSpeed:REQ
PSO_BUS_SPEED
DB 10
DB SocketID
DB ChannelID
DD TimingMode
DD BusSpeed
ENDM
DRAM_TECHNOLOGY MACRO SocketID:REQ, MemTechType:REQ
DB PSO_MEM_TECH
DB 6
DB SocketID
DB ANY_CHANNEL
DD MemTechType
ENDM
WRITE_LEVELING_SEED MACRO SocketID:REQ, ChannelID:REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \
Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ
DB PSO_WL_SEED
DB 11
DB SocketID
DB ChannelID
DB Byte0Seed
DB Byte1Seed
DB Byte2Seed
DB Byte3Seed
DB Byte4Seed
DB Byte5Seed
DB Byte6Seed
DB Byte7Seed
DB ByteEccSeed
ENDM
HW_RXEN_SEED MACRO SocketID:REQ, ChannelID:REQ, Byte0Seed:REQ, Byte1Seed:REQ, Byte2Seed:REQ, Byte3Seed:REQ, Byte4Seed:REQ, Byte5Seed:REQ, \
Byte6Seed:REQ, Byte7Seed:REQ, ByteEccSeed:REQ
DB PSO_RXEN_SEED
DB 20
DB SocketID
DB ChannelID
DW Byte0Seed
DW Byte1Seed
DW Byte2Seed
DW Byte3Seed
DW Byte4Seed
DW Byte5Seed
DW Byte6Seed
DW Byte7Seed
DW ByteEccSeed
ENDM
NO_LRDIMM_CS67_ROUTING MACRO SocketID:REQ, ChannelID:REQ
DB PSO_NO_LRDIMM_CS67_ROUTING
DB 3
DB SocketID
DB ChannelID
DB 1
ENDM
SOLDERED_DOWN_SODIMM_TYPE MACRO SocketID:REQ, ChannelID:REQ
DB PSO_SOLDERED_DOWN_SODIMM_TYPE
DB 3
DB SocketID
DB ChannelID
DB 1
ENDM
LVDIMM_FORCE_VOLT1_5_FOR_D0 MACRO
DB PSO_LVDIMM_VOLT1_5_SUPPORT
DB 3
DB ANY_SOCKET
DB ANY_CHANNEL
DB 1
ENDM
; *****************************************************************************************
; *
; * CONDITIONAL OVERRIDE TABLE MACROS
; *
; *****************************************************************************************
CONDITION_AND MACRO
DB PSO_CONDITION_AND
DB 0
ENDM
COND_LOC MACRO SocketMsk:REQ, ChannelMsk:REQ, DimmMsk:REQ
DB PSO_CONDITION_LOC
DB 3
DB SocketMsk
DB ChannelMsk
DB DimmMsk
ENDM
COND_SPD MACRO Byte:REQ, Mask:REQ, Value:REQ
DB PSO_CONDITION_SPD
DB 3
DB Byte
DB Mask
DB Value
ENDM
COND_REG MACRO Access:REQ, Offset:REQ, Mask:REQ, Value:REQ
DB PSO_CONDITION_REG
DB 11
DB Access
DW Offset
DD Mask
DD Value
ENDM
ACTION_ODT MACRO Frequency:REQ, Dimms:REQ, QrDimms:REQ, DramOdt:REQ, QrDramOdt:REQ, DramDynOdt:REQ
DB PSO_ACTION_ODT
DB 9
DD Frequency
DB Dimms
DB QrDimms
DB DramOdt
DB QrDramOdt
DB DramDynOdt
ENDM
ACTION_ADDRTMG MACRO Frequency:REQ, DimmConfig:REQ, AddrTmg:REQ
DB PSO_ACTION_ADDRTMG
DB 10
DD Frequency
DW DimmConfig
DD AddrTmg
ENDM
ACTION_ODCCTRL MACRO Frequency:REQ, DimmConfig:REQ, OdcCtrl:REQ
DB PSO_ACTION_ODCCONTROL
DB 10
DD Frequency
DW DimmConfig
DD OdcCtrl
ENDM
ACTION_SLEWRATE MACRO Frequency:REQ, DimmConfig:REQ, SlewRate:REQ
DB PSO_ACTION_SLEWRATE
DB 10
DD Frequency
DW DimmConfig
DD SlewRate
ENDM
ACTION_SPEEDLIMIT MACRO DimmConfig:REQ, Dimms:REQ, SpeedLimit15:REQ, SpeedLimit135:REQ, SpeedLimit125:REQ
DB PSO_ACTION_SPEEDLIMIT
DB 9
DW DimmConfig
DB Dimms
DW SpeedLimit15
DW SpeedLimit135
DW SpeedLimit125
ENDM
; *****************************************************************************************
; *
; * END OF CONDITIONAL OVERRIDE TABLE MACROS
; *
; *****************************************************************************************

158
src/vendorcode/amd/agesa/f12/Legacy/Proc/Dispatcher.c Executable file
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@ -0,0 +1,158 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD binary block interface
*
* Contains the block entry function dispatcher
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Legacy
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
* ***************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Dispatcher.h"
#include "Options.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE LEGACY_PROC_DISPATCHER_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
extern CONST DISPATCH_TABLE DispatchTable[];
extern AMD_MODULE_HEADER mCpuModuleID;
/*---------------------------------------------------------------------------------------*/
/**
* The Dispatcher is the entry point into the AGESA software. It takes a function
* number as entry parameter in order to invoke the published function
*
* @param[in,out] ConfigPtr
*
* @return AGESA Status.
*
*/
AGESA_STATUS
CALLCONV
AmdAgesaDispatcher (
IN OUT VOID *ConfigPtr
)
{
AGESA_STATUS Status;
IMAGE_ENTRY ImageEntry;
MODULE_ENTRY ModuleEntry;
DISPATCH_TABLE *Entry;
UINT32 ImageStart;
UINT32 ImageEnd;
AMD_IMAGE_HEADER* AltImagePtr;
Status = AGESA_UNSUPPORTED;
ImageEntry = NULL;
ModuleEntry = NULL;
ImageStart = 0xFFF00000;
ImageEnd = 0xFFFFFFFF;
AltImagePtr = NULL;
Entry = (DISPATCH_TABLE *) DispatchTable;
while (Entry->FunctionId != 0) {
if ((((AMD_CONFIG_PARAMS *) ConfigPtr)->Func) == Entry->FunctionId) {
Status = Entry->EntryPoint (ConfigPtr);
break;
}
Entry++;
}
// 2. Try next dispatcher if possible, and we have not already got status back
if ((mCpuModuleID.NextBlock != NULL) && (Status == AGESA_UNSUPPORTED)) {
ModuleEntry = (MODULE_ENTRY) (UINT64) mCpuModuleID.NextBlock->ModuleDispatcher;
if (ModuleEntry != NULL) {
Status = (*ModuleEntry) (ConfigPtr);
}
}
// 3. If not this image specific function, see if we can find alternative image instead
if (Status == AGESA_UNSUPPORTED) {
if ((((AMD_CONFIG_PARAMS *)ConfigPtr)->AltImageBasePtr != 0xFFFFFFFF ) || (((AMD_CONFIG_PARAMS *)ConfigPtr)->AltImageBasePtr != 0)) {
ImageStart = ((AMD_CONFIG_PARAMS *)ConfigPtr)->AltImageBasePtr;
ImageEnd = ImageStart + 4;
// Locate/test image base that matches this component
AltImagePtr = LibAmdLocateImage ((VOID *) (UINT64)ImageStart, (VOID *) (UINT64)ImageEnd, 4096, (CHAR8 *)AGESA_ID);
if (AltImagePtr != NULL) {
//Invoke alternative Image
ImageEntry = (IMAGE_ENTRY) ((UINT64) AltImagePtr + AltImagePtr->EntryPointAddress);
Status = (*ImageEntry) (ConfigPtr);
}
}
}
return (Status);
}
/*---------------------------------------------------------------------------------------*/
/**
* The host environment interface of callout.
*
* @param[in] Func
* @param[in] Data
* @param[in,out] ConfigPtr
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
CALLCONV
AmdAgesaCallout (
IN UINT32 Func,
IN UINT32 Data,
IN OUT VOID *ConfigPtr
)
{
UINT32 Result;
Result = AGESA_UNSUPPORTED;
if (((AMD_CONFIG_PARAMS *) ConfigPtr)->CalloutPtr == NULL) {
return Result;
}
Result = (((AMD_CONFIG_PARAMS *) ConfigPtr)->CalloutPtr) (Func, Data, ConfigPtr);
return (Result);
}

259
src/vendorcode/amd/agesa/f12/Legacy/Proc/Legacy.bat Executable file
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@ -0,0 +1,259 @@
@echo off
goto Begin
:Documentation
echo off
echo **************************************************************************
echo * Legacy.Bat
echo * This batchfile establishes the build environment for an AGESA(TM)
echo * legacy build.
echo *
echo * Syntax:
echo * Legacy.bat Solution [DevTipPath] [DevKey] [DoxKey] [Release^|Debug] [Internal]
echo * Parameters:
echo * %% 1 Solution name. This is the AMD Platform Solution name that
echo * identifies the delivery package. No default, this
echo * parameter MUST be specified. This parameter MUST
echo * be specified before the DevTip Path parameter.
echo * %% 2 Path to the platform specific build directory. This is
echo * where the options file %%Solution%%Options.c is located,
echo * which contains the platform specific build option settings.
echo * If left blank, the default %%Solution%%Options.c file from
echo * the AGESA\Addendum directory is used.
echo * %% 3 Developer's key - open an interactive MSVS window. This parameter is
echo * optional, but when used it requires the first two parameters.
echo * %% 4 Documentation Key - requests a compilation of the DOxygen
echo * documentation files. key is "DOX". This parameter is
echo * optional, but when used it requires the first two parameters.
echo * %% 5 Build Configuration. There are two choices, "Release" and "Debug".
echo * Debug is the default choice if not specified. This parameter is
echo * optional, but when used it requires the first two parameters.
echo * %% 6 Internal solution file select - choose a internal solution file.This parameter
echo * is optional, but when used it requires the first two parameters.
echo * NOTE: The paths MUST have a trailing '\' character.
echo *
echo * The AGESA build environment requires the following environment
echo * variables MUST be defined for proper operation:
echo * $(AGESA_ROOT) - identifies the directory where the AGESA code
echo * is located. The top most dir; where AGESA.h is located.
echo * This must be the full path, eg D:\myPlatform\AGESA\
echo * **** This var is expected to be set by the caller ****
echo *
echo * $(Solution) - identifies the Platform Solution being targeted
echo * $(AGESA_OptsDir) - identifies the directory where the platform
echo * options and customization files are located.
echo * This must be the full path
echo *
echo * Optional build environment variables
echo *
echo * set AGESA_B1_ADDRESS=0xFFF?????
echo * Sets the B1 image base address in the ROM (otherwise 0xFFFD0000).
echo * set AGESA_B2_ADDRESS=0xFFF?????
echo * Sets the B2 image base address in the ROM (otherwise 0xFFFA0000).
echo *
echo * NOTE: The paths MUST have a trailing '\' character.
echo **************************************************************************
goto Exit
:Begin
rem Clear working vars...
set DevKey=
set DoxKey=
set Solution=
set Configuration=
rem set default to external file prefix none
set SolutionType=
rem Validate the AGESA_ROOT variable
IF "%AGESA_ROOT%"=="" goto Else001
rem User has set a path for Agesa_Root, verify that path...
IF EXIST %AGESA_ROOT%Agesa.h goto EndIf002
rem Try adding trailing '\'
set AGESA_ROOT=%AGESA_ROOT%\
IF EXIST %AGESA_ROOT%Agesa.h goto EndIf003
echo Build ERROR: Environment variable AGESA_ROOT is invalid,
echo Build ERROR: Could not find file Agesa.h at: %AGESA_ROOT%
pause
goto Documentation
:EndIf003
:EndIf002
goto EndIf001
:Else001
echo Build ERROR: Required environment variable missing: AGESA_ROOT
pause
goto Documentation
:EndIf001
rem Start processing the input parameters...
:DoLoop
rem Switch (%1)
IF /I "%1"=="DevKey" goto Case001
IF /I "%1"=="Maranello" goto Case002
IF /I "%1"=="DevTest" goto Case002
IF /I "%1"=="Danube" goto Case002
IF /I "%1"=="DanNi" goto Case002
IF /I "%1"=="Deccan" goto Case002
IF /I "%1"=="Nile" goto Case002
IF /I "%1"=="Dragon" goto Case002
IF /I "%1"=="SanMarino" goto Case002
IF /I "%1"=="Scorpius" goto Case002
IF /I "%1"=="Sabine" goto Case002
IF /I "%1"=="Lynx" goto Case002
IF /I "%1"=="Brazos" goto Case002
IF /I "%1"=="Comal" goto Case002
IF /I "%1"=="Virgo" goto Case002
IF /I "%1"=="DOX" goto Case009
IF /I "%1"=="Debug" goto Case011
IF /I "%1"=="Release" goto Case011
IF /I "%1"=="Internal" goto Case012
IF "%1"=="" goto Case006
goto Case004
:Case001
rem Case 1: Special command param
set DevKey=DevKey
goto EndSwitch
:Case002
rem Case 2: Solution name parameter
rem Set the Platform Solution name for the build environment
rem Validation of the names was done by the IF's at the top of DoLoop
set Solution=%1
goto EndSwitch
:Case004
rem Case 4: Path param, check for validity
rem Check if parameter matches the default
rem Check for shortcut versions of the default. Also
rem checking for missing trailing '\'
IF /I "%1"=="Addendum" goto Then040
IF /I "%1"=="Addendum\" goto Then040
IF /I "%1"=="..\Addendum" goto Then040
IF /I "%1"=="..\Addendum\" goto Then040
IF /I "%1"=="..\..\Addendum" goto Then040
IF /I "%1"=="..\..\Addendum\" goto Then040
goto Else040
:Then040
set AGESA_OptsDir=%AGESA_ROOT%Addendum\
Echo Build WARNING: User selected the default options path.
goto EndIf040
:Else040
set AGESA_OptsDir=%1
rem Non-default path given,
rem Validate the AGESA_OptsDir parameter ( %%1 = %1 )...
IF /I "%Solution%"=="" goto Else042
IF EXIST %AGESA_OptsDir%%Solution%Options.c goto EndIf044
rem Check if param was missing trailing '\'...
set AGESA_OptsDir=%AGESA_OptsDir%\
IF EXIST %AGESA_OptsDir%%Solution%Options.c goto EndIf045
rem If using the default, assume the release file is in place.
rem Could not find options file, post an error
Echo Build ERROR: Path to AGESA options file is not valid...
Echo . . Could not find options file: %AGESA_OptsDir%%Solution%Options.c
set AGESA_OptsDir=
set Solution=
exit /B 5
:EndIf045
:EndIf044
goto EndIf042
:Else042
rem Else042 - parameter ordering error, need to specify solution before tip path
Echo Build ERROR: The 'Solution' name was not recognized or
Echo The Solution must be specified before the Development tip path
Echo . . . Legacy.bat Solution [DevTipPath] [DevKey] [DoxKey]
exit /B 4
:EndIf042
:EndIf040
goto EndSwitch
:Case006
rem Case 6: Parameter is blank, end of list
rem Validate the required Environment Variables
IF /I "%Solution%"=="" goto Else066
IF NOT "%AGESA_OptsDir%"=="" goto Else060
Rem No path param specified. Use the default file shipped with the AGESA package...
Echo Build WARNING: Using default options file.
set AGESA_OptsDir=%AGESA_ROOT%Addendum\
goto EndIf060
:Else060
rem Else060 - tip path may have been set by caller prior to call,
rem Validate the AGESA_OptsDir parameter ( %%AGESA_OptsDir = %AGESA_OptsDir% )...
IF EXIST %AGESA_OptsDir%%Solution%Options.c goto EndIf061
rem Check if param was missing trailing '\'...
set AGESA_OptsDir=%AGESA_OptsDir%\
IF EXIST %AGESA_OptsDir%%Solution%Options.c goto EndIf062
rem If using the default, assume the release file is in place.
rem Could not find options file, post an error
Echo Build ERROR: Path to AGESA options file is not valid...
Echo . . Could not find options file: %AGESA_OptsDir%%Solution%Options.c
set AGESA_OptsDir=
set Solution=
exit /B 4
:EndIf062
:EndIf061
:EndIf060
goto EndIf066
:Else066
rem Else066 - parameter missing error, need to specify 'solution'
Echo Build ERROR: The Platform Solution name must be specified:
Echo . . . Legacy.bat Solution [DevTipPath] [DevKey] [DoxKey]
exit /B 4
:EndIf066
goto EndDo
:Case009
rem Case 9: Documentation generation key
set DoxKey=DoxKey
goto EndSwitch
:Case011
rem Case 11: Build Configuration
set Configuration=%1
goto EndSwitch
:Case012
rem Case 12: Select Internal solution file prefix
set SolutionType=%1
goto EndSwitch
:EndSwitch
SHIFT
goto DoLoop
:EndDo
rem # Ensure that Microsoft Visual Studio 2005 is installed on this machine.
IF NOT "%VS80COMNTOOLS%"=="" goto EndIf95
echo ---------------------------------------------------------------------
echo - Building AGESA ARCH2008 requires Microsoft Visual Studio 2005 -
echo - Install Visual Studio 2005 and confirm environment -
echo - variable VS80COMNTOOLS is present. -
echo ---------------------------------------------------------------------
pause
exit
:EndIf95
rem set the Visual Studio 32-bit development environment
call "%VS80COMNTOOLS%vsvars32.bat"
rem Launch the documentation generator if selected by the user
IF NOT "%DoxKey%"=="DoxKey" goto EndIf100
devenv %AGESA_ROOT%Proc\AgesaDoc.sln /Rebuild "Release|Win32"
:EndIf100
rem Use the default build configuration if none was specified.
IF NOT "%Configuration%"=="" goto EndIf110
set Configuration=Debug
:EndIf110
rem Check image bases
IF NOT "%AGESA_B1_ADDRESS%"=="" goto EndIf120
set AGESA_B1_ADDRESS=0xFFFD0000
:EndIf120
IF NOT "%AGESA_B2_ADDRESS%"=="" goto EndIf130
set AGESA_B2_ADDRESS=0xFFFA0000
:EndIf130
rem Check if the 'secret' developers' key was used, open an interactive VS window
IF NOT "%DevKey%"=="DevKey" goto Else140
set DevKey=
rem This is the command to open an interactive development window ...
start /NORMAL devenv.exe %AGESA_ROOT%Legacy\Proc\%Solution%%SolutionType%Legacy.sln /ProjectConfig "%Configuration%|Win32"
goto EndIf140
:Else140
rem Else140 - This is the command to perform a background or automated build ...
devenv %AGESA_ROOT%Legacy\Proc\%Solution%%SolutionType%Legacy.sln /Rebuild "%Configuration%|Win32"
:EndIf140
:Exit
exit /B 0

420
src/vendorcode/amd/agesa/f12/Legacy/Proc/agesaCallouts.c Executable file
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@ -0,0 +1,420 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD CPU AGESA Callout Functions
*
* Contains code to set / get useful platform information.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Common
* @e \$Revision: 49633 $ @e \$Date: 2011-03-26 06:52:29 +0800 (Sat, 26 Mar 2011) $
*
*/
/*****************************************************************************
* AMD Generic Encapsulated Software Architecture
*
* Description: agesaCallouts.c - AGESA Call out functions
*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuRegisters.h"
#include "Dispatcher.h"
#include "cpuServices.h"
#include "Ids.h"
#include "Filecode.h"
#define FILECODE LEGACY_PROC_AGESACALLOUTS_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S - (AGESA ONLY)
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
*
* Call the host environment interface to do the warm or cold reset.
*
* @param[in] ResetType Warm or Cold Reset is requested
* @param[in,out] StdHeader Config header
*
*/
VOID
AgesaDoReset (
IN UINTN ResetType,
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
AGESA_STATUS Status;
WARM_RESET_REQUEST Request;
// Clear warm request bit and set state bits to the current post stage
GetWarmResetFlag (StdHeader, &Request);
Request.RequestBit = FALSE;
Request.StateBits = Request.PostStage;
SetWarmResetFlag (StdHeader, &Request);
Status = AmdAgesaCallout (AGESA_DO_RESET, (UINT32)ResetType, (VOID *) StdHeader);
}
/*---------------------------------------------------------------------------------------*/
/**
*
* Call the host environment interface to allocate buffer in main system memory.
*
* @param[in] FcnData
* @param[in,out] AllocParams Heap manager parameters
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaAllocateBuffer (
IN UINTN FcnData,
IN OUT AGESA_BUFFER_PARAMS *AllocParams
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_ALLOCATE_BUFFER, (UINT32)FcnData, (VOID *) AllocParams);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to deallocate buffer in main system memory.
*
* @param[in] FcnData
* @param[in,out] DeallocParams Heap Manager parameters
*
* @return The AGESA Status returned from the callout.
*/
AGESA_STATUS
AgesaDeallocateBuffer (
IN UINTN FcnData,
IN OUT AGESA_BUFFER_PARAMS *DeallocParams
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_DEALLOCATE_BUFFER, (UINT32)FcnData, (VOID *) DeallocParams);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
*
* Call the host environment interface to Locate buffer Pointer in main system memory
*
* @param[in] FcnData
* @param[in,out] LocateParams Heap manager parameters
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaLocateBuffer (
IN UINTN FcnData,
IN OUT AGESA_BUFFER_PARAMS *LocateParams
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_LOCATE_BUFFER, (UINT32)FcnData, (VOID *) LocateParams);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to launch APs
*
* @param[in] ApicIdOfCore
* @param[in,out] LaunchApParams
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaRunFcnOnAp (
IN UINTN ApicIdOfCore,
IN AP_EXE_PARAMS *LaunchApParams
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_RUNFUNC_ONAP, (UINT32)ApicIdOfCore, (VOID *) LaunchApParams);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to read an SPD's content.
*
* @param[in] FcnData
* @param[in,out] ReadSpd
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaReadSpd (
IN UINTN FcnData,
IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_READ_SPD, (UINT32)FcnData, ReadSpd);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to read an SPD's content.
*
* @param[in] FcnData
* @param[in,out] ReadSpd
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaReadSpdRecovery (
IN UINTN FcnData,
IN OUT AGESA_READ_SPD_PARAMS *ReadSpd
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_READ_SPD_RECOVERY, (UINT32)FcnData, ReadSpd);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to provide a user hook opportunity.
*
* @param[in] FcnData
* @param[in,out] MemData
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaHookBeforeDramInitRecovery (
IN UINTN FcnData,
IN OUT MEM_DATA_STRUCT *MemData
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DRAM_INIT_RECOVERY, (UINT32)FcnData, MemData);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to provide a user hook opportunity.
*
* @param[in] SocketIdModuleId - (SocketID << 8) | ModuleId
* @param[in,out] MemData
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaHookBeforeDramInit (
IN UINTN SocketIdModuleId,
IN OUT MEM_DATA_STRUCT *MemData
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DRAM_INIT, (UINT32)SocketIdModuleId, MemData);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to provide a user hook opportunity.
*
* @param[in] SocketIdModuleId - (SocketID << 8) | ModuleId
* @param[in,out] MemData
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaHookBeforeDQSTraining (
IN UINTN SocketIdModuleId,
IN OUT MEM_DATA_STRUCT *MemData
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_HOOKBEFORE_DQS_TRAINING, (UINT32)SocketIdModuleId, MemData);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to provide a user hook opportunity.
*
* @param[in] FcnData
* @param[in,out] MemData
*
* @return The AGESA Status returned from the callout.
*
*/
AGESA_STATUS
AgesaHookBeforeExitSelfRefresh (
IN UINTN FcnData,
IN OUT MEM_DATA_STRUCT *MemData
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_HOOKBEFORE_EXIT_SELF_REF, (UINT32)FcnData, MemData);
return Status;
}
/*---------------------------------------------------------------------------------------*/
/**
* Call the host environment interface to provide a user hook opportunity.
*
* @param[in] Data
* @param[in,out] IdsCalloutData
*
* @return The AGESA Status returned from the callout.
*
*/
/*
AGESA_STATUS
AgesaGetIdsData (
IN UINTN Data,
IN OUT IDS_CALLOUT_STRUCT *IdsCalloutData
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_GET_IDS_INIT_DATA, (UINT32)Data, IdsCalloutData);
return Status;
}
*/
/*----------------------------------------------------------------------------------------*/
/**
* PCIE slot reset control
*
*
*
* @param[in] FcnData Function data
* @param[in] ResetInfo Reset information
* @retval Status Agesa status
*/
AGESA_STATUS
AgesaPcieSlotResetControl (
IN UINTN FcnData,
IN PCIe_SLOT_RESET_INFO *ResetInfo
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_GNB_PCIE_SLOT_RESET, (UINT32) FcnData, ResetInfo);
return Status;
}
/*----------------------------------------------------------------------------------------*/
/**
* OEM callout function for FCH data override
*
*
* @param[in] FchData FCH data pointer
* @retval Status This feature is not supported
*/
AGESA_STATUS
AgesaFchOemCallout (
IN VOID *FchData
)
{
AGESA_STATUS Status;
Status = AmdAgesaCallout (AGESA_FCH_OEM_CALLOUT, (UINT32) 0, FchData);
return Status;
}

2674
src/vendorcode/amd/agesa/f12/Legacy/Proc/arch2008.asm Executable file
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src/vendorcode/amd/agesa/f12/Legacy/Proc/hobTransfer.c Executable file
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/* $NoKeywords:$ */
/**
* @file
*
* AMD Hob Transfer functions.
*
* Contains code that copy Heap to temp memory or main memory.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "cpuRegisters.h"
#include "GeneralServices.h"
#include "cpuServices.h"
#include "cpuCacheInit.h"
#include "cpuFamilyTranslation.h"
#include "heapManager.h"
#include "cpuLateInit.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE LEGACY_PROC_HOBTRANSFER_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P U B L I C F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
extern BUILD_OPT_CFG UserOptions;
/* -----------------------------------------------------------------------------*/
/**
*
* CopyHeapToTempRamAtPost
*
* This function copies BSP heap content to RAM
*
* @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct.
*
* @retval AGESA_STATUS
*
*/
AGESA_STATUS
CopyHeapToTempRamAtPost (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 *BaseAddressInCache;
UINT8 *BaseAddressInTempMem;
UINT8 *Source;
UINT8 *Destination;
UINT8 AlignTo16ByteInCache;
UINT8 AlignTo16ByteInTempMem;
UINT8 Ignored;
UINT32 SizeOfNodeData;
UINT32 TotalSize;
UINT32 HeapRamFixMtrr;
UINT32 HeapRamVariableMtrr;
UINT32 HeapInCacheOffset;
UINT64 MsrData;
UINT64 VariableMtrrBase;
UINT64 VariableMtrrMask;
UINTN AmdHeapRamAddress;
AGESA_STATUS IgnoredStatus;
BUFFER_NODE *HeapInCache;
BUFFER_NODE *HeapInTempMem;
HEAP_MANAGER *HeapManagerInCache;
HEAP_MANAGER *HeapManagerInTempMem;
CACHE_INFO *CacheInfoPtr;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
AmdHeapRamAddress = (UINTN) UserOptions.CfgHeapDramAddress;
//
//If the user define address above 1M, Mem Init has already set
//whole available memory as WB cacheable.
//
if (AmdHeapRamAddress < 0x100000) {
// Region below 1MB
// Fixed MTTR region
// turn on modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x80000;
LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
if (AmdHeapRamAddress >= 0xC0000) {
//
// 0xC0000 ~ 0xFFFFF
//
HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX4k_C0000 + (((AmdHeapRamAddress >> 16) & 0x3) * 2));
MsrData = (UINT64)AMD_MTRR_FIX4K_UC_DRAM;
LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader);
LibAmdMsrWrite ((HeapRamFixMtrr + 1), &MsrData, StdHeader);
} else if (AmdHeapRamAddress >= 0x80000) {
//
// 0x80000~0xBFFFF
//
HeapRamFixMtrr = (UINT32) (AMD_MTRR_FIX16k_80000 + ((AmdHeapRamAddress >> 17) & 0x1));
MsrData = (UINT64)AMD_MTRR_FIX16K_UC_DRAM;
LibAmdMsrWrite (HeapRamFixMtrr, &MsrData, StdHeader);
} else {
//
// 0x0 ~ 0x7FFFF
//
LibAmdMsrRead (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
MsrData = MsrData & (~(0xFF << (8 * ((AmdHeapRamAddress >> 16) & 0x7))));
MsrData = MsrData | (AMD_MTRR_FIX64K_UC_DRAM << (8 * ((AmdHeapRamAddress >> 16) & 0x7)));
LibAmdMsrWrite (AMD_MTRR_FIX64k_00000, &MsrData, StdHeader);
}
// Turn on MTTR enable bit and turn off modification bit
LibAmdMsrRead (MSR_SYS_CFG, &MsrData, StdHeader);
MsrData |= 0x40000;
MsrData &= 0xFFFFFFFFFFF7FFFFull;
LibAmdMsrWrite (MSR_SYS_CFG, &MsrData, StdHeader);
} else {
// Region above 1MB
// Variable MTTR region
// Get family specific cache Info
GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **)&FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **) &CacheInfoPtr, &Ignored, StdHeader);
// Find an empty MTRRphysBase/MTRRphysMask
for (HeapRamVariableMtrr = AMD_MTRR_VARIABLE_HEAP_BASE;
HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0;
HeapRamVariableMtrr--) {
LibAmdMsrRead (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
LibAmdMsrRead ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
if ((VariableMtrrBase == 0) && (VariableMtrrMask == 0)) {
break;
}
}
if (HeapRamVariableMtrr < AMD_MTRR_VARIABLE_BASE0) {
// All variable MTRR is used.
ASSERT (FALSE);
}
// Set variable MTRR base and mask
// If the address ranges of two or more MTRRs overlap
// and if at least one of the memory types is UC, the UC memory type is used.
VariableMtrrBase = (UINT64) (AmdHeapRamAddress & CacheInfoPtr->HeapBaseMask);
VariableMtrrMask = CacheInfoPtr->VariableMtrrHeapMask & (UINT64)AMD_HEAP_MTRR_MASK;
LibAmdMsrWrite (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
LibAmdMsrWrite ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
}
// Copying Heap content
if (IsBsp (StdHeader, &IgnoredStatus)) {
TotalSize = sizeof (HEAP_MANAGER);
SizeOfNodeData = 0;
AlignTo16ByteInTempMem = 0;
BaseAddressInCache = (UINT8 *) StdHeader->HeapBasePtr;
HeapManagerInCache = (HEAP_MANAGER *) BaseAddressInCache;
HeapInCacheOffset = HeapManagerInCache->FirstActiveBufferOffset;
HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset);
BaseAddressInTempMem = (UINT8 *) UserOptions.CfgHeapDramAddress;
HeapManagerInTempMem = (HEAP_MANAGER *) BaseAddressInTempMem;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize);
// copy heap from cache to temp memory.
// only heap with persist great than HEAP_LOCAL_CACHE will be copied.
// Note: Only copy heap with persist greater than HEAP_LOCAL_CACHE.
while (HeapInCacheOffset != AMD_HEAP_INVALID_HEAP_OFFSET) {
if (HeapInCache->Persist > HEAP_LOCAL_CACHE) {
AlignTo16ByteInCache = HeapInCache->PadSize;
AlignTo16ByteInTempMem = (UINT8) ((0x10 - (((UINTN) (VOID *) HeapInTempMem + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL) & 0xF)) & 0xF);
SizeOfNodeData = HeapInCache->BufferSize - AlignTo16ByteInCache;
TotalSize = (UINT32) (TotalSize + sizeof (BUFFER_NODE) + SizeOfNodeData + AlignTo16ByteInTempMem);
Source = (UINT8 *) HeapInCache + sizeof (BUFFER_NODE) + AlignTo16ByteInCache;
Destination = (UINT8 *) HeapInTempMem + sizeof (BUFFER_NODE) + AlignTo16ByteInTempMem;
LibAmdMemCopy (HeapInTempMem, HeapInCache, sizeof (BUFFER_NODE), StdHeader);
LibAmdMemCopy (Destination, Source, SizeOfNodeData, StdHeader);
HeapInTempMem->OffsetOfNextNode = TotalSize;
HeapInTempMem->BufferSize = SizeOfNodeData + AlignTo16ByteInTempMem;
HeapInTempMem->PadSize = AlignTo16ByteInTempMem;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize);
}
HeapInCacheOffset = HeapInCache->OffsetOfNextNode;
HeapInCache = (BUFFER_NODE *) (BaseAddressInCache + HeapInCacheOffset);
}
// initialize heap manager
if (TotalSize == sizeof (HEAP_MANAGER)) {
// heap is empty
HeapManagerInTempMem->UsedSize = sizeof (HEAP_MANAGER);
HeapManagerInTempMem->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET;
HeapManagerInTempMem->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER);
} else {
// heap is NOT empty
HeapManagerInTempMem->UsedSize = TotalSize;
HeapManagerInTempMem->FirstActiveBufferOffset = sizeof (HEAP_MANAGER);
HeapManagerInTempMem->FirstFreeSpaceOffset = TotalSize;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize - SizeOfNodeData - AlignTo16ByteInTempMem - sizeof (BUFFER_NODE));
HeapInTempMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + TotalSize);
}
// heap signature
HeapManagerInCache->Signature = 0x00000000;
HeapManagerInTempMem->Signature = HEAP_SIGNATURE_VALID;
// Free space node
HeapInTempMem->BufferSize = (UINT32) (AMD_HEAP_SIZE_PER_CORE - TotalSize);
HeapInTempMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
}
return AGESA_SUCCESS;
}
/* -----------------------------------------------------------------------------*/
/**
*
* CopyHeapToMainRamAtPost
*
* This function copies Temp Ram heap content to Main Ram
*
* @param[in,out] StdHeader - Pointer to AMD_CONFIG_PARAMS struct.
*
* @retval AGESA_STATUS
*
*/
AGESA_STATUS
CopyHeapToMainRamAtPost (
IN OUT AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 *BaseAddressInTempMem;
UINT8 *BaseAddressInMainMem;
UINT8 *Source;
UINT8 *Destination;
UINT8 AlignTo16ByteInTempMem;
UINT8 AlignTo16ByteInMainMem;
UINT8 Ignored;
UINT32 SizeOfNodeData;
UINT32 TotalSize;
UINT32 HeapInTempMemOffset;
UINT32 HeapRamVariableMtrr;
UINT64 VariableMtrrBase;
UINT64 VariableMtrrMask;
AGESA_STATUS IgnoredStatus;
BUFFER_NODE *HeapInTempMem;
BUFFER_NODE *HeapInMainMem;
HEAP_MANAGER *HeapManagerInTempMem;
HEAP_MANAGER *HeapManagerInMainMem;
AGESA_BUFFER_PARAMS AgesaBuffer;
CACHE_INFO *CacheInfoPtr;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
if (IsBsp (StdHeader, &IgnoredStatus)) {
TotalSize = sizeof (HEAP_MANAGER);
SizeOfNodeData = 0;
AlignTo16ByteInMainMem = 0;
BaseAddressInTempMem = (UINT8 *) StdHeader->HeapBasePtr;
HeapManagerInTempMem = (HEAP_MANAGER *) StdHeader->HeapBasePtr;
HeapInTempMemOffset = HeapManagerInTempMem->FirstActiveBufferOffset;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + HeapInTempMemOffset);
AgesaBuffer.StdHeader = *StdHeader;
AgesaBuffer.BufferHandle = AMD_HEAP_IN_MAIN_MEMORY_HANDLE;
AgesaBuffer.BufferLength = AMD_HEAP_SIZE_PER_CORE;
if (AgesaAllocateBuffer (0, &AgesaBuffer) != AGESA_SUCCESS) {
return AGESA_ERROR;
}
BaseAddressInMainMem = (UINT8 *) AgesaBuffer.BufferPointer;
HeapManagerInMainMem = (HEAP_MANAGER *) BaseAddressInMainMem;
HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize);
LibAmdMemFill (BaseAddressInMainMem, 0x00, AMD_HEAP_SIZE_PER_CORE, StdHeader);
// copy heap from temp memory to main memory.
// only heap with persist great than HEAP_TEMP_MEM will be copied.
// Note: Only copy heap buffers with persist greater than HEAP_TEMP_MEM.
while (HeapInTempMemOffset != AMD_HEAP_INVALID_HEAP_OFFSET) {
if (HeapInTempMem->Persist > HEAP_TEMP_MEM) {
AlignTo16ByteInTempMem = HeapInTempMem->PadSize;
AlignTo16ByteInMainMem = (UINT8) ((0x10 - (((UINTN) (VOID *) HeapInMainMem + sizeof (BUFFER_NODE) + SIZE_OF_SENTINEL) & 0xF)) & 0xF);
SizeOfNodeData = HeapInTempMem->BufferSize - AlignTo16ByteInTempMem;
TotalSize = (UINT32) (TotalSize + sizeof (BUFFER_NODE) + SizeOfNodeData + AlignTo16ByteInMainMem);
Source = (UINT8 *) HeapInTempMem + sizeof (BUFFER_NODE) + AlignTo16ByteInTempMem;
Destination = (UINT8 *) HeapInMainMem + sizeof (BUFFER_NODE) + AlignTo16ByteInMainMem;
LibAmdMemCopy (HeapInMainMem, HeapInTempMem, sizeof (BUFFER_NODE), StdHeader);
LibAmdMemCopy (Destination, Source, SizeOfNodeData, StdHeader);
HeapInMainMem->OffsetOfNextNode = TotalSize;
HeapInMainMem->BufferSize = SizeOfNodeData + AlignTo16ByteInMainMem;
HeapInMainMem->PadSize = AlignTo16ByteInMainMem;
HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize);
}
HeapInTempMemOffset = HeapInTempMem->OffsetOfNextNode;
HeapInTempMem = (BUFFER_NODE *) (BaseAddressInTempMem + HeapInTempMemOffset);
}
// initialize heap manager
if (TotalSize == sizeof (HEAP_MANAGER)) {
// heap is empty
HeapManagerInMainMem->UsedSize = sizeof (HEAP_MANAGER);
HeapManagerInMainMem->FirstActiveBufferOffset = AMD_HEAP_INVALID_HEAP_OFFSET;
HeapManagerInMainMem->FirstFreeSpaceOffset = sizeof (HEAP_MANAGER);
} else {
// heap is NOT empty
HeapManagerInMainMem->UsedSize = TotalSize;
HeapManagerInMainMem->FirstActiveBufferOffset = sizeof (HEAP_MANAGER);
HeapManagerInMainMem->FirstFreeSpaceOffset = TotalSize;
HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize - SizeOfNodeData - AlignTo16ByteInMainMem - sizeof (BUFFER_NODE));
HeapInMainMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
HeapInMainMem = (BUFFER_NODE *) (BaseAddressInMainMem + TotalSize);
}
// heap signature
HeapManagerInTempMem->Signature = 0x00000000;
HeapManagerInMainMem->Signature = HEAP_SIGNATURE_VALID;
// Free space node
HeapInMainMem->BufferSize = AMD_HEAP_SIZE_PER_CORE - TotalSize;
HeapInMainMem->OffsetOfNextNode = AMD_HEAP_INVALID_HEAP_OFFSET;
}
// if address of heap in temp memory is above 1M, then we must used one variable MTRR.
if (StdHeader->HeapBasePtr >= 0x100000) {
// Find out which variable MTRR was used in CopyHeapToTempRamAtPost.
GetCpuServicesOfCurrentCore ((const CPU_SPECIFIC_SERVICES **) &FamilySpecificServices, StdHeader);
FamilySpecificServices->GetCacheInfo (FamilySpecificServices, (const VOID **) &CacheInfoPtr, &Ignored, StdHeader);
for (HeapRamVariableMtrr = AMD_MTRR_VARIABLE_HEAP_BASE;
HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0;
HeapRamVariableMtrr--) {
LibAmdMsrRead (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
LibAmdMsrRead ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
if ((VariableMtrrBase == (UINT64) (StdHeader->HeapBasePtr & CacheInfoPtr->HeapBaseMask)) &&
(VariableMtrrMask == (UINT64) (CacheInfoPtr->VariableMtrrHeapMask & (UINT64) AMD_HEAP_MTRR_MASK))) {
break;
}
}
if (HeapRamVariableMtrr >= AMD_MTRR_VARIABLE_BASE0) {
// Clear variable MTRR which set in CopyHeapToTempRamAtPost.
VariableMtrrBase = 0;
VariableMtrrMask = 0;
LibAmdMsrWrite (HeapRamVariableMtrr, &VariableMtrrBase, StdHeader);
LibAmdMsrWrite ((HeapRamVariableMtrr + 1), &VariableMtrrMask, StdHeader);
}
}
return AGESA_SUCCESS;
}

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; ****************************************************************************
; *
; * @file
; *
; * Agesa structures and definitions
; *
; * Contains AMD AGESA core interface
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Include
; * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
;
; ****************************************************************************
; *
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
; *
; **************************************************************************
UINT64 TEXTEQU <QWORD>
UINT32 TEXTEQU <DWORD>
UINT16 TEXTEQU <WORD>
UINT8 TEXTEQU <BYTE>
CHAR8 TEXTEQU <BYTE>
BOOLEAN TEXTEQU <BYTE>
POINTER TEXTEQU <DWORD>
; AGESA Types and Definitions
AGESA_REVISION EQU "Arch2008"
AGESA_ID EQU "AGESA"
LAST_ENTRY EQU 0FFFFFFFFh
IMAGE_SIGNATURE EQU 'DMA$'
IOCF8 EQU 0CF8h
IOCFC EQU 0CFCh
; The return status for all AGESA public services.
; Services return the most severe status of any logged event. Status other than SUCCESS, UNSUPPORTED, and BOUNDS_CHK
; will have log entries with more detail.
AGESA_SUCCESS EQU 0 ; < The service completed normally. Info may be logged.
AGESA_UNSUPPORTED EQU 1 ; < The dispatcher or create struct had an unimplemented function requested.
; < Not logged.
AGESA_BOUNDS_CHK EQU 2 ; < A dynamic parameter was out of range and the service was not provided.
; < Example, memory address not installed, heap buffer handle not found.
; < Not Logged.
; AGESA_STATUS of greater severity (the ones below this line), always have a log entry available.
AGESA_ALERT EQU 3 ; < An observed condition, but no loss of function.
; < See log. Example, HT CRC.
AGESA_WARNING EQU 4 ; < Possible or minor loss of function. See Log.
AGESA_ERROR EQU 5 ; < Significant loss of function, boot may be possible. See Log.
AGESA_CRITICAL EQU 6 ; < Continue boot only to notify user. See Log.
AGESA_FATAL EQU 7 ; < Halt booting. See Log.
AgesaStatusMax EQU 8 ; < Not a status, use for limit checking.
AGESA_STATUS TEXTEQU <DWORD>
; For checking whether a status is at or above the mandatory log level.
AGESA_STATUS_LOG_LEVEL EQU AGESA_ALERT
CALLOUT_ENTRY TEXTEQU <POINTER>
IMAGE_ENTRY TEXTEQU <POINTER>
MODULE_ENTRY TEXTEQU <POINTER>
; This allocation type is used by the AmdCreateStruct entry point
PreMemHeap EQU 0 ; < Create heap in cache.
PostMemDram EQU 1 ; < Create heap in memory.
ByHost EQU 2 ; < Create heap by Host.
ALLOCATION_METHOD TEXTEQU <DWORD>
; These width descriptors are used by the library function, and others, to specify the data size
AccessWidth8 EQU 1 ; < Access width is 8 bits.
AccessWidth16 EQU 2 ; < Access width is 16 bits.
AccessWidth32 EQU 3 ; < Access width is 32 bits.
AccessWidth64 EQU 4 ; < Access width is 64 bits.
AccessS3SaveWidth8 EQU 81h ; < Save 8 bits data.
AccessS3SaveWidth16 EQU 130 ; < Save 16 bits data.
AccessS3SaveWidth32 EQU 131 ; < Save 32 bits data.
AccessS3SaveWidth64 EQU 132 ; < Save 64 bits data.
ACCESS_WIDTH TEXTEQU <DWORD>
; AGESA struct name
; AGESA BASIC FUNCTIONS
AMD_INIT_RECOVERY EQU 00020000h
AMD_CREATE_STRUCT EQU 00020001h
AMD_INIT_EARLY EQU 00020002h
AMD_INIT_ENV EQU 00020003h
AMD_INIT_LATE EQU 00020004h
AMD_INIT_MID EQU 00020005h
AMD_INIT_POST EQU 00020006h
AMD_INIT_RESET EQU 00020007h
AMD_INIT_RESUME EQU 00020008h
AMD_RELEASE_STRUCT EQU 00020009h
AMD_S3LATE_RESTORE EQU 0002000Ah
AMD_S3_SAVE EQU 0002000Bh
AMD_GET_APIC_ID EQU 0002000Ch
AMD_GET_PCI_ADDRESS EQU 0002000Dh
AMD_IDENTIFY_CORE EQU 0002000Eh
AMD_READ_EVENT_LOG EQU 0002000Fh
AMD_GET_EXECACHE_SIZE EQU 00020010h
AMD_LATE_RUN_AP_TASK EQU 00020011h
AMD_IDENTIFY_DIMMS EQU 00020012h
AGESA_STRUCT_NAME TEXTEQU <DWORD>
; ResetType constant values
WARM_RESET_WHENEVER EQU 1
COLD_RESET_WHENEVER EQU 2
WARM_RESET_IMMEDIATELY EQU 3
COLD_RESET_IMMEDIATELY EQU 4
; AGESA Structures
; The standard header for all AGESA services.
AMD_CONFIG_PARAMS STRUCT
ImageBasePtr UINT32 ? ; < The AGESA Image base address.
Func UINT32 ? ; < The service desired, @sa dispatch.h.
AltImageBasePtr UINT32 ? ; < Alternate Image location
CalloutPtr CALLOUT_ENTRY ? ; < For Callout from AGESA
HeapStatus UINT8 ? ; < For heap status from boot time slide.
HeapBasePtr UINT64 ? ; < Location of the heap
Reserved UINT8 (7) DUP (?) ; < This space is reserved for future use.
AMD_CONFIG_PARAMS ENDS
; Create Struct Interface.
AMD_INTERFACE_PARAMS STRUCT
StdHeader AMD_CONFIG_PARAMS {} ; < Config header
AgesaFunctionName AGESA_STRUCT_NAME ? ; < The service to init, @sa dispatch.h
AllocationMethod ALLOCATION_METHOD ? ; < How to handle buffer allocation
NewStructSize UINT32 ? ; < The size of the allocated data, in for ByHost, else out only.
NewStructPtr POINTER ? ; < The struct for the service.
; < The struct to init for ByHost allocation,
; < the initialized struct on return.
AMD_INTERFACE_PARAMS ENDS
FUNC_0 EQU 0 ; bit-placed for PCI address creation
FUNC_1 EQU 1
FUNC_2 EQU 2
FUNC_3 EQU 3
FUNC_4 EQU 4
FUNC_5 EQU 5
FUNC_6 EQU 6
FUNC_7 EQU 7
; AGESA Binary module header structure
AMD_IMAGE_HEADER STRUCT
Signature UINT32 ? ; < Binary Signature
CreatorID CHAR8 (8) DUP (?) ; < 8 characters ID
Version CHAR8 (12) DUP (?) ; < 12 characters version
ModuleInfoOffset UINT32 ? ; < Offset of module
EntryPointAddress UINT32 ? ; < Entry address
ImageBase UINT32 ? ; < Image base
RelocTableOffset UINT32 ? ; < Relocate Table offset
ImageSize UINT32 ? ; < Size
Checksum UINT16 ? ; < Checksum
ImageType UINT8 ? ; < Type
V_Reserved UINT8 ? ; < Reserved
AMD_IMAGE_HEADER ENDS
; AGESA Binary module header structure
AMD_MODULE_HEADER STRUCT
ModuleHeaderSignature UINT32 ? ; < Module signature
ModuleIdentifier CHAR8 (8) DUP (?) ; < 8 characters ID
ModuleVersion CHAR8 (12) DUP (?) ; < 12 characters version
ModuleDispatcher POINTER ? ; < A pointer point to dispatcher
NextBlock POINTER ? ; < Next module header link
AMD_MODULE_HEADER ENDS
; AMD_CODE_HEADER Signatures.
AGESA_CODE_SIGNATURE TEXTEQU <'!', '!', 'A', 'G', 'E', 'S', 'A', ' '>
CIMXNB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'N', 'B'>
CIMXSB_CODE_SIGNATURE TEXTEQU <'!', '!', 'C', 'I', 'M', 'X', 'S', 'B'>
; AGESA_CODE_SIGNATURE
AMD_CODE_HEADER STRUCT
Signature CHAR8 (8) DUP (?) ; < code header Signature
ComponentName CHAR8 (8) DUP (?) ; < 8 character name of the code module
Version CHAR8 (12) DUP (?) ; < 12 character version string
TerminatorNull CHAR8 ? ; < null terminated string
VerReserved CHAR8 (7) DUP (?) ; < reserved space
AMD_CODE_HEADER ENDS
; Extended PCI address format
EXT_PCI_ADDR STRUCT
Register UINT32 ?
; IN OUT UINT32 Register:12; ; < Register offset
; IN OUT UINT32 Function:3; ; < Function number
; IN OUT UINT32 Device:5; ; < Device number
; IN OUT UINT32 Bus:8; ; < Bus number
; IN OUT UINT32 Segment:4; ; < Segment
EXT_PCI_ADDR ENDS
; Union type for PCI address
PCI_ADDR UNION
AddressValue UINT32 ? ; < Formal address
Address EXT_PCI_ADDR {} ; < Extended address
PCI_ADDR ENDS
; SBDFO - Segment Bus Device Function Offset
; 31:28 Segment (4-bits)
; 27:20 Bus (8-bits)
; 19:15 Device (5-bits)
; 14:12 Function(3-bits)
; 11:00 Offset (12-bits)
ILLEGAL_SBDFO EQU 0FFFFFFFFh
; CPUID data received registers format
CPUID_DATA STRUCT
EAX_Reg UINT32 ? ; < CPUID instruction result in EAX
EBX_Reg UINT32 ? ; < CPUID instruction result in EBX
ECX_Reg UINT32 ? ; < CPUID instruction result in ECX
EDX_Reg UINT32 ? ; < CPUID instruction result in EDX
CPUID_DATA ENDS
; HT frequency for external callbacks
;typedef enum {
HT_FREQUENCY_200M EQU 0 ; < HT speed 200 for external callbacks
HT_FREQUENCY_400M EQU 2 ; < HT speed 400 for external callbacks
HT_FREQUENCY_600M EQU 4 ; < HT speed 600 for external callbacks
HT_FREQUENCY_800M EQU 5 ; < HT speed 800 for external callbacks
HT_FREQUENCY_1000M EQU 6 ; < HT speed 1000 for external callbacks
HT_FREQUENCY_1200M EQU 7 ; < HT speed 1200 for external callbacks
HT_FREQUENCY_1400M EQU 8 ; < HT speed 1400 for external callbacks
HT_FREQUENCY_1600M EQU 9 ; < HT speed 1600 for external callbacks
HT_FREQUENCY_1800M EQU 10 ; < HT speed 1800 for external callbacks
HT_FREQUENCY_2000M EQU 11 ; < HT speed 2000 for external callbacks
HT_FREQUENCY_2200M EQU 12 ; < HT speed 2200 for external callbacks
HT_FREQUENCY_2400M EQU 13 ; < HT speed 2400 for external callbacks
HT_FREQUENCY_2600M EQU 14 ; < HT speed 2600 for external callbacks
HT_FREQUENCY_2800M EQU 17 ; < HT speed 2800 for external callbacks
HT_FREQUENCY_3000M EQU 18 ; < HT speed 3000 for external callbacks
HT_FREQUENCY_3200M EQU 19 ; < HT speed 3200 for external callbacks
HT_FREQUENCY_MAX EQU 20 ; < Limit Check.
HT_FREQUENCIES TEXTEQU <DWORD> ;} HT_FREQUENCIES;
HT3_FREQUENCY_MIN EQU HT_FREQUENCY_1200M
IFNDEF BIT0
BIT0 EQU 0000000000000001h
ENDIF
IFNDEF BIT1
BIT1 EQU 0000000000000002h
ENDIF
IFNDEF BIT2
BIT2 EQU 0000000000000004h
ENDIF
IFNDEF BIT3
BIT3 EQU 0000000000000008h
ENDIF
IFNDEF BIT4
BIT4 EQU 0000000000000010h
ENDIF
IFNDEF BIT5
BIT5 EQU 0000000000000020h
ENDIF
IFNDEF BIT6
BIT6 EQU 0000000000000040h
ENDIF
IFNDEF BIT7
BIT7 EQU 0000000000000080h
ENDIF
IFNDEF BIT8
BIT8 EQU 0000000000000100h
ENDIF
IFNDEF BIT9
BIT9 EQU 0000000000000200h
ENDIF
IFNDEF BIT10
BIT10 EQU 0000000000000400h
ENDIF
IFNDEF BIT11
BIT11 EQU 0000000000000800h
ENDIF
IFNDEF BIT12
BIT12 EQU 0000000000001000h
ENDIF
IFNDEF BIT13
BIT13 EQU 0000000000002000h
ENDIF
IFNDEF BIT14
BIT14 EQU 0000000000004000h
ENDIF
IFNDEF BIT15
BIT15 EQU 0000000000008000h
ENDIF
IFNDEF BIT16
BIT16 EQU 0000000000010000h
ENDIF
IFNDEF BIT17
BIT17 EQU 0000000000020000h
ENDIF
IFNDEF BIT18
BIT18 EQU 0000000000040000h
ENDIF
IFNDEF BIT19
BIT19 EQU 0000000000080000h
ENDIF
IFNDEF BIT20
BIT20 EQU 0000000000100000h
ENDIF
IFNDEF BIT21
BIT21 EQU 0000000000200000h
ENDIF
IFNDEF BIT22
BIT22 EQU 0000000000400000h
ENDIF
IFNDEF BIT23
BIT23 EQU 0000000000800000h
ENDIF
IFNDEF BIT24
BIT24 EQU 0000000001000000h
ENDIF
IFNDEF BIT25
BIT25 EQU 0000000002000000h
ENDIF
IFNDEF BIT26
BIT26 EQU 0000000004000000h
ENDIF
IFNDEF BIT27
BIT27 EQU 0000000008000000h
ENDIF
IFNDEF BIT28
BIT28 EQU 0000000010000000h
ENDIF
IFNDEF BIT29
BIT29 EQU 0000000020000000h
ENDIF
IFNDEF BIT30
BIT30 EQU 0000000040000000h
ENDIF
IFNDEF BIT31
BIT31 EQU 0000000080000000h
ENDIF
IFNDEF BIT32
BIT32 EQU 0000000100000000h
ENDIF
IFNDEF BIT33
BIT33 EQU 0000000200000000h
ENDIF
IFNDEF BIT34
BIT34 EQU 0000000400000000h
ENDIF
IFNDEF BIT35
BIT35 EQU 0000000800000000h
ENDIF
IFNDEF BIT36
BIT36 EQU 0000001000000000h
ENDIF
IFNDEF BIT37
BIT37 EQU 0000002000000000h
ENDIF
IFNDEF BIT38
BIT38 EQU 0000004000000000h
ENDIF
IFNDEF BIT39
BIT39 EQU 0000008000000000h
ENDIF
IFNDEF BIT40
BIT40 EQU 0000010000000000h
ENDIF
IFNDEF BIT41
BIT41 EQU 0000020000000000h
ENDIF
IFNDEF BIT42
BIT42 EQU 0000040000000000h
ENDIF
IFNDEF BIT43
BIT43 EQU 0000080000000000h
ENDIF
IFNDEF BIT44
BIT44 EQU 0000100000000000h
ENDIF
IFNDEF BIT45
BIT45 EQU 0000200000000000h
ENDIF
IFNDEF BIT46
BIT46 EQU 0000400000000000h
ENDIF
IFNDEF BIT47
BIT47 EQU 0000800000000000h
ENDIF
IFNDEF BIT48
BIT48 EQU 0001000000000000h
ENDIF
IFNDEF BIT49
BIT49 EQU 0002000000000000h
ENDIF
IFNDEF BIT50
BIT50 EQU 0004000000000000h
ENDIF
IFNDEF BIT51
BIT51 EQU 0008000000000000h
ENDIF
IFNDEF BIT52
BIT52 EQU 0010000000000000h
ENDIF
IFNDEF BIT53
BIT53 EQU 0020000000000000h
ENDIF
IFNDEF BIT54
BIT54 EQU 0040000000000000h
ENDIF
IFNDEF BIT55
BIT55 EQU 0080000000000000h
ENDIF
IFNDEF BIT56
BIT56 EQU 0100000000000000h
ENDIF
IFNDEF BIT57
BIT57 EQU 0200000000000000h
ENDIF
IFNDEF BIT58
BIT58 EQU 0400000000000000h
ENDIF
IFNDEF BIT59
BIT59 EQU 0800000000000000h
ENDIF
IFNDEF BIT60
BIT60 EQU 1000000000000000h
ENDIF
IFNDEF BIT61
BIT61 EQU 2000000000000000h
ENDIF
IFNDEF BIT62
BIT62 EQU 4000000000000000h
ENDIF
IFNDEF BIT63
BIT63 EQU 8000000000000000h
ENDIF

576
src/vendorcode/amd/agesa/f12/Legacy/bridge32.inc Executable file
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@ -0,0 +1,576 @@
; ****************************************************************************
; *
; * @file
; *
; * Agesa structures and definitions
; *
; * Contains AMD AGESA core interface
; *
; * @xrefitem bom "File Content Label" "Release Content"
; * @e project: AGESA
; * @e sub-project: Include
; * @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
;
; ****************************************************************************
;
; Copyright (c) 2011, Advanced Micro Devices, Inc.
; All rights reserved.
;
; Redistribution and use in source and binary forms, with or without
; modification, are permitted provided that the following conditions are met:
; * Redistributions of source code must retain the above copyright
; notice, this list of conditions and the following disclaimer.
; * Redistributions in binary form must reproduce the above copyright
; notice, this list of conditions and the following disclaimer in the
; documentation and/or other materials provided with the distribution.
; * Neither the name of Advanced Micro Devices, Inc. nor the names of
; its contributors may be used to endorse or promote products derived
; from this software without specific prior written permission.
;
; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
; DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
; DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
; ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
;*****************************************************************************
PARAM1 textequ <[bp+8]>
PARAM2 textequ <[bp+12]>
PARAM3 textequ <[bp+16]>
RETAddress textequ <[bp+4]>
AMD_PRIVATE_PARAMS STRUCT
Gate16_CS DW ? ; Segment of AMD_BRIDGE_32 and AMD_CALLOUT_16
Gate16_SS DW ? ; RM stack segment
Router_Seg DW ? ; Segment of oem router
Router_Off DW ? ; Offset of oem router
AMD_PRIVATE_PARAMS ENDS
; OEM may pre-define the GDT and selector offsets. If they do not, use our defaults.
IFNDEF AGESA_SELECTOR_GDT
AGESA_SELECTOR_GDT EQU 00h
ENDIF
IFNDEF AGESA_SELECTOR_CODE16
AGESA_SELECTOR_CODE16 EQU 08h
ENDIF
IFNDEF AGESA_SELECTOR_DATA16
AGESA_SELECTOR_DATA16 EQU 10h
ENDIF
IFNDEF AGESA_SELECTOR_CODE32
AGESA_SELECTOR_CODE32 EQU 18h
ENDIF
IFNDEF AGESA_SELECTOR_DATA32
AGESA_SELECTOR_DATA32 EQU 20h
ENDIF
AMD_BRIDGE_32_GDT MACRO GDT_Name:REQ
GDT_Name LABEL BYTE
DD 000000000h, 000000000h ; NULL descriptor
DD 00000ffffh, 000009b00h ; 16-bit code, fixed up
DD 00000ffffh, 000009300h ; 16-bit data, fixed up
DD 00000ffffh, 000CF9B00h ; 32-bit protected mode code
DD 00000ffffh, 000CF9300h ; 32-bit protected mode data
GDT_Length EQU ($-GDT_Name)
ENDM
;+-------------------------------------------------------------------------
;
; AMD_BRIDGE_32 - Execute Agesa through Pushhigh interface
;
; Processing:
; The following steps are taken:
; 1) Enter 32bit Protected Mode (PM32)
; 2) Run AGESA code
; 3) Restore Real Mode (RM)
;
; Entry:
; [big real mode] : ds, es set to base 0 limit 4G segment
; EDX - if not 0, provides a FAR PTR to oem router (Seg | Offset)
; ESI - configuration block pointer
;
; Exit:
; EAX - return value
; ESI - configuration block pointer
; ds, es, fs, gs - Set to 4GB segment limit for Big Real Mode
;
; Modified:
; None
;
AMD_BRIDGE_32 MACRO GDT_Name
local copyGDT
local flushTo16PM
local agesaReturnAddress
local leave32bitPM
local flush2RM
push gs
push fs
push ebx
push ecx
push edi
mov eax, esp
push eax
movzx esp, sp
;
; Do not use any locals here, BP will be changed frequently during RM->PM32->RM
;
pushf
cli ; Disable interrupts during AGESA
cld ; Need known direction flag during AGESA
;
; Save the FAR PTR input parameter
;
mov gs, dx ; Offset
shr edx, 16
mov fs, dx ; Segment
;
; Determine where our binary file is and get entry point
;
mov edx, (AMD_CONFIG_PARAMS PTR [esi]).ImageBasePtr
add edx, (AMD_IMAGE_HEADER PTR [edx]).EntryPointAddress
;
; Figure out the return address we will use after calling AGESA
; and store it in ebx until we have our stack set up properly
;
mov ebx, cs
shl ebx, 4
add ebx, OFFSET agesaReturnAddress
;
; Save our current RM stack AND entry EBP
;
push ebp
; push esp
push ss
;
; BEGIN --- STACK MUST BE BALANCED AT THIS POINT --- BEGIN
;
; Copy the GDT onto the stack for modification
;
mov cx, GDT_Length
sub sp, cx
mov bp, sp
lea di, GDT_Name
copyGDT:
mov al, cs:[di]
mov [bp], al
inc di
inc bp
loop copyGDT
;
; Patch 16-bit code and data descriptors on stack. We will
; fix up CS and SS for PM16 during the callout if applicable.
;
mov bp, sp
mov eax, cs
shl eax, 4
mov [bp+AGESA_SELECTOR_CODE16+2], ax
shr eax, 16
mov [bp+AGESA_SELECTOR_CODE16+4], al
mov eax, ss
shl eax, 4
mov [bp+AGESA_SELECTOR_DATA16+2], ax
shr eax, 16
mov [bp+AGESA_SELECTOR_DATA16+4], al
;
; Need to place Length and Address on GDT
;
mov eax, ss
shl eax, 4
add eax, esp
push eax
push WORD PTR (GDT_Length-1)
;
; Load the GDT
;
mov bp, sp
lgdt FWORD PTR [bp]
;
; TABLE 1
;
; Place PRIVATE DATA on stack DIRECTLY following GDT
; During this routine, stack data is critical. If
; order is changed or additional added, bad things
; will happen!
;
; HIGHEST PHYSICAL ADDRESS
;
; | ... |
; ------------------------
; | old RM SP |
; | old RM SS |
; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS + (SIZEOF GDT_LENGTH + 6 {size, address})
; | GDT_DATA32 |
; | ... |
; | GDT_NULL |
; | GDT Addr, Length |
; ------------------------ sp + SIZEOF AMD_PRIVATE_PARAMS
; | Priv.Gate16_SS |
; | Priv.Gate16_CS |
; ------------------------ sp
; ------ THEN PUSH -------
; | Return to 16-bit CS |
; | Return to 16-bit Off |
; | ... |
;
; LOWEST PHYSICAL ADDRESS
;
mov edi, esp
sub edi, SIZEOF AMD_PRIVATE_PARAMS
mov ax, cs
mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS, ax
mov ax, ss
mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS, ax
mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off, gs
mov (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg, fs
mov esp, edi
;
; Save an address for returning to 16 bit real mode on stack,
; we'll use it in a far ret after turning off CR0.PE so that
; we can take our address off and force a far jump. Be sure
; no unexpected data is on the stack after this!
;
mov ax, cs
push cs
lea ax, flush2RM
push ax
;
; Convert ss:esp to "flat"
;
mov ax, sp
push ax
mov eax, ss
shl eax, 4
add eax, esp
mov esp, eax ; Load the zero based ESP
;
; Set CR0.PE
;
mov eax, CR0 ; Get CPU control word 0
or al, 01 ; Enable CPU protected mode
mov CR0, eax ; Write back to CPU control word 0
jmp flushTo16PM
flushTo16PM:
;
; 16-bit protected mode
;
mov ax, AGESA_SELECTOR_DATA32
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
mov ss, ax
;
; Push our parameters RIGHT TO LEFT, and then return address
;
push esi ; AGESA configuration block pointer (data)
push ebx ; after AGESA return offset (32PM flat) - consumed by dispatcher ret
pushd AGESA_SELECTOR_CODE32 ; AGESA entry selector (32PM flat)
push edx ; AGESA entry point (32PM flat)
DB 066h
retf ; <><><> Enter AGESA 32-bit code!!! <><><>
agesaReturnAddress:
;
; Returns from the Agesa 32-bit code still PM32
;
DB 0EAh
DD OFFSET leave32bitPM
DW AGESA_SELECTOR_CODE16
leave32bitPM:
;
; Now in 16-bit PM
;
add esp, 4 ; +4 to remove our config block pointer
;
; Eax reserve AGESA_STATUS return code, save it
;
mov ebx, eax
;
; Turn off CR0.PE, restore 64K stack limit
;
pop ax
mov sp, ax
mov ax, AGESA_SELECTOR_DATA16
mov ss, ax
mov eax, CR0
and al, NOT 1 ; Disable protected mode
mov CR0, eax ; Write back CR0.PE
;
; Jump far to enter RM, we saved this address on the stack
; already. Hopefully stack is balanced through AGESA
; nor were any params added by pushing them on the stack and
; not removing them between BEGIN-END comments.
;
retf
flush2RM:
;
; Set segments registers for big real mode before returning
;
xor ax, ax
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
;
; Discard GDT, +6 for GDT pointer/size, privates
;
add esp, GDT_Length + 6 + SIZEOF AMD_PRIVATE_PARAMS
;
; Restore real mode stack and entry EBP
;
pop cx
; mov esp, [esp]
mov ss, cx
pop ebp
;
; Restore AGESA_STATUS return code to eax
;
mov eax, ebx
;
; END --- STACK MUST BE BALANCED TO THIS POINT --- END
;
popf
pop ebx
mov esp, ebx
pop edi
pop ecx
pop ebx
pop fs
pop gs
; EXIT AMD_BRIDGE_32
ENDM
;+-------------------------------------------------------------------------
;
; AMD_CALLOUT_16 - Execute Callback from Pushhigh interface
;
; Processing:
; The following steps are taken:
; 1) Enter PM16
; 2) Setup stack, get private params
; 3) Enter RM
; 4) Get 3 params
; 5) Call oemCallout OR oem router
; 6) Enter PM32
; 7) Return to Agesa PH
;
; Entry:
; [32-bit protected mode]
; [esp+8] Func
; [esp+12] Data
; [esp+16] Configuration Block
; [esp+4] return address to Agesa
;
; Exit:
; [32-bit protected mode]
;
; Modified:
; None
;
AMD_CALLOUT_16 MACRO LocalOemCalloutRouter
;
; Note that we are still PM32, so MASM may work strangely
;
push bp ; Save our original SP to access params
mov bp, sp
push bx
push si
push di
push cx
push dx
push di
DB 066h, 0EAh
DW OFFSET PM16Entry
DW AGESA_SELECTOR_CODE16
PM16Entry:
;
; PM16 CS, but still PM32 SS, as we need to access our private params
; before we enter RM.
;
; Note: we are working below the stack temporarily, and and it will
; not affect our ability to get entry params
;
xor ecx, ecx
xor edx, edx
;
; SGDT will give us the original location of the GDT on our CAS stack.
; We need this value because our private parameters are located just
; below the GDT.
;
mov edi, esp
sub edi, GDT_Length + 6
sgdt FWORD PTR [edi] ; [edi] = word size, dword address
mov edi, DWORD PTR [edi+2] ; Get the PM32 address only
sub edi, SIZEOF AMD_PRIVATE_PARAMS + 6
;
; cx = code segment of this code in RM
; dx = stack segment of CAS in RM
; fs = code segment of oem router (save for later)
; gs = offset of oem router (save for later)
; fs and gs are loaded after switch to real mode because we can't
; use them as scratch pad registers in protected mode
;
mov cx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_CS
mov dx, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Gate16_SS
mov eax, edi ; Save edi in eax for after RM switch
mov edi, esp ; Save our current ESP for RM
movzx ebx, dx
shl ebx, 4
sub esp, ebx
;
; We had been accessing the stack in PM32, we will now change to PM16 so we
; will make the stack segment 64KB limit so SP needs to be fixed made PM16
; compatible.
;
mov bx, AGESA_SELECTOR_DATA16
mov ss, bx
;
; Save the RM segment and RM offset of the jump we will need to make in
; order to enter RM so that code in this segment is relocatable.
;
; BEGIN --- Don't unbalance the stack --- BEGIN
;
push cx
pushw OFFSET RMEntry
mov ebx, CR0
and bl, NOT 1
mov CR0, ebx ; CR0.PE cleared
;
; Far jump to clear segment descriptor cache and enter RM
;
retf
RMEntry:
;
; We are in RM, setup RM stack
;
movzx ebx, dx ; Get RM SS in ebx
shl ebx, 4 ; Get our stack top on entry in EBP to
sub ebp, ebx ; access our entry parameters
sub eax, ebx ; save copy of parameters address
mov ss, dx ; Set stack segment
;
; We are going to figure out the address to use when we return
; and have to go back into PM32 while we have access to it
;
movzx ebx, cx ; Get original CS in ebx
shl ebx, 4
add ebx, OFFSET PM32Entry
;
; Now we put our data, func, block params into calling convention
; for our hook
;
; ECX = Func
; EDX = Data
; ESI = config pointer
;
mov ecx, PARAM1 ; Func
mov edx, PARAM2 ; Data
mov esi, PARAM3 ; pointer
push ebx ; Save PM32 mode switch address
push edi ; Save PM32 stack pointer
pushf
;
; Get Router Function Address
;
mov edi, eax
mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Seg
mov fs, ax
mov ax, (AMD_PRIVATE_PARAMS PTR ss:[edi]).Router_Off
mov gs, ax
mov eax, AGESA_UNSUPPORTED ; Default return value
;
; If AMD_BRIDGE_32 EDX == 0 call oemCallout
; otherwise call FAR PTR EDX
;
; Critical:
; sp+2 - EDI aka PM32 stack address
; sp+4 - address of PM32Entry in PM32
;
mov bx, fs
shl ebx, 16
mov bx, gs
.if (ebx == 0)
call LocalOemCalloutRouter
.else
;
; Make far call to Router function
;
push cs
push offset CalloutReturn
push ebx
retf
CalloutReturn:
.endif
;
; Restore PM32 esp from RM stack
;
popf
pop edi ; Our PM32 stack pointer
pop edx ; Our PM32 mode switch address
mov ebx, CR0
or bl, 1 ; CR0.PE set
mov CR0, ebx
mov ebx, AGESA_SELECTOR_DATA32
pushd AGESA_SELECTOR_CODE32 ; PM32 selector
push edx ; PM32 entry point
DB 066h
retf ; Far jump to enter PM32
PM32Entry:
;
; END --- Don't unbalance the stack --- END
; We are now PM32, so remember MASM is assembling in 16-bit again
;
mov ss, bx
mov ds, bx
mov es, bx
mov fs, bx
mov gs, bx
mov sp, di
pop di
pop dx
pop cx
pop di
pop si
pop bx
pop bp
; EXIT AMD_CALLOUT_16
ENDM

1340
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/* $NoKeywords:$ */
/**
* @file
*
* AMD Library
*
* Contains interface to the AMD AGESA library
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Lib
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
**/
#ifndef _AMD_LIB_H_
#define _AMD_LIB_H_
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
#define IOCF8 0xCF8
#define IOCFC 0xCFC
// Reg Values for ReadCpuReg and WriteCpuReg
#define CR0_REG 0x00
#define CR4_REG 0x04
#define DR0_REG 0x10
#define DR1_REG 0x11
#define DR2_REG 0x12
#define DR3_REG 0x13
#define DR7_REG 0x17
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
#if !defined __GNUC__
// PROTOTYPES FOR amdlib32.asm
void _mm_stream_si128_fs (void *__A, void *__B);
void _mm_store_si128_fs (void *dest, void *data);
void _mm_clflush_fs (void *address32);
#endif
/*---------------------------------------------------------------------------------------
* L O C A L F U N C T I O N S
*---------------------------------------------------------------------------------------
*/
UINT8
ReadIo8 (
IN UINT16 Address
);
UINT16
ReadIo16 (
IN UINT16 Address
);
UINT32
ReadIo32 (
IN UINT16 Address
);
VOID
WriteIo8 (
IN UINT16 Address,
IN UINT8 Data
);
VOID
WriteIo16 (
IN UINT16 Address,
IN UINT16 Data
);
VOID
WriteIo32 (
IN UINT16 Address,
IN UINT32 Data
);
UINT8
Read64Mem8 (
IN UINT64 Address
);
UINT16
Read64Mem16 (
IN UINT64 Address
);
UINT32
Read64Mem32 (
IN UINT64 Address
);
VOID
Write64Mem8 (
IN UINT64 Address,
IN UINT8 Data
);
VOID
Write64Mem16 (
IN UINT64 Address,
IN UINT16 Data
);
VOID
Write64Mem32 (
IN UINT64 Address,
IN UINT32 Data
);
UINT64
ReadTSC (
VOID
);
// MSR
VOID
LibAmdMsrRead (
IN UINT32 MsrAddress,
OUT UINT64 *Value,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
LibAmdMsrWrite (
IN UINT32 MsrAddress,
IN UINT64 *Value,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
// IO
VOID
LibAmdIoRead (
IN ACCESS_WIDTH AccessWidth,
IN UINT16 IoAddress,
OUT VOID *Value,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
LibAmdIoWrite (
IN ACCESS_WIDTH AccessWidth,
IN UINT16 IoAddress,
IN VOID *Value,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
LibAmdIoRMW (
IN ACCESS_WIDTH AccessWidth,
IN UINT16 IoAddress,
IN VOID *Data,
IN VOID *DataMask,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
LibAmdIoPoll (
IN ACCESS_WIDTH AccessWidth,
IN UINT16 IoAddress,
IN VOID *Data,
IN VOID *DataMask,
IN UINT64 Delay,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
// Memory or MMIO
VOID
LibAmdMemRead (
IN ACCESS_WIDTH AccessWidth,
IN UINT64 MemAddress,
OUT VOID *Value,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
LibAmdMemWrite (
IN ACCESS_WIDTH AccessWidth,
IN UINT64 MemAddress,
IN VOID *Value,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
LibAmdMemRMW (
IN ACCESS_WIDTH AccessWidth,
IN UINT64 MemAddress,
IN VOID *Data,
IN VOID *DataMask,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
LibAmdMemPoll (
IN ACCESS_WIDTH AccessWidth,
IN UINT64 MemAddress,
IN VOID *Data,
IN VOID *DataMask,
IN UINT64 Delay,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
// PCI
VOID
LibAmdPciRead (
IN ACCESS_WIDTH AccessWidth,
IN PCI_ADDR PciAddress,
OUT VOID *Value,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
LibAmdPciWrite (
IN ACCESS_WIDTH AccessWidth,
IN PCI_ADDR PciAddress,
IN VOID *Value,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
LibAmdPciRMW (
IN ACCESS_WIDTH AccessWidth,
IN PCI_ADDR PciAddress,
IN VOID *Data,
IN VOID *DataMask,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
LibAmdPciPoll (
IN ACCESS_WIDTH AccessWidth,
IN PCI_ADDR PciAddress,
IN VOID *Data,
IN VOID *DataMask,
IN UINT64 Delay,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
LibAmdPciReadBits (
IN PCI_ADDR Address,
IN UINT8 Highbit,
IN UINT8 Lowbit,
OUT UINT32 *Value,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
LibAmdPciWriteBits (
IN PCI_ADDR Address,
IN UINT8 Highbit,
IN UINT8 Lowbit,
IN UINT32 *Value,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
LibAmdPciFindNextCap (
IN OUT PCI_ADDR *Address,
IN AMD_CONFIG_PARAMS *StdHeader
);
// CPUID
VOID
LibAmdCpuidRead (
IN UINT32 CpuidFcnAddress,
OUT CPUID_DATA *Value,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
// Utility Functions
VOID
LibAmdMemFill (
IN VOID *Destination,
IN UINT8 Value,
IN UINTN FillLength,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID
LibAmdMemCopy (
IN VOID *Destination,
IN VOID *Source,
IN UINTN CopyLength,
IN OUT AMD_CONFIG_PARAMS *StdHeader
);
VOID *
LibAmdLocateImage (
IN VOID *StartAddress,
IN VOID *EndAddress,
IN UINT32 Alignment,
IN CHAR8 ModuleSignature[8]
);
UINT32
LibAmdGetPackageType (
IN AMD_CONFIG_PARAMS *StdHeader
);
BOOLEAN
LibAmdVerifyImageChecksum (
IN VOID *ImagePtr
);
UINT8
LibAmdBitScanReverse (
IN UINT32 value
);
UINT8
LibAmdBitScanForward (
IN UINT32 value
);
VOID
LibAmdReadCpuReg (
IN UINT8 RegNum,
OUT UINT32 *Value
);
VOID
LibAmdWriteCpuReg (
IN UINT8 RegNum,
IN UINT32 Value
);
VOID
LibAmdWriteBackInvalidateCache (
IN VOID
);
VOID
LibAmdSimNowEnterDebugger (VOID);
VOID
LibAmdHDTBreakPoint (VOID);
UINT8
LibAmdAccessWidth (
IN ACCESS_WIDTH AccessWidth
);
VOID
LibAmdCLFlush (
IN UINT64 Address,
IN UINT8 Count
);
VOID F10RevDProbeFilterCritical (
IN PCI_ADDR PciAddress,
IN UINT32 PciRegister
);
VOID
IdsOutPort (
IN UINT32 Addr,
IN UINT32 Value,
IN UINT32 Flag
);
VOID
StopHere (
VOID
);
VOID
CpuidRead (
IN UINT32 CpuidFcnAddress,
OUT CPUID_DATA *Value
);
UINT8
ReadNumberOfCpuCores(
VOID
);
#endif // _AMD_LIB_H_

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/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
// helper.c - these functions are compiled separately because they redefine
// functions invoked directly by the compiler code generator.
// The Microsoft tools do not allow such functions to be compiled
// with the "Enable link-time code generation (/GL)" option. Compile
// this module without /GL to avoid a build failure LNK1237.
//
#if defined (_MSC_VER)
#include "Porting.h"
//---------------------------------------------------------------------------
void *memcpy (void *dest, const void *src, size_t bytes)
{
// Rep movsb is faster than a byte loop, but still quite slow
// for large operations. However, it is a good choice here because
// this function is intended for use by the compiler only. For
// large copy operations, call LibAmdMemCopy.
__movsb (dest, src, bytes);
return dest;
}
//---------------------------------------------------------------------------
void *memset (void *dest, int value, size_t bytes)
{
// Rep stosb is faster than a byte loop, but still quite slow
// for large operations. However, it is a good choice here because
// this function is intended for use by the compiler only. For
// large fill operations, call LibAmdMemFill.
__stosb (dest, value, bytes);
return dest;
}
//---------------------------------------------------------------------------
#endif

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src/vendorcode/amd/agesa/f12/MainPage.h Executable file
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/* $NoKeywords:$ */
/**
* @file
*
* Create outline and references for mainpage documentation.
*
* Design guides, maintenance guides, and general documentation, are
* collected using this file onto the documentation mainpage.
* This file contains doxygen comment blocks, only.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Documentation
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/**
* @mainpage
*
* The design and maintenance documentation for AGESA Sample Code is organized as
* follows. On this page, you can reference design guides, maintenance guides, and
* general documentation. Detailed Data Structure, Function, and Interface documentation
* may be found using the Data Structures or Files tabs. See Related Pages for a
* Release content summary, and, if this is not a production release, lists of To Do's,
* Deprecated items, etc.
*
* @subpage starthere "Start Here - Initial Porting and Integration."
*
* @subpage optionmain "Build Configuration and Options Guides and Documentation."
*
* @subpage commonmain "Processor Common Component Guides and Documentation."
*
* @subpage cpumain "CPU Component Guides and Documentation."
*
* @subpage htmain "HT Component Guides and Documentation."
*
* @subpage memmain "MEM Component Guides and Documentation."
*
* @subpage gnbmain "GNB Component Documentation."
*
* @subpage idsmain "IDS Component Guides and Documentation."
*
* @subpage recoverymain "Recovery Component Guides and Documentation."
*
*/
/**
* @page starthere Initial Porting and Integration
*
* @par Basic Check List
*
* <ul>
* <li> Copy the \<plat\>Options.c file from the Addendum directory to the platform tip build directory.
* AMD recommends the use of a sub-directory named AGESA to contain these files and the build output files.
* <li> Copy the OptionsIds.h content in the spec to OptionsIds.h in the platform build tip directory
* and make changes to enable the IDS support desired. It is highly recommended to set the following for
* initial integration and development:@n
* @code
* #define IDSOPT_IDS_ENABLED TRUE
* #define IDSOPT_ERROR_TRAP_ENABLED TRUE
* #define IDSOPT_ASSERT_ENABLED TRUE
* @endcode
* <li> Edit and modify the option selections in those two files to meet the needs of the specific platform.
* <li> Set the environment variable AGESA_ROOT to the root folder of the AGESA code.
* <li> Set the environment variable AGESA_OptsDir the platform build tip AGESA directory.
* <li> Generate the doxygen documentation or locate the file arch2008.chm within your AGESA release package.
* </ul>
*
* @par Debugging Using ASSERT and IDS_ERROR_TRAP
*
* While AGESA code uses ::ASSERT and ::IDS_ERROR_TRAP to check for internal errors, these macros can also
* catch and assist debug of wrapper and platform BIOS issues.
*
* When an ::ASSERT fails or an ::IDS_ERROR_TRAP is executed, the AGESA code will enter a halt loop and display a
* Stop Code. A Stop Code is eight hex digits. The first (most significant) four are the FILECODE.
* FILECODEs can be looked up in Filecode.h to determine which file contains the stop macro. Each file has a
* unique code value.
* The least significant digits are the line number in that file.
* For example, 0210 means the macro is on line two hundred ten.
* (see ::IdsErrorStop for more details on stop code display.)
*
* Enabling ::ASSERT and ::IDS_ERROR_TRAP ensure errors are caught and also provide a useful debug assist.
* Comments near each macro use will describe the nature of the error and typical wrapper errors or other
* root causes.
*
* After your wrapper consistently executes ::ASSERT and ::IDS_ERROR_TRAP stop free, you can disable them in
* OptionsIds.h, except for regression testing. IDS is not expected to be enabled in production BIOS builds.
*
*/

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src/vendorcode/amd/agesa/f12/Makefile.inc Executable file
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#*****************************************************************************
#
# Copyright (c) 2011, Advanced Micro Devices, Inc.
# All rights reserved.
#
# Redistribution and use in source and binary forms, with or without
# modification, are permitted provided that the following conditions are met:
# * Redistributions of source code must retain the above copyright
# notice, this list of conditions and the following disclaimer.
# * Redistributions in binary form must reproduce the above copyright
# notice, this list of conditions and the following disclaimer in the
# documentation and/or other materials provided with the distribution.
# * Neither the name of Advanced Micro Devices, Inc. nor the names of
# its contributors may be used to endorse or promote products derived
# from this software without specific prior written permission.
#
# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
# ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
# WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
# DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
# DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
# (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
# LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
# ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
# SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
#
#*****************************************************************************
# AGESA V5 Files
AGESA_ROOT = src/vendorcode/amd/agesa/f12
AGESA_INC = -Isrc/mainboard/$(MAINBOARDDIR)
AGESA_INC += -I$(AGESA_ROOT)
AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU
AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family
AGESA_INC += -I$(AGESA_ROOT)/Include
AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS
AGESA_INC += -I$(AGESA_ROOT)/Lib
AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Feature
AGESA_INC += -I$(AGESA_ROOT)/Proc/Common
AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem
AGESA_INC += -I$(AGESA_ROOT)/Proc/Recovery/CPU
AGESA_INC += -I$(AGESA_ROOT)/Proc/CPU/Family/0x12
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Nb
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Common
AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Family/0x12
AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Internal/Family/0x12
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbCommonLib
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Gfx
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Gfx/Family
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxConfig
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbGfxInitLibV1
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbSbLib
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieConfig
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbNbInitLibV1
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Nb/Family/LN
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbCableSafe
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieInitLibV1
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieAlibV1
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Modules/GnbPcieTrainingV1
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Nb/Family
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/Nb/Feature
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/PCIe/Family
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/PCIe
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/PCIe/Family/LN
AGESA_INC += -I$(AGESA_ROOT)/Proc/GNB/PCIe/Feature
AGESA_INC += -I$(AGESA_ROOT)/Proc/HT
AGESA_INC += -I$(AGESA_ROOT)/Proc/HT/Fam12
AGESA_INC += -I$(AGESA_ROOT)/Proc/IDS/Control
AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/Feat/CHINTLV
AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/Feat/CSINTLV
AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/Feat/ECC
AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/Feat/IDENDIMM
AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/Feat/INTLVRN
AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/Feat/LVDDR3
AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/Feat/ODTHERMAL
AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/Main
AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/NB/LN
AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/Tech
AGESA_INC += -I$(AGESA_ROOT)/Proc/Mem/Tech/DDR3
AGESA_CFLAGS =-march=k8-sse3 -mtune=k8-sse3 -fno-zero-initialized-in-bss -fno-strict-aliasing
export AGESA_ROOT := $(AGESA_ROOT)
export AGESA_INC := $(AGESA_INC)
export AGESA_CFLAGS := $(AGESA_CFLAGS)
CC := $(CC) $(AGESA_INC) $(AGESA_CFLAGS)
#######################################################################

292
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/* $NoKeywords:$ */
/**
* @file
*
* Describes compiler dependencies - to support several compile time environments
*
* Contains compiler environment porting descriptions
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: Includes
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*/
/*
*****************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
* ***************************************************************************
*
*/
#ifndef _PORTING_H_
#define _PORTING_H_
#if defined (_MSC_VER)
#include <intrin.h>
void _disable (void);
void _enable (void);
#pragma warning(disable: 4103 4001 4733)
#pragma intrinsic (_disable, _enable)
#pragma warning(push)
// -----------------------------------------------------------------------
// Define a code_seg MACRO
//
#define MAKE_AS_A_STRING(arg) #arg
#define CODE_GROUP(arg) __pragma (code_seg (MAKE_AS_A_STRING (.t##arg)))
#define RDATA_GROUP(arg) __pragma (const_seg (MAKE_AS_A_STRING (.d##arg)))
#define FUNC_ATTRIBUTE(arg) __declspec(arg)
//#include <intrin.h> // MS has built-in functions
#if _MSC_VER < 900
// -----------------------------------------------------------------------
// Assume MSVC 1.52C (16-bit)
//
// NOTE: When using MSVC 1.52C use the following command line:
//
// CL.EXE /G3 /AL /O1i /Fa <FILENAME.C>
//
// This will produce 32-bit code in USE16 segment that is optimized for code
// size.
typedef void VOID;
// Create the universal 32, 16, and 8-bit data types
typedef unsigned long UINTN;
typedef long INT32;
typedef unsigned long UINT32;
typedef int INT16;
typedef unsigned int UINT16;
typedef char INT8;
typedef unsigned char UINT8;
typedef char CHAR8;
typedef unsigned short CHAR16;
/// struct for 16-bit environment handling of 64-bit value
typedef struct _UINT64 {
IN OUT UINT32 lo; ///< lower 32-bits of 64-bit value
IN OUT UINT32 hi; ///< highest 32-bits of 64-bit value
} UINT64;
// Create the Boolean type
#define TRUE 1
#define FALSE 0
typedef unsigned char BOOLEAN;
#define CONST const
#define STATIC static
#define VOLATILE volatile
#define CALLCONV __pascal
#define ROMDATA __based( __segname( "_CODE" ) )
#define _16BYTE_ALIGN __declspec(align(16))
// Force tight packing of structures
// Note: Entire AGESA (Project / Solution) will be using pragma pack 1
#pragma warning( disable : 4103 ) // Disable '#pragma pack' in .h warning
#pragma pack(1)
// Disable WORD->BYTE automatic conversion warnings. Example:
// BYTE LocalByte;
// void MyFunc(BYTE val);
//
// MyFunc(LocalByte*2+1); // Warning, automatic conversion
//
// The problem is any time math is performed on a BYTE, it is converted to a
// WORD by MSVC 1.52c, and then when it is converted back to a BYTE, a warning
// is generated. Disable warning C4761
#pragma warning( disable : 4761 )
#else
// -----------------------------------------------------------------------
// Assume a 32-bit MSVC++
//
// Disable the following warnings:
// 4100 - 'identifier' : unreferenced formal parameter
// 4276 - 'function' : no prototype provided; assumed no parameters
// 4214 - non standard extension used : bit field types other than int
// 4001 - nonstandard extension 'single line comment' was used
// 4142 - benign redefinition of type for following declaration
// - typedef char INT8
#if defined (_M_IX86)
#pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306)
#ifndef VOID
typedef void VOID;
#endif
// Create the universal 32, 16, and 8-bit data types
#ifndef UINTN
typedef unsigned __w64 UINTN;
#endif
typedef __int64 INT64;
typedef unsigned __int64 UINT64;
typedef int INT32;
typedef unsigned int UINT32;
typedef short INT16;
typedef unsigned short UINT16;
typedef char INT8;
typedef unsigned char UINT8;
typedef char CHAR8;
typedef unsigned short CHAR16;
// Create the Boolean type
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
typedef unsigned char BOOLEAN;
// Force tight packing of structures
// Note: Entire AGESA (Project / Solution) will be using pragma pack 1
#pragma pack(1)
#define CONST const
#define STATIC static
#define VOLATILE volatile
#define CALLCONV
#define ROMDATA
#define _16BYTE_ALIGN __declspec(align(64))
// 64 bit of compiler
#else
#pragma warning (disable: 4100 4276 4214 4001 4142 4305 4306 4366)
#ifndef VOID
typedef void VOID;
#endif
// Create the universal 32, 16, and 8-bit data types
#ifndef UINTN
typedef unsigned __int64 UINTN;
#endif
typedef __int64 INT64;
typedef unsigned __int64 UINT64;
typedef int INT32;
typedef unsigned int UINT32;
typedef short INT16;
typedef unsigned short UINT16;
typedef char INT8;
typedef unsigned char UINT8;
typedef char CHAR8;
typedef unsigned short CHAR16;
// Create the Boolean type
#ifndef TRUE
#define TRUE 1
#endif
#ifndef FALSE
#define FALSE 0
#endif
typedef unsigned char BOOLEAN;
// Force tight packing of structures
// Note: Entire AGESA (Project / Solution) will be using pragma pack 1
#pragma pack(1)
#define CONST const
#define STATIC static
#define VOLATILE volatile
#define CALLCONV
#define ROMDATA
#endif
#endif
// -----------------------------------------------------------------------
// End of MS compiler versions
#elif defined __GNUC__
#define IN
#define OUT
#define STATIC static
#define VOLATILE volatile
#define TRUE 1
#define FALSE 0
#define CONST const
#define ROMDATA
// #define ROMDATA __attribute__ ((section ("text")))
#define CALLCONV
#define _16BYTE_ALIGN __attribute__ ((aligned (16)))
typedef unsigned char BOOLEAN;
typedef signed char INT8;
typedef signed short INT16;
typedef signed long INT32;
typedef unsigned char CHAR8;
typedef unsigned char UINT8;
typedef unsigned short UINT16;
typedef unsigned long UINT32;
typedef unsigned long UINTN;
typedef unsigned long long UINT64;
typedef void VOID;
//typedef unsigned long size_t;
//typedef unsigned int uintptr_t;
// Force tight packing of structures
// Note: Entire AGESA (Project / Solution) will be using pragma pack 1
#pragma pack(1)
#define CODE_GROUP(arg)
#define RDATA_GROUP(arg)
#define FUNC_ATTRIBUTE(arg) __attribute__((arg))
#define MAKE_AS_A_STRING(arg) #arg
// -----------------------------------------------------------------------
// Common definitions for all compilers
//
#include <stddef.h>
#include "gcc-intrin.h"
#include <assert.h>
#include <console/console.h>
#include <console/loglevel.h>
#ifndef NULL
#define NULL (void *)0
#endif
#else
// -----------------------------------------------------------------------
// Unknown or unsupported compiler
//
#error "Unknown compiler in use"
#endif
// -----------------------------------------------------------------------
// Common definitions for all compilers
//
//Support forward reference construct
#define AGESA_FORWARD_DECLARATION(x) typedef struct _##x x
// The following are use in conformance to the UEFI style guide
#define IN
#define OUT
#endif // _PORTING_H_

117
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10InitEarlyTable.c Executable file
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/* $NoKeywords:$ */
/**
* @file
*
* Initialize the Family 10h specific way of running early initialization.
*
* Returns the table of initialization steps to perform at
* AmdInitEarly.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/FAMILY/0x10
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "cpuFamilyTranslation.h"
#include "Filecode.h"
#include "cpuEarlyInit.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_CPU_FAMILY_0X10_F10INITEARLYTABLE_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
extern F_PERFORM_EARLY_INIT_ON_CORE McaInitializationAtEarly;
extern F_PERFORM_EARLY_INIT_ON_CORE SetRegistersFromTablesAtEarly;
extern F_PERFORM_EARLY_INIT_ON_CORE SetBrandIdRegistersAtEarly;
extern F_PERFORM_EARLY_INIT_ON_CORE LocalApicInitializationAtEarly;
extern F_PERFORM_EARLY_INIT_ON_CORE LoadMicrocodePatchAtEarly;
CONST S_PERFORM_EARLY_INIT_ON_CORE ROMDATA F10EarlyInitOnCoreTable[] =
{
{McaInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION},
{SetRegistersFromTablesAtEarly, PERFORM_EARLY_ANY_CONDITION},
{SetBrandIdRegistersAtEarly, PERFORM_EARLY_ANY_CONDITION},
{LocalApicInitializationAtEarly, PERFORM_EARLY_ANY_CONDITION},
{LoadMicrocodePatchAtEarly, PERFORM_EARLY_WARM_RESET},
{NULL, 0}
};
/*------------------------------------------------------------------------------------*/
/**
* Initializer routine that may be invoked at AmdCpuEarly to return the steps that a
* processor that uses the standard initialization steps should take.
*
* @CpuServiceMethod{::F_GET_EARLY_INIT_TABLE}.
*
* @param[in] FamilyServices The current Family Specific Services.
* @param[out] Table Table of appropriate init steps for the executing core.
* @param[in] EarlyParams Service Interface structure to initialize.
* @param[in] StdHeader Opaque handle to standard config header.
*
*/
VOID
GetF10EarlyInitOnCoreTable (
IN CPU_SPECIFIC_SERVICES *FamilyServices,
OUT CONST S_PERFORM_EARLY_INIT_ON_CORE **Table,
IN AMD_CPU_EARLY_PARAMS *EarlyParams,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
*Table = F10EarlyInitOnCoreTable;
}

292
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10IoCstate.c Executable file
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/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_10 IO C-state feature support functions.
*
* Provides the functions necessary to initialize the IO C-state feature.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F10
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "Ids.h"
#include "cpuFeatures.h"
#include "cpuIoCstate.h"
#include "cpuF10PowerMgmt.h"
#include "cpuLateInit.h"
#include "cpuRegisters.h"
#include "cpuServices.h"
#include "cpuApicUtilities.h"
#include "cpuFamilyTranslation.h"
#include "CommonReturns.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_CPU_FAMILY_0X10_F10IOCSTATE_FILECODE
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
STATIC
F10InitializeIoCstateOnCore (
IN VOID *CstateBaseMsr,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
extern CPU_FAMILY_SUPPORT_TABLE IoCstateFamilyServiceTable;
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Enable IO Cstate on a family 10h CPU.
*
* @param[in] IoCstateServices Pointer to this CPU's IO Cstate family services.
* @param[in] EntryPoint Timepoint designator.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data.
* @param[in] StdHeader Config Handle for library, services.
*
* @return AGESA_SUCCESS Always succeeds.
*
*/
AGESA_STATUS
STATIC
F10InitializeIoCstate (
IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
IN UINT64 EntryPoint,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 LocalMsrRegister;
AP_TASK TaskPtr;
if ((EntryPoint & CPU_FEAT_AFTER_PM_INIT) != 0) {
// Initialize MSRC001_0073[CstateAddr] on each core to a region of
// the IO address map with 8 consecutive available addresses.
LocalMsrRegister = 0;
((CSTATE_ADDRESS_MSR *) &LocalMsrRegister)->CstateAddr = PlatformConfig->CStateIoBaseAddress;
TaskPtr.FuncAddress.PfApTaskI = F10InitializeIoCstateOnCore;
TaskPtr.DataTransfer.DataSizeInDwords = 2;
TaskPtr.DataTransfer.DataPtr = &LocalMsrRegister;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, NULL);
}
return AGESA_SUCCESS;
}
/*---------------------------------------------------------------------------------------*/
/**
* Enable CState on a family 10h core.
*
* @param[in] CstateBaseMsr MSR value to write to C001_0073 as determined by core 0.
* @param[in] StdHeader Config Handle for library, services.
*
*/
VOID
STATIC
F10InitializeIoCstateOnCore (
IN VOID *CstateBaseMsr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
// Initialize MSRC001_0073[CstateAddr] on each core
LibAmdMsrWrite (MSR_CSTATE_ADDRESS, (UINT64 *) CstateBaseMsr, StdHeader);
}
/*---------------------------------------------------------------------------------------*/
/**
* Returns the size of CST object
*
* @param[in] IoCstateServices IO Cstate services.
* @param[in] PlatformConfig Contains the runtime modifiable feature input data
* @param[in] StdHeader Config Handle for library, services.
*
* @retval CstObjSize Size of CST Object
*
*/
UINT32
STATIC
F10GetAcpiCstObj (
IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
IN PLATFORM_CONFIGURATION *PlatformConfig,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
return (CST_HEADER_SIZE + CST_BODY_SIZE);
}
/*---------------------------------------------------------------------------------------*/
/**
* Routine to generate the C-State ACPI objects
*
* @param[in] IoCstateServices IO Cstate services.
* @param[in] LocalApicId Local Apic Id for each core.
* @param[in, out] **PstateAcpiBufferPtr Pointer to the Acpi Buffer Pointer.
* @param[in] StdHeader Config Handle for library, services.
*
*/
VOID
STATIC
F10CreateAcpiCstObj (
IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
IN UINT8 LocalApicId,
IN OUT VOID **PstateAcpiBufferPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 MsrData;
CST_HEADER_STRUCT *CstHeaderPtr;
CST_BODY_STRUCT *CstBodyPtr;
// Read from MSR C0010073 to obtain CstateAddr
LibAmdMsrRead (MSR_CSTATE_ADDRESS, &MsrData, StdHeader);
ASSERT ((((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr != 0) &&
(((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr <= 0xFFF8));
// Typecast the pointer
CstHeaderPtr = (CST_HEADER_STRUCT *) *PstateAcpiBufferPtr;
// Set CST Header
CstHeaderPtr->NameOpcode = NAME_OPCODE;
CstHeaderPtr->CstName_a__ = CST_NAME__;
CstHeaderPtr->CstName_a_C = CST_NAME_C;
CstHeaderPtr->CstName_a_S = CST_NAME_S;
CstHeaderPtr->CstName_a_T = CST_NAME_T;
// Typecast the pointer
CstHeaderPtr++;
CstBodyPtr = (CST_BODY_STRUCT *) CstHeaderPtr;
// Set CST Body
CstBodyPtr->PkgOpcode = PACKAGE_OPCODE;
CstBodyPtr->PkgLength = CST_LENGTH;
CstBodyPtr->PkgElements = CST_NUM_OF_ELEMENTS;
CstBodyPtr->BytePrefix = BYTE_PREFIX_OPCODE;
CstBodyPtr->Count = CST_COUNT;
CstBodyPtr->PkgOpcode2 = PACKAGE_OPCODE;
CstBodyPtr->PkgLength2 = CST_PKG_LENGTH;
CstBodyPtr->PkgElements2 = CST_PKG_ELEMENTS;
CstBodyPtr->BufferOpcode = BUFFER_OPCODE;
CstBodyPtr->BufferLength = CST_SUBPKG_LENGTH;
CstBodyPtr->BufferElements = CST_SUBPKG_ELEMENTS;
CstBodyPtr->BufferOpcode2 = BUFFER_OPCODE;
CstBodyPtr->GdrOpcode = GENERIC_REG_DESCRIPTION;
CstBodyPtr->GdrLength = CST_GDR_LENGTH;
CstBodyPtr->AddrSpaceId = GDR_ASI_SYSTEM_IO;
CstBodyPtr->RegBitWidth = 0x08;
CstBodyPtr->RegBitOffset = 0x00;
CstBodyPtr->AddressSize = GDR_ASZ_BYTE_ACCESS;
CstBodyPtr->RegisterAddr = ((CSTATE_ADDRESS_MSR *) &MsrData)->CstateAddr;
CstBodyPtr->EndTag = 0x0079;
CstBodyPtr->BytePrefix2 = BYTE_PREFIX_OPCODE;
CstBodyPtr->Type = CST_C2_TYPE;
CstBodyPtr->WordPrefix = WORD_PREFIX_OPCODE;
CstBodyPtr->Latency = 0x4B;
CstBodyPtr->DWordPrefix = DWORD_PREFIX_OPCODE;
CstBodyPtr->Power = 0;
CstBodyPtr++;
//Update the pointer
*PstateAcpiBufferPtr = CstBodyPtr;
}
/*---------------------------------------------------------------------------------------*/
/**
* Routine to check whether IO Cstate should be supported.
*
* @param[in] IoCstateServices IO Cstate services.
* @param[in] Socket Zero-based socket number.
* @param[in] StdHeader Config Handle for library, services.
*
* @retval TRUE Support IO Cstate.
* @retval FALSE Do not support IO Cstate.
*
*/
BOOLEAN
F10IsIoCstateFeatureSupported (
IN IO_CSTATE_FAMILY_SERVICES *IoCstateServices,
IN UINT32 Socket,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT64 LocalMsrRegister;
CPUID_DATA CpuId;
CPU_LOGICAL_ID LogicalId;
GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
// Only Rev.E processor with CPB enabled and ucode 010000BF or later loaded
// MSR_C001_0073 can be programmed
if ((LogicalId.Revision & AMD_F10_Ex) != 0) {
LibAmdCpuidRead (AMD_CPUID_APM, &CpuId, StdHeader);
if (((CpuId.EDX_Reg & 0x00000200) >> 9) == 1) {
LibAmdMsrRead (MSR_PATCH_LEVEL, &LocalMsrRegister, StdHeader);
if ((LocalMsrRegister & 0xffffffff) >= 0x010000BF) {
return TRUE;
}
}
}
return FALSE;
}
CONST IO_CSTATE_FAMILY_SERVICES ROMDATA F10IoCstateSupport =
{
0,
F10IsIoCstateFeatureSupported,
F10InitializeIoCstate,
F10GetAcpiCstObj,
F10CreateAcpiCstObj,
(PF_IO_CSTATE_IS_CSD_GENERATED) CommonReturnFalse
};

1525
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10MultiLinkPciTables.c Executable file
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83
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PackageType.h Executable file
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/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_10 Package Type Definitions
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F10
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _F10_PACKAGE_TYPE_H_
#define _F10_PACKAGE_TYPE_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
// Below equates are defined to cooperate with LibAmdGetPackageType.
#define PACKAGE_TYPE_FR2_FR5_FR6 (1 << 0)
#define PACKAGE_TYPE_AM2R2_AM3 (1 << 1)
#define PACKAGE_TYPE_S1G3_S1G4 (1 << 2)
#define PACKAGE_TYPE_G34 (1 << 3)
#define PACKAGE_TYPE_ASB2 (1 << 4)
#define PACKAGE_TYPE_C32 (1 << 5)
#define PACKAGE_TYPE_FR2 PACKAGE_TYPE_FR2_FR5_FR6
#define PACKAGE_TYPE_FR5 PACKAGE_TYPE_FR2_FR5_FR6
#define PACKAGE_TYPE_FR6 PACKAGE_TYPE_FR2_FR5_FR6
#define PACKAGE_TYPE_S1G3 PACKAGE_TYPE_S1G3_S1G4
#define PACKAGE_TYPE_S1G4 PACKAGE_TYPE_S1G3_S1G4
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
#endif // _F10_PACKAGE_TYPE_H_

180
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmAsymBoostInit.c Executable file
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/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_10 Asymmetric Boost Initialization
*
* Performs the "BIOS Configuration for Asymmetric Boost" as
* described in the BKDG.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F10
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuRegisters.h"
#include "cpuApicUtilities.h"
#include "cpuServices.h"
#include "GeneralServices.h"
#include "cpuFamilyTranslation.h"
#include "cpuF10PowerMgmt.h"
#include "F10PmAsymBoostInit.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_CPU_FAMILY_0X10_F10PMASYMBOOSTINIT_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
STATIC
SetAsymBoost (
IN VOID *AsymBoostRegister,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Family 10h core 0 entry point for performing the "Asymmetric Boost
* Configuration" algorithm.
*
* The algorithm is as follows:
* // Determine whether the processor support boost
* if (CPUID CPUID Fn8000_0007[CPB]==1)&& CPUID Fn8000_0008[NC]==5) {
* Core0 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore0]
* Core1 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore1]
* Core2 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore2]
* Core3 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore3]
* Core4 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore4]
* Core5 MSRC001_0064[CpuFid] += F3x10C[AsymmetricBoostCore5]
* }
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParamsPtr Service related parameters (unused).
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F10PmAsymBoostInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AP_TASK TaskPtr;
UINT32 Core;
UINT32 Socket;
UINT32 Module;
UINT32 LocalPciRegister;
PCI_ADDR PciAddress;
CPUID_DATA CpuidData;
AGESA_STATUS IgnoredSts;
// Check if CPB is supported. if yes, skip boosted p-state.
LibAmdCpuidRead (AMD_CPUID_APM, &CpuidData, StdHeader);
if (((CpuidData.EDX_Reg & 0x00000200) >> 9) == 1) {
LibAmdCpuidRead (CPUID_LONG_MODE_ADDR, &CpuidData, StdHeader);
if ((CpuidData.ECX_Reg & 0x000000FF) == 5) {
// get the local node ID
IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
// Read F3x10C [Boost Offset]
PciAddress.AddressValue = F3x10C_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
TaskPtr.FuncAddress.PfApTaskI = SetAsymBoost;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.DataTransfer.DataSizeInDwords = 1;
TaskPtr.DataTransfer.DataPtr = &LocalPciRegister;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
}
}
}
/*---------------------------------------------------------------------------------------*/
/**
* Set Asymmetric Boost.
*
* This function set Asymmetric Boost.
*
* @param[in] AsymBoostRegister Contains the value of Asymmetric Boost register
* @param[in] StdHeader Config handle for library and services
*
*/
VOID
STATIC
SetAsymBoost (
IN VOID *AsymBoostRegister,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 ControlByte;
UINT32 Core;
UINT32 Ignored;
UINT64 MsrValue;
AGESA_STATUS IgnoredSts;
IdentifyCore (StdHeader, &Ignored, &Ignored, &Core, &IgnoredSts);
ControlByte = (UINT8) ((Core & 0xFF) * 2);
LibAmdMsrRead (MSR_PSTATE_0, &MsrValue, StdHeader);
// Bits 5:0
((PSTATE_MSR *) &MsrValue)->CpuFid += ((*(UINT32*) AsymBoostRegister >> ControlByte) & 0x3);
LibAmdMsrWrite (MSR_PSTATE_0, &MsrValue, StdHeader);
}

77
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmAsymBoostInit.h Executable file
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/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_10 Asymmetric Boost Initialization
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F10
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _CPU_F10_ASYM_BOOST_H_
#define _CPU_F10_ASYM_BOOST_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
VOID
F10PmAsymBoostInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _CPU_F10_ASYM_BOOST_H_

245
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.c Executable file
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/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_10 Dual-plane Only Support
*
* Performs the "BIOS Configuration for Dual-plane Only Support" as
* described in the BKDG.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F10
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuRegisters.h"
#include "cpuApicUtilities.h"
#include "cpuServices.h"
#include "GeneralServices.h"
#include "cpuFamilyTranslation.h"
#include "cpuF10PowerMgmt.h"
#include "F10PackageType.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_CPU_FAMILY_0X10_F10PMDUALPLANEONLYSUPPORT_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
UINT32
STATIC
SetPstateMSR (
IN VOID *CPB,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------*/
/**
* Family 10h core 0 entry point for performing the "Dual-plane Only Support" algorithm.
*
* The algorithm is as follows:
* // Determine whether algorithm applies to this processor
* if (CPUID Fn8000_0001_EBX[PkgType] == 0001b && (revision C or E) {
* // Determine whether processor is supported in this infrastructure
* if (((F3x1FC[DualPlaneOnly] == 1) && (this is a dual-plane platform))
* || ((F3x1FC[AM3r2Only] == 1) && (this is an AM3r2 platform))) {
* // Fixup the P-state MSRs
* for (each core in the system) {
* if (CPUID Fn8000_0007[CPB]) {
* Copy MSRC001_0065 as MinPstate;
* Copy MSRC001_0068 to MSRC001_0065;
* Copy MinPstate to MSRC001_0068;
* } else {
* Copy MSRC001_0068 to MSRC001_0064;
* Program MSRC001_0068 = 0;
* } // endif
* for (each MSR in MSRC001_00[68:64]) {
* if (value in MSRC001_00[68:64][IddValue] != 0) {
* Set PstateEn in current MSR to 1;
* } // endif
* } // endfor
* } // endfor
* Set F3xDC[PstateMaxVal] = lowest-performance enabled P-state;
* Set F3xA8[PopDownPstate] = lowest-performance enabled P-state;
* Set F3x64[HtcPstateLimit] = lowest-performance enabled P-state;
* } // endif
* } // endif
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParamsPtr Service related parameters (unused).
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F10PmDualPlaneOnlySupport (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
AP_TASK TaskPtr;
UINT32 CPB;
UINT32 Core;
UINT32 Socket;
UINT32 Module;
UINT32 Pvimode;
UINT32 LowestPsEn;
UINT32 LocalPciRegister;
UINT32 ActiveCores;
UINT32 ProcessorPackageType;
PCI_ADDR PciAddress;
CPUID_DATA CpuidData;
CPU_LOGICAL_ID LogicalId;
AGESA_STATUS IgnoredSts;
// get the local node ID
IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
// get the package type
ProcessorPackageType = LibAmdGetPackageType (StdHeader);
GetLogicalIdOfCurrentCore (&LogicalId, StdHeader);
if (((LogicalId.Revision & (AMD_F10_Cx | AMD_F10_Ex)) != 0) && ((ProcessorPackageType & PACKAGE_TYPE_AM2R2_AM3) != 0)) {
PciAddress.AddressValue = PRCT_INFO_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
PciAddress.AddressValue = PW_CTL_MISC_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &Pvimode, StdHeader);
if ((((LocalPciRegister & 0x80000000) != 0) && (((POWER_CTRL_MISC_REGISTER *) &Pvimode)->PviMode == 0))
|| ((LocalPciRegister & 0x04000000) != 0)) {
CPB = 0;
LibAmdCpuidRead (AMD_CPUID_APM, &CpuidData, StdHeader);
if (((CpuidData.EDX_Reg & 0x00000200) >> 9) == 1) {
CPB = 1;
}
TaskPtr.FuncAddress.PfApTaskIO = SetPstateMSR;
TaskPtr.ExeFlags = TASK_HAS_OUTPUT | WAIT_FOR_CORE;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.DataTransfer.DataSizeInDwords = 1;
TaskPtr.DataTransfer.DataPtr = &CPB;
GetActiveCoresInCurrentSocket (&ActiveCores, StdHeader);
for (Core = 1; Core < (UINT8) ActiveCores; ++Core) {
ApUtilRunCodeOnSocketCore ((UINT8)0, (UINT8)Core, &TaskPtr, StdHeader);
}
LowestPsEn = ApUtilTaskOnExecutingCore (&TaskPtr, StdHeader, (VOID *) CpuEarlyParamsPtr);
PciAddress.AddressValue = CPTC2_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
((CLK_PWR_TIMING_CTRL2_REGISTER *) &LocalPciRegister)->PstateMaxVal = LowestPsEn;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
PciAddress.AddressValue = POPUP_PSTATE_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
((POPUP_PSTATE_REGISTER *) &LocalPciRegister)->PopDownPstate = LowestPsEn;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
PciAddress.AddressValue = HTC_PCI_ADDR;
LibAmdPciRead (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
((HTC_REGISTER *) &LocalPciRegister)->HtcPstateLimit = LowestPsEn;
LibAmdPciWrite (AccessWidth32, PciAddress, &LocalPciRegister, StdHeader);
}
}
}
/*---------------------------------------------------------------------------------------*/
/**
* Set P-State MSR.
*
* This function set the P-state MSRs per each core in the system.
*
* @param[in] CPB Contains the value of Asymmetric Boost register
* @param[in] StdHeader Config handle for library and services
*
* @return Return the lowest-performance enabled P-state
*/
UINT32
STATIC
SetPstateMSR (
IN VOID *CPB,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 dtemp;
UINT32 LowestPsEn;
UINT64 MsrValue;
UINT64 MinMsrValue;
if (*(UINT32*) CPB != 0) {
LibAmdMsrRead (MSR_PSTATE_1, &MinMsrValue, StdHeader);
LibAmdMsrRead (MSR_PSTATE_4, &MsrValue, StdHeader);
LibAmdMsrWrite (MSR_PSTATE_1, &MsrValue, StdHeader);
LibAmdMsrWrite (MSR_PSTATE_4, &MinMsrValue, StdHeader);
} else {
LibAmdMsrRead (MSR_PSTATE_4, &MsrValue, StdHeader);
LibAmdMsrWrite (MSR_PSTATE_0, &MsrValue, StdHeader);
MsrValue = 0;
LibAmdMsrWrite (MSR_PSTATE_4, &MsrValue, StdHeader);
}
LowestPsEn = 0;
for (dtemp = MSR_PSTATE_0; dtemp <= MSR_PSTATE_4; dtemp++) {
LibAmdMsrRead (dtemp, &MsrValue, StdHeader);
if (((PSTATE_MSR *) &MsrValue)->IddValue != 0) {
MsrValue = MsrValue | BIT63;
LibAmdMsrWrite (dtemp, &MsrValue, StdHeader);
LowestPsEn = dtemp - MSR_PSTATE_0;
}
}
return (LowestPsEn);
}

77
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmDualPlaneOnlySupport.h Executable file
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/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_10 BIOS Configuration for Dual-plane Only Support
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F10
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _CPU_F10_DUAL_PLANE_ONLY_SUPPORT_H_
#define _CPU_F10_DUAL_PLANE_ONLY_SUPPORT_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
VOID
F10PmDualPlaneOnlySupport (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _CPU_F10_DUAL_PLANE_ONLY_SUPPORT_H_

299
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmNbCofVidInit.c Executable file
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/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_10 NB COF VID Initialization
*
* Performs the "BIOS Northbridge COF and VID Configuration" as
* described in the BKDG.
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F10
* @e \$Revision: 44702 $ @e \$Date: 2011-01-05 06:54:00 +0800 (Wed, 05 Jan 2011) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
/*----------------------------------------------------------------------------------------
* M O D U L E S U S E D
*----------------------------------------------------------------------------------------
*/
#include "AGESA.h"
#include "amdlib.h"
#include "cpuRegisters.h"
#include "cpuF10PowerMgmt.h"
#include "cpuApicUtilities.h"
#include "OptionMultiSocket.h"
#include "cpuServices.h"
#include "GeneralServices.h"
#include "cpuFamilyTranslation.h"
#include "cpuF10Utilities.h"
#include "F10PmNbCofVidInit.h"
#include "Filecode.h"
CODE_GROUP (G1_PEICC)
RDATA_GROUP (G1_PEICC)
#define FILECODE PROC_CPU_FAMILY_0X10_F10PMNBCOFVIDINIT_FILECODE
/*----------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*----------------------------------------------------------------------------------------
*/
/*----------------------------------------------------------------------------------------
* T Y P E D E F S A N D S T R U C T U R E S
*----------------------------------------------------------------------------------------
*/
/// Structure used for performing the steps outlined in
/// the NB COFVID configuration sequence
typedef struct {
UINT8 NewNbVid; ///< Destination NB VID code
BOOLEAN NbVidUpdateAll; ///< Status of NbVidUpdateAll
} NB_COF_VID_INIT_WARM;
/*----------------------------------------------------------------------------------------
* P R O T O T Y P E S O F L O C A L F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
VOID
STATIC
PmNbCofVidInitP0P1Core (
IN VOID *NewNbVid,
IN AMD_CONFIG_PARAMS *StdHeader
);
VOID
STATIC
PmNbCofVidInitWarmCore (
IN VOID *FunctionData,
IN AMD_CONFIG_PARAMS *StdHeader
);
/*----------------------------------------------------------------------------------------
* E X P O R T E D F U N C T I O N S
*----------------------------------------------------------------------------------------
*/
extern OPTION_MULTISOCKET_CONFIGURATION OptionMultiSocketConfiguration;
/*---------------------------------------------------------------------------------------*/
/**
* Family 10h core 0 entry point for performing the "Northbridge COF and
* VID Configuration" algorithm.
*
* The steps are as follows:
* 1. Determine if the algorithm is necessary by checking if all NB FIDs
* match in the coherent fabric. If so, check to see if NbCofVidUpdate
* is zero for all CPUs. If that is also true, no further steps are
* necessary. If not + cold reset, proceed to step 2. If not + warm
* reset, proceed to step 8.
* 2. Determine NewNbVid & NewNbFid.
* 3. Copy Startup Pstate settings to P0/P1 MSRs on all local cores.
* 4. Copy NewNbVid to P0 NbVid on all local cores.
* 5. Transition to P1 on all local cores.
* 6. Transition to P0 on local core 0 only.
* 7. Copy NewNbFid to F3xD4[NbFid], set NbFidEn, and issue a warm reset.
* 8. Update all enabled Pstate MSRs' NbVids according to NbVidUpdateAll
* on all local cores.
* 9. Transition to Startup Pstate on all local cores.
*
* @param[in] FamilySpecificServices The current Family Specific Services.
* @param[in] CpuEarlyParamsPtr Service related parameters (unused).
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
F10PmNbCofVidInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
BOOLEAN PerformNbCofVidCfg;
BOOLEAN NotUsed;
BOOLEAN SystemNbCofsMatch;
UINT8 NewNbFid;
UINT8 NewNbVid;
UINT32 Socket;
UINT32 Module;
UINT32 Core;
UINT32 SystemNbCof;
UINT32 AndMask;
UINT32 OrMask;
UINT32 Ignored;
UINT32 NewNbVoltage;
UINT32 FrequencyDivisor;
WARM_RESET_REQUEST Request;
AP_TASK TaskPtr;
PCI_ADDR PciAddress;
AGESA_STATUS IgnoredSts;
NB_COF_VID_INIT_WARM FunctionData;
PerformNbCofVidCfg = TRUE;
OptionMultiSocketConfiguration.GetSystemNbPstateSettings ((UINT32) 0, &CpuEarlyParamsPtr->PlatformConfig, &SystemNbCof, &FrequencyDivisor, &SystemNbCofsMatch, &NotUsed, StdHeader);
if (SystemNbCofsMatch) {
if (!OptionMultiSocketConfiguration.GetSystemNbCofVidUpdate (StdHeader)) {
PerformNbCofVidCfg = FALSE;
}
}
if (PerformNbCofVidCfg) {
// get the local node ID
IdentifyCore (StdHeader, &Socket, &Module, &Core, &IgnoredSts);
GetPciAddress (StdHeader, Socket, Module, &PciAddress, &IgnoredSts);
ASSERT (Core == 0);
// get NewNbVid
FamilySpecificServices->GetNbPstateInfo (FamilySpecificServices,
&CpuEarlyParamsPtr->PlatformConfig,
&PciAddress,
(UINT32) 0,
&Ignored,
&Ignored,
&NewNbVoltage,
StdHeader);
ASSERT (((1550000 - NewNbVoltage) % 12500) == 0);
NewNbVid = (UINT8) ((1550000 - NewNbVoltage) / 12500);
ASSERT (NewNbVid < 0x80);
if (!(IsWarmReset (StdHeader))) {
// determine NewNbFid
NewNbFid = (UINT8) ((SystemNbCof / 200) - 4);
TaskPtr.FuncAddress.PfApTaskI = PmNbCofVidInitP0P1Core;
TaskPtr.DataTransfer.DataSizeInDwords = 1;
TaskPtr.DataTransfer.DataPtr = &NewNbVid;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = 0;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
// Transition core 0 to P0 and wait for change to complete
FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 0, (BOOLEAN) TRUE, StdHeader);
PciAddress.Address.Register = CPTC0_REG;
AndMask = 0xFFFFFFFF;
((CLK_PWR_TIMING_CTRL_REGISTER *) &AndMask)->NbFid = 0;
OrMask = 0x00000000;
((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->NbFid = NewNbFid;
((CLK_PWR_TIMING_CTRL_REGISTER *) &OrMask)->NbFidEn = 1;
ModifyCurrentSocketPci (&PciAddress, AndMask, OrMask, StdHeader);
// warm reset request
GetWarmResetFlag (StdHeader, &Request);
Request.RequestBit = TRUE;
Request.StateBits = Request.PostStage - 1;
SetWarmResetFlag (StdHeader, &Request);
} else {
// warm reset path
FunctionData.NewNbVid = NewNbVid;
FamilySpecificServices->IsNbCofInitNeeded (FamilySpecificServices, &PciAddress, &FunctionData.NbVidUpdateAll, StdHeader);
TaskPtr.FuncAddress.PfApTaskI = PmNbCofVidInitWarmCore;
TaskPtr.DataTransfer.DataSizeInDwords = SIZE_IN_DWORDS (NB_COF_VID_INIT_WARM);
TaskPtr.DataTransfer.DataPtr = &FunctionData;
TaskPtr.DataTransfer.DataTransferFlags = 0;
TaskPtr.ExeFlags = WAIT_FOR_CORE;
ApUtilRunCodeOnAllLocalCoresAtEarly (&TaskPtr, StdHeader, CpuEarlyParamsPtr);
}
} // skip whole algorithm
}
/*---------------------------------------------------------------------------------------*/
/**
* Cold reset support routine for F10PmNbCofVidInit.
*
* This function implements steps 3, 4, & 5 on each core.
*
* @param[in] NewNbVid NewNbVid determined by core 0 in step 2.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
STATIC
PmNbCofVidInitP0P1Core (
IN VOID *NewNbVid,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT8 NumBoostStates;
UINT32 MsrAddress;
UINT64 LocalMsrRegister;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
NumBoostStates = F10GetNumberOfBoostedPstatesOnCore (StdHeader);
GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
LibAmdMsrRead (MSR_COFVID_STS, &LocalMsrRegister, StdHeader);
MsrAddress = (UINT32) ((((COFVID_STS_MSR *) &LocalMsrRegister)->StartupPstate) + PS_REG_BASE);
LibAmdMsrRead (MsrAddress, &LocalMsrRegister, StdHeader);
LibAmdMsrWrite ((UINT32) (PS_REG_BASE + 1 + NumBoostStates), &LocalMsrRegister, StdHeader);
((PSTATE_MSR *) &LocalMsrRegister)->NbVid = *(UINT8 *) NewNbVid;
LibAmdMsrWrite (PS_REG_BASE + NumBoostStates, &LocalMsrRegister, StdHeader);
FamilySpecificServices->TransitionPstate (FamilySpecificServices, (UINT8) 1, (BOOLEAN) FALSE, StdHeader);
}
/*---------------------------------------------------------------------------------------*/
/**
* Warm reset support routine for F10PmNbCofVidInit.
*
* This function implements steps 8 & 9 on each core.
*
* @param[in] FunctionData Contains NewNbVid determined by core 0 in step
* 2, and NbVidUpdateAll.
* @param[in] StdHeader Config handle for library and services.
*
*/
VOID
STATIC
PmNbCofVidInitWarmCore (
IN VOID *FunctionData,
IN AMD_CONFIG_PARAMS *StdHeader
)
{
UINT32 MsrAddress;
UINT64 LocalMsrRegister;
CPU_SPECIFIC_SERVICES *FamilySpecificServices;
GetCpuServicesOfCurrentCore (&FamilySpecificServices, StdHeader);
for (MsrAddress = PS_REG_BASE; MsrAddress <= PS_MAX_REG; MsrAddress++) {
LibAmdMsrRead (MsrAddress, &LocalMsrRegister, StdHeader);
if (((PSTATE_MSR *) &LocalMsrRegister)->IddValue != 0) {
if ((((PSTATE_MSR *) &LocalMsrRegister)->NbDid == 0) || ((NB_COF_VID_INIT_WARM *) FunctionData)->NbVidUpdateAll) {
((PSTATE_MSR *) &LocalMsrRegister)->NbVid = ((NB_COF_VID_INIT_WARM *) FunctionData)->NewNbVid;
LibAmdMsrWrite (MsrAddress, &LocalMsrRegister, StdHeader);
}
}
}
}

76
src/vendorcode/amd/agesa/f12/Proc/CPU/Family/0x10/F10PmNbCofVidInit.h Executable file
View File

@ -0,0 +1,76 @@
/* $NoKeywords:$ */
/**
* @file
*
* AMD Family_10 NB COF VID Initialization
*
* @xrefitem bom "File Content Label" "Release Content"
* @e project: AGESA
* @e sub-project: CPU/F10
* @e \$Revision: 44324 $ @e \$Date: 2010-12-22 17:16:51 +0800 (Wed, 22 Dec 2010) $
*
*/
/*
******************************************************************************
*
* Copyright (c) 2011, Advanced Micro Devices, Inc.
* All rights reserved.
*
* Redistribution and use in source and binary forms, with or without
* modification, are permitted provided that the following conditions are met:
* * Redistributions of source code must retain the above copyright
* notice, this list of conditions and the following disclaimer.
* * Redistributions in binary form must reproduce the above copyright
* notice, this list of conditions and the following disclaimer in the
* documentation and/or other materials provided with the distribution.
* * Neither the name of Advanced Micro Devices, Inc. nor the names of
* its contributors may be used to endorse or promote products derived
* from this software without specific prior written permission.
*
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
* DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. BE LIABLE FOR ANY
* DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
* ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
******************************************************************************
*/
#ifndef _CPU_F10_PM_NB_COF_VID_INIT_H_
#define _CPU_F10_PM_NB_COF_VID_INIT_H_
/*---------------------------------------------------------------------------------------
* M I X E D (Definitions And Macros / Typedefs, Structures, Enums)
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* D E F I N I T I O N S A N D M A C R O S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* T Y P E D E F S, S T R U C T U R E S, E N U M S
*---------------------------------------------------------------------------------------
*/
/*---------------------------------------------------------------------------------------
* F U N C T I O N P R O T O T Y P E
*---------------------------------------------------------------------------------------
*/
VOID
F10PmNbCofVidInit (
IN CPU_SPECIFIC_SERVICES *FamilySpecificServices,
IN AMD_CPU_EARLY_PARAMS *CpuEarlyParamsPtr,
IN AMD_CONFIG_PARAMS *StdHeader
);
#endif // _CPU_F10_PM_NB_COF_VID_INIT_H_

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