chromeos mainboards: remove chromeos.asl

Use the ACPI generator for creating the Chrome OS gpio
package. Each mainboard has its own list of Chrome OS
gpios that are fed into a helper to generate the ACPI
external OIPG package.  Additionally, the common
chromeos.asl is now conditionally included based on
CONFIG_CHROMEOS.

Change-Id: I1d3d951964374a9d43521879d4c265fa513920d2
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/15909
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Duncan Laurie <dlaurie@chromium.org>

src/mainboard/google/auron/acpi/chromeos.asl

@@ -1,19 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
-	Package () { 0x0001, 0, 0xFFFFFFFF, "PCH-LP" }, // no recovery button
-	Package () { 0x0003, 1, 58, "PCH-LP" }, // firmware write protect
-})

src/mainboard/google/auron/chromeos.c

@@ -82,3 +82,13 @@ int get_write_protect_state(void)
 {
 	return get_gpio(CROS_WP_GPIO);
 }
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}

src/mainboard/google/auron/dsdt.asl

@@ -47,7 +47,6 @@ DefinitionBlock(
 	#include "acpi/thermal.asl"
 
 	// Chrome OS specific
-	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	// Chipset specific sleep states

src/mainboard/google/auron/mainboard.c

@@ -28,6 +28,7 @@
 #include <arch/io.h>
 #include <arch/interrupt.h>
 #include <boot/coreboot_tables.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 #include "ec.h"
 #include "onboard.h"
 
@@ -88,6 +89,7 @@ static void mainboard_enable(device_t dev)
 {
 	dev->ops->init = mainboard_init;
 	dev->ops->get_smbios_data = mainboard_smbios_data;
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
 }
 

src/mainboard/google/auron_paine/acpi/chromeos.asl

@@ -1,19 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
-	Package () { 0x0001, 0, 0xFFFFFFFF, "PCH-LP" }, // no recovery button
-	Package () { 0x0003, 1, 58, "PCH-LP" }, // firmware write protect
-})

src/mainboard/google/auron_paine/chromeos.c

@@ -82,3 +82,13 @@ int get_write_protect_state(void)
 {
 	return get_gpio(CROS_WP_GPIO);
 }
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}

src/mainboard/google/auron_paine/dsdt.asl

@@ -47,7 +47,6 @@ DefinitionBlock(
 	#include "acpi/thermal.asl"
 
 	// Chrome OS specific
-	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	// Chipset specific sleep states

src/mainboard/google/auron_paine/mainboard.c

@@ -28,6 +28,7 @@
 #include <arch/io.h>
 #include <arch/interrupt.h>
 #include <boot/coreboot_tables.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 #include "ec.h"
 #include "onboard.h"
 
@@ -61,6 +62,7 @@ static void mainboard_enable(device_t dev)
 {
 	dev->ops->init = mainboard_init;
 	dev->ops->get_smbios_data = mainboard_smbios_data;
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP,
 		GMA_INT15_PANEL_FIT_CENTERING,
 		GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);

src/mainboard/google/butterfly/acpi/chromeos.asl

@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
-	Package() { 0x001, 1, 0xFF, "PantherPoint" }, // recovery button
-	Package() { 0x002, 1, 0xFF, "PantherPoint" }, // developer button
-	Package() { 0x003, 0,    6, "PantherPoint" }, // firmware write protect
-})

src/mainboard/google/butterfly/chromeos.c

@@ -23,6 +23,7 @@
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
 #include <ec/quanta/ene_kb3940q/ec.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 #include "ec.h"
 
 #define WP_GPIO		6
@@ -136,3 +137,14 @@ int get_recovery_mode_switch(void)
 
 	return ec_rec_mode;
 }
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_DEV_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AL(WP_GPIO, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}

src/mainboard/google/butterfly/dsdt.asl

@@ -50,7 +50,6 @@ DefinitionBlock(
 		}
 	}
 
-	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	/* Chipset specific sleep states */

src/mainboard/google/butterfly/mainboard.c

@@ -34,6 +34,7 @@
 #include <smbios.h>
 #include <device/pci.h>
 #include <ec/quanta/ene_kb3940q/ec.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 static unsigned int search(char *p, char *a, unsigned int lengthp,
 			   unsigned int lengtha)
@@ -276,6 +277,7 @@ static void mainboard_enable(device_t dev)
 {
 	dev->ops->init = mainboard_init;
 	dev->ops->get_smbios_data = butterfly_onboard_smbios_data;
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
 }
 

src/mainboard/google/chell/acpi/chromeos.asl

@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include "../gpio.h"
-
-Name (OIPG, Package () {
-	/* No physical recovery GPIO. */
-	Package () { 0x0001, 0, 0xFFFFFFFF, "INT344B:00" },
-	/* Firmware write protect GPIO. */
-	Package () { 0x0003, 1, GPIO_PCH_WP, "INT344B:00" },
-})

src/mainboard/google/chell/chromeos.c

@@ -82,3 +82,13 @@ int get_write_protect_state(void)
 	/* Read PCH_WP GPIO. */
 	return gpio_get(GPIO_PCH_WP);
 }
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}

src/mainboard/google/chell/dsdt.asl

@@ -45,7 +45,6 @@ DefinitionBlock(
 	}
 
 	// Chrome OS specific
-	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	// Chipset specific sleep states

src/mainboard/google/chell/mainboard.c

@@ -20,6 +20,7 @@
 #include <device/device.h>
 #include <stdlib.h>
 #include <soc/nhlt.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 #include "ec.h"
 
 static void mainboard_init(device_t dev)
@@ -69,6 +70,7 @@ static void mainboard_enable(device_t dev)
 {
 	dev->ops->init = mainboard_init;
 	dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 }
 
 struct chip_operations mainboard_ops = {

src/mainboard/google/cyan/acpi/chromeos.asl

@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/*
- * Fields are in the following order.
- * - Type: recovery = 1 developer mode = 2 write protect = 3
- * - Active Level - if -1 not a valid gpio
- * - GPIO number encoding - if -1 not a valid gpio
- * - Chipset Name
- *
- * Note: We need to encode gpios within the 4 separate banks
- * with the MMIO offset of each banks space. e.g. MF_ISH_GPIO_4 would be encoded
- * as 0x10016 where the SUS offset (COMMUNITY_OFFSET_GPEAST) is 0x10000.
- */
-
-Name(OIPG, Package() {
-	/* No physical recovery button */
-	Package () { 0x0001, 0, 0xFFFFFFFF, "Braswell" },
-	Package () { 0x0003, 1, 0x10013, "Braswell" },
-})

src/mainboard/google/cyan/chromeos.c

@@ -123,3 +123,13 @@ int get_write_protect_state(void)
 	return (read32((void *)(COMMUNITY_GPEAST_BASE + WP_STATUS_PAD_CFG0))
 		& PAD_VAL_HIGH);
 }
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(0x10013, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}

src/mainboard/google/cyan/dsdt.asl

@@ -53,7 +53,6 @@ DefinitionBlock(
 			#include <soc/intel/common/acpi/wifi.asl>
 		}
 	}
-	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	/* Chipset specific sleep states */

src/mainboard/google/cyan/mainboard.c

@@ -18,6 +18,7 @@
 #include <bootstate.h>
 #include <device/device.h>
 #include <soc/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 #include "ec.h"
 
 static void mainboard_init(device_t dev)
@@ -32,6 +33,7 @@ static void mainboard_init(device_t dev)
 static void mainboard_enable(device_t dev)
 {
 	dev->ops->init = mainboard_init;
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 }
 
 

src/mainboard/google/falco/acpi/chromeos.asl

@@ -1,19 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
-	Package () { 0x0001, 0, 0xFFFFFFFF, "LynxPoint" }, // no recovery button
-	Package () { 0x0003, 1, 58, "LynxPoint" }, // firmware write protect
-})

src/mainboard/google/falco/chromeos.c

@@ -20,6 +20,7 @@
 #include <device/pci.h>
 #include <southbridge/intel/lynxpoint/pch.h>
 #include <southbridge/intel/common/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 #if CONFIG_EC_GOOGLE_CHROMEEC
 #include "ec.h"
@@ -86,3 +87,13 @@ int get_write_protect_state(void)
 {
 	return get_gpio(58);
 }
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(58, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}

src/mainboard/google/falco/dsdt.asl

@@ -54,7 +54,6 @@ DefinitionBlock(
 	#include "acpi/thermal.asl"
 
 	// Chrome OS specific
-	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	// Chipset specific sleep states

src/mainboard/google/falco/mainboard.c

@@ -29,6 +29,7 @@
 #include <arch/interrupt.h>
 #include <boot/coreboot_tables.h>
 #include <southbridge/intel/lynxpoint/pch.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 #include "ec.h"
 #include "onboard.h"
 
@@ -87,6 +88,7 @@ static void mainboard_enable(device_t dev)
 {
 	dev->ops->init = mainboard_init;
 	dev->ops->get_smbios_data = mainboard_smbios_data;
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
 }
 

src/mainboard/google/glados/acpi/chromeos.asl

@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include "../gpio.h"
-
-Name (OIPG, Package () {
-	/* No physical recovery GPIO. */
-	Package () { 0x0001, 0, 0xFFFFFFFF, "INT344B:00" },
-	/* Firmware write protect GPIO. */
-	Package () { 0x0003, 1, GPIO_PCH_WP, "INT344B:00" },
-})

src/mainboard/google/glados/chromeos.c

@@ -82,3 +82,13 @@ int get_write_protect_state(void)
 	/* Read PCH_WP GPIO. */
 	return gpio_get(GPIO_PCH_WP);
 }
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}

src/mainboard/google/glados/dsdt.asl

@@ -45,7 +45,6 @@ DefinitionBlock(
 	}
 
 	// Chrome OS specific
-	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	// Chipset specific sleep states

src/mainboard/google/glados/mainboard.c

@@ -20,6 +20,7 @@
 #include <device/device.h>
 #include <stdlib.h>
 #include <soc/nhlt.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 #include "ec.h"
 
 static void mainboard_init(device_t dev)
@@ -73,6 +74,7 @@ static void mainboard_enable(device_t dev)
 {
 	dev->ops->init = mainboard_init;
 	dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 }
 
 struct chip_operations mainboard_ops = {

src/mainboard/google/guado/acpi/chromeos.asl

@@ -1,19 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
-	Package () { 0x0001, 0, 12, "PCH-LP" }, // recovery button
-	Package () { 0x0003, 1, 58, "PCH-LP" }, // firmware write protect
-})

src/mainboard/google/guado/chromeos.c

@@ -93,3 +93,13 @@ void save_chromeos_gpios(void)
 	pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
 }
 #endif
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}

src/mainboard/google/guado/dsdt.asl

@@ -46,7 +46,6 @@ DefinitionBlock(
 	#include "acpi/thermal.asl"
 
 	// Chrome OS specific
-	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	// Chipset specific sleep states

src/mainboard/google/guado/mainboard.c

@@ -16,6 +16,7 @@
 
 #include <arch/acpi.h>
 #include <arch/io.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 #include "onboard.h"
 
 void mainboard_suspend_resume(void)
@@ -35,6 +36,7 @@ static void mainboard_init(device_t dev)
 static void mainboard_enable(device_t dev)
 {
 	dev->ops->init = mainboard_init;
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 }
 
 struct chip_operations mainboard_ops = {

src/mainboard/google/jecht/acpi/chromeos.asl

@@ -1,19 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
-	Package () { 0x0001, 0, 12, "PCH-LP" }, // recovery button
-	Package () { 0x0003, 1, 58, "PCH-LP" }, // firmware write protect
-})

src/mainboard/google/jecht/chromeos.c

@@ -94,3 +94,13 @@ void save_chromeos_gpios(void)
 	pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
 }
 #endif
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}

src/mainboard/google/jecht/dsdt.asl

@@ -47,7 +47,6 @@ DefinitionBlock(
 	#include "acpi/thermal.asl"
 
 	// Chrome OS specific
-	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	// Chipset specific sleep states

src/mainboard/google/jecht/mainboard.c

@@ -30,6 +30,7 @@
 #include <arch/io.h>
 #include <arch/interrupt.h>
 #include <boot/coreboot_tables.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 #include "onboard.h"
 
 void mainboard_suspend_resume(void)
@@ -135,6 +136,7 @@ static void mainboard_init(device_t dev)
 static void mainboard_enable(device_t dev)
 {
 	dev->ops->init = mainboard_init;
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 #if CONFIG_VGA_ROM_RUN
 	/* Install custom int15 handler for VGA OPROM */
 	mainboard_interrupt_handlers(0x15, &int15_handler);

src/mainboard/google/lars/acpi/chromeos.asl

@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include "../gpio.h"
-
-Name (OIPG, Package () {
-	/* No physical recovery GPIO. */
-	Package () { 0x0001, 0, 0xFFFFFFFF, "INT344B:00" },
-	/* Firmware write protect GPIO. */
-	Package () { 0x0003, 1, GPIO_PCH_WP, "INT344B:00" },
-})

src/mainboard/google/lars/chromeos.c

@@ -82,3 +82,13 @@ int get_write_protect_state(void)
 	/* Read PCH_WP GPIO. */
 	return gpio_get(GPIO_PCH_WP);
 }
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}

src/mainboard/google/lars/dsdt.asl

@@ -45,7 +45,6 @@ DefinitionBlock(
 	}
 
 	// Chrome OS specific
-	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	// Chipset specific sleep states

src/mainboard/google/lars/mainboard.c

@@ -20,6 +20,7 @@
 #include <device/device.h>
 #include <stdlib.h>
 #include <soc/nhlt.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 #include "ec.h"
 
 static void mainboard_init(device_t dev)
@@ -69,6 +70,7 @@ static void mainboard_enable(device_t dev)
 {
 	dev->ops->init = mainboard_init;
 	dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 }
 
 struct chip_operations mainboard_ops = {

src/mainboard/google/link/acpi/chromeos.asl

@@ -1,19 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
-	Package() { 0x001, 0,  9, "PantherPoint" }, // recovery button
-	Package() { 0x003, 1, 57, "PantherPoint" }, // firmware write protect
-})

src/mainboard/google/link/chromeos.c

@@ -22,6 +22,7 @@
 #include <southbridge/intel/common/gpio.h>
 #include "ec.h"
 #include <ec/google/chromeec/ec.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 #ifndef __PRE_RAM__
 #include <boot/coreboot_tables.h>
@@ -107,3 +108,13 @@ int get_recovery_mode_switch(void)
 	return !!(ec_events &
 		  EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEYBOARD_RECOVERY));
 }
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(9, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(57, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}

src/mainboard/google/link/dsdt.asl

@@ -50,7 +50,6 @@ DefinitionBlock(
 		}
 	}
 
-	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	/* Chipset specific sleep states */

src/mainboard/google/link/mainboard.c

@@ -36,6 +36,7 @@
 #include <smbios.h>
 #include <device/pci.h>
 #include <ec/google/chromeec/ec.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 /* placeholder for evenual link post. Not sure what we'll
  * do but it will look nice
@@ -199,6 +200,7 @@ static void mainboard_enable(device_t dev)
 {
 	dev->ops->init = mainboard_init;
 	dev->ops->get_smbios_data = link_onboard_smbios_data;
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 #if CONFIG_VGA_ROM_RUN
 	/* Install custom int15 handler for VGA OPROM */
 	mainboard_interrupt_handlers(0x15, &int15_handler);

src/mainboard/google/ninja/acpi/chromeos.asl

@@ -1,31 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/*
- * Fields are in the following order.
- * - Type: recovery = 1 developer mode = 2 write protect = 3
- * - Active Level - if -1 not a valid gpio
- * - GPIO number encoding - if -1 not a valid gpio
- * - Chipset Name
- *
- * Note: On Bay Trail we need to encode gpios within the 3 separate banks
- * with the MMIO offset of each banks space. e.g. GPIO_SUS[8] would be encoded
- * as 0x2008 where the SUS offset (IO_BASE_OFFSET_GPSSUS) is 0x2000.
- */
-
-Name(OIPG, Package() {
-	Package () { 0x0001, 0, 0x2008, "BayTrail" }, // recovery
-	Package () { 0x0003, 1, 0x2006, "BayTrail" }, // firmware write protect
-})

src/mainboard/google/ninja/chromeos.c

@@ -100,4 +100,14 @@ int get_write_protect_state(void)
 
 	/* WP is enabled when the pin is reading high. */
 	return ssus_get_gpio(WP_STATUS_PAD);
-}
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(0x2008, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(0x2006, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}

src/mainboard/google/ninja/dsdt.asl

@@ -44,7 +44,6 @@ DefinitionBlock(
 		#include "acpi/dptf.asl"
 	}
 
-	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	/* Chipset specific sleep states */

src/mainboard/google/ninja/mainboard.c

@@ -34,6 +34,7 @@
 #include "onboard.h"
 #include <soc/gpio.h>
 #include <bootstate.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 void mainboard_suspend_resume(void)
 {
@@ -144,6 +145,7 @@ static void mainboard_enable(device_t dev)
 {
 	dev->ops->init = mainboard_init;
 	dev->ops->get_smbios_data = mainboard_smbios_data;
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 #if CONFIG_VGA_ROM_RUN
 	/* Install custom int15 handler for VGA OPROM */
 	mainboard_interrupt_handlers(0x15, &int15_handler);

src/mainboard/google/panther/acpi/chromeos.asl

@@ -1,19 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
-	Package () { 0x0001, 0, 12, "LynxPoint" }, // recovery button
-	Package () { 0x0003, 1, 58, "LynxPoint" }, // firmware write protect
-})

src/mainboard/google/panther/chromeos.c

@@ -92,3 +92,13 @@ void init_bootmode_straps(void)
 	pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
 }
 #endif
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}

src/mainboard/google/panther/dsdt.asl

@@ -54,7 +54,6 @@ DefinitionBlock(
 	#include "acpi/thermal.asl"
 
 	// Chrome OS specific
-	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	// Chipset specific sleep states

src/mainboard/google/panther/mainboard.c

@@ -29,6 +29,7 @@
 #include <pc80/mc146818rtc.h>
 #include <southbridge/intel/lynxpoint/pch.h>
 #include <drivers/intel/gma/int15.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 #include "onboard.h"
 
 
@@ -51,6 +52,7 @@ static void mainboard_init(device_t dev)
 static void mainboard_enable(device_t dev)
 {
 	dev->ops->init = mainboard_init;
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
 }
 

src/mainboard/google/parrot/acpi/chromeos.asl

@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
-	Package() { 0x001, 1, 0xFF, "PantherPoint" }, // recovery button
-	Package() { 0x002, 1, 0xFF, "PantherPoint" }, // developer button
-	Package() { 0x003, 0,   70, "PantherPoint" }, // firmware write protect
-})

src/mainboard/google/parrot/chromeos.c

@@ -23,6 +23,7 @@
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
 #include <ec/compal/ene932/ec.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 #include "ec.h"
 
 
@@ -122,3 +123,14 @@ int parrot_ec_running_ro(void)
 {
 	return !get_gpio(68);
 }
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_DEV_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AL(70, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}

src/mainboard/google/parrot/dsdt.asl

@@ -50,7 +50,6 @@ DefinitionBlock(
 		}
 	}
 
-	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	/* Chipset specific sleep states */

src/mainboard/google/parrot/mainboard.c

@@ -32,6 +32,7 @@
 #include <smbios.h>
 #include <device/pci.h>
 #include <ec/compal/ene932/ec.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 void mainboard_suspend_resume(void)
 {
@@ -81,6 +82,7 @@ static void mainboard_enable(device_t dev)
 {
 	dev->ops->init = mainboard_init;
 	dev->ops->get_smbios_data = parrot_onboard_smbios_data;
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
 }
 

src/mainboard/google/peppy/acpi/chromeos.asl

@@ -1,19 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
-	Package () { 0x0001, 0, 0xFFFFFFFF, "LynxPoint" }, // no recovery button
-	Package () { 0x0003, 1, 58, "LynxPoint" }, // firmware write protect
-})

src/mainboard/google/peppy/chromeos.c

@@ -20,6 +20,7 @@
 #include <device/pci.h>
 #include <southbridge/intel/lynxpoint/pch.h>
 #include <southbridge/intel/common/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 #if CONFIG_EC_GOOGLE_CHROMEEC
 #include "ec.h"
@@ -86,3 +87,13 @@ int get_write_protect_state(void)
 {
 	return get_gpio(58);
 }
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(58, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}

src/mainboard/google/peppy/dsdt.asl

@@ -52,7 +52,6 @@ DefinitionBlock(
 	#include "acpi/thermal.asl"
 
 	// Chrome OS specific
-	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	// Chipset specific sleep states

src/mainboard/google/peppy/mainboard.c

@@ -29,6 +29,7 @@
 #include <arch/interrupt.h>
 #include <boot/coreboot_tables.h>
 #include <southbridge/intel/lynxpoint/pch.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 #include "ec.h"
 #include "onboard.h"
 
@@ -87,6 +88,7 @@ static void mainboard_enable(device_t dev)
 {
 	dev->ops->init = mainboard_init;
 	dev->ops->get_smbios_data = mainboard_smbios_data;
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
 }
 

src/mainboard/google/rambi/acpi/chromeos.asl

@@ -1,32 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/*
- * Fields are in the following order.
- * - Type: recovery = 1 developer mode = 2 write protect = 3
- * - Active Level - if -1 not a valid gpio
- * - GPIO number encoding - if -1 not a valid gpio
- * - Chipset Name
- *
- * Note: On Bay Trail we need to encode gpios within the 3 separate banks
- * with the MMIO offset of each banks space. e.g. GPIO_SUS[8] would be encoded
- * as 0x2008 where the SUS offset (IO_BASE_OFFSET_GPSSUS) is 0x2000.
- */
-
-Name(OIPG, Package() {
-	// No physical recovery button
-	Package () { 0x0001, 0, 0xFFFFFFFF, "BayTrail" },
-	Package () { 0x0003, 1, 0x2006, "BayTrail" },
-})

src/mainboard/google/rambi/chromeos.c

@@ -20,6 +20,7 @@
 #include <device/pci.h>
 #include <soc/gpio.h>
 #include <vboot/vboot_common.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 #if CONFIG_EC_GOOGLE_CHROMEEC
 #include "ec.h"
@@ -111,3 +112,13 @@ int get_write_protect_state(void)
 	/* WP is enabled when the pin is reading high. */
 	return ssus_get_gpio(WP_STATUS_PAD);
 }
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(0x2006, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}

src/mainboard/google/rambi/dsdt.asl

@@ -44,7 +44,6 @@ DefinitionBlock(
 		#include "acpi/dptf.asl"
 	}
 
-	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	/* Chipset specific sleep states */

src/mainboard/google/rambi/mainboard.c

@@ -34,6 +34,7 @@
 #include "onboard.h"
 #include <soc/gpio.h>
 #include <bootstate.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 void mainboard_suspend_resume(void)
 {
@@ -163,6 +164,7 @@ static void mainboard_enable(device_t dev)
 {
 	dev->ops->init = mainboard_init;
 	dev->ops->get_smbios_data = mainboard_smbios_data;
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 #if CONFIG_VGA_ROM_RUN
 	/* Install custom int15 handler for VGA OPROM */
 	mainboard_interrupt_handlers(0x15, &int15_handler);

src/mainboard/google/reef/acpi/chromeos.asl

@@ -1,23 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright 2016 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <soc/gpio_defs.h>
-
-Name (OIPG, Package () {
-	/* No physical recovery GPIO. */
-	Package () { 0x0001, 0, 0xFFFFFFFF, "INT3452:01" },
-	/* Firmware write protect GPIO. */
-	Package () { 0x0003, 1, PAD_NW(GPIO_75), "INT3452:01" },
-})

src/mainboard/google/reef/chromeos.c

@@ -19,6 +19,7 @@
 #include <vendorcode/google/chromeos/chromeos.h>
 #include <soc/gpio.h>
 #include "ec.h"
+#include "gpio.h"
 
 #define GPIO_PCH_WP GPIO_75
 #define GPIO_EC_IN_RW GPIO_41
@@ -69,3 +70,13 @@ int get_write_protect_state(void)
 	/* Read PCH_WP GPIO. */
 	return gpio_get(GPIO_PCH_WP);
 }
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_COMM_NW_NAME),
+	CROS_GPIO_WP_AH(PAD_NW(GPIO_PCH_WP), GPIO_COMM_NW_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}

src/mainboard/google/reef/dsdt.asl

@@ -38,7 +38,6 @@ DefinitionBlock(
 	}
 
 	/* Chrome OS specific */
-	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	/* Chipset specific sleep states */

src/mainboard/google/reef/mainboard.c

@@ -20,6 +20,7 @@
 #include <nhlt.h>
 #include <soc/gpio.h>
 #include <soc/nhlt.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 #include "ec.h"
 #include "gpio.h"
 
@@ -83,6 +84,7 @@ static unsigned long mainboard_write_acpi_tables(
 static void mainboard_enable(device_t dev)
 {
 	dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 }
 
 struct chip_operations mainboard_ops = {

src/mainboard/google/rikku/acpi/chromeos.asl

@@ -1,19 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2015 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
-	Package () { 0x0001, 0, 12, "PCH-LP" }, // recovery button
-	Package () { 0x0003, 1, 58, "PCH-LP" }, // firmware write protect
-})

src/mainboard/google/rikku/chromeos.c

@@ -93,3 +93,13 @@ void save_chromeos_gpios(void)
 	pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
 }
 #endif
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}

src/mainboard/google/rikku/dsdt.asl

@@ -46,7 +46,6 @@ DefinitionBlock(
 	#include "acpi/thermal.asl"
 
 	// Chrome OS specific
-	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	// Chipset specific sleep states

src/mainboard/google/rikku/mainboard.c

@@ -16,6 +16,7 @@
 
 #include <arch/acpi.h>
 #include <arch/io.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 #include "onboard.h"
 
 void mainboard_suspend_resume(void)
@@ -35,6 +36,7 @@ static void mainboard_init(device_t dev)
 static void mainboard_enable(device_t dev)
 {
 	dev->ops->init = mainboard_init;
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 }
 
 struct chip_operations mainboard_ops = {

src/mainboard/google/samus/acpi/chromeos.asl

@@ -1,19 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Name (OIPG, Package() {
-	Package () { 0x0001, 0, 0xFFFFFFFF, "INT3437:00" }, // no recovery button
-	Package () { 0x0003, 1, 16, "INT3437:00" }, // firmware write protect
-})

src/mainboard/google/samus/chromeos.c

@@ -93,3 +93,13 @@ int get_write_protect_state(void)
 {
 	return get_gpio(CROS_WP_GPIO);
 }
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_ACPI_DEVICE_NAME),
+	CROS_GPIO_WP_AH(CROS_WP_GPIO, CROS_GPIO_ACPI_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}

src/mainboard/google/samus/dsdt.asl

@@ -47,7 +47,6 @@ DefinitionBlock(
 	#include "acpi/thermal.asl"
 
 	// Chrome OS specific
-	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	// Chipset specific sleep states

src/mainboard/google/samus/mainboard.c

@@ -28,6 +28,7 @@
 #include <arch/io.h>
 #include <arch/interrupt.h>
 #include <boot/coreboot_tables.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 #include "board_version.h"
 #include "ec.h"
 
@@ -51,6 +52,7 @@ static void mainboard_init(device_t dev)
 static void mainboard_enable(device_t dev)
 {
 	dev->ops->init = mainboard_init;
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
 }
 

src/mainboard/google/stout/acpi/chromeos.asl

@@ -1,22 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
-	// No GPIO for recovery mode, developer mode, or firmware write protect
-	// on stout - note: all virtual pins are active HIGH polarity on stout.
-	Package() { 0x001, 1, 0xFF, "PantherPoint" }, // recovery button
-	Package() { 0x002, 1, 0xFF, "PantherPoint" }, // developer button
-	Package() { 0x003, 0, 7, "PantherPoint" }, // firmware write protect
-})

src/mainboard/google/stout/chromeos.c

@@ -22,6 +22,7 @@
 
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 #include "ec.h"
 #include <ec/quanta/it8518/ec.h>
 
@@ -133,3 +134,14 @@ int get_recovery_mode_switch(void)
 	return ec_in_rec_mode;
 #endif
 }
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_REC_AH(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AL(7, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}

src/mainboard/google/stout/dsdt.asl

@@ -50,7 +50,6 @@ DefinitionBlock(
 		}
 	}
 
-	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	/* Chipset specific sleep states */

src/mainboard/google/stout/mainboard.c

@@ -32,6 +32,7 @@
 #include <smbios.h>
 #include <device/pci.h>
 #include <ec/quanta/it8518/ec.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 void mainboard_suspend_resume(void)
 {
@@ -66,6 +67,7 @@ static void mainboard_init(device_t dev)
 static void mainboard_enable(device_t dev)
 {
 	dev->ops->init = mainboard_init;
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_INT_LVDS, GMA_INT15_PANEL_FIT_DEFAULT, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
 }
 

src/mainboard/google/tidus/acpi/chromeos.asl

@@ -1,19 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2014 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
-	Package () { 0x0001, 0, 12, "PCH-LP" }, // recovery button
-	Package () { 0x0003, 1, 58, "PCH-LP" }, // firmware write protect
-})

src/mainboard/google/tidus/chromeos.c

@@ -93,3 +93,13 @@ void save_chromeos_gpios(void)
 	pci_write_config32(PCI_DEV(0, 0x1f, 2), SATA_SP, flags);
 }
 #endif
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(GPIO_REC_MODE, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(GPIO_SPI_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}

src/mainboard/google/tidus/dsdt.asl

@@ -46,7 +46,6 @@ DefinitionBlock(
 	#include "acpi/thermal.asl"
 
 	// Chrome OS specific
-	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	// Chipset specific sleep states

src/mainboard/google/tidus/mainboard.c

@@ -16,6 +16,7 @@
 
 #include <arch/acpi.h>
 #include <arch/io.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 #include "onboard.h"
 
 void mainboard_suspend_resume(void)
@@ -35,6 +36,7 @@ static void mainboard_init(device_t dev)
 static void mainboard_enable(device_t dev)
 {
 	dev->ops->init = mainboard_init;
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 }
 
 struct chip_operations mainboard_ops = {

src/mainboard/intel/amenia/acpi/chromeos.asl

@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2016 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <soc/gpio_defs.h>
-
-Name (OIPG, Package () {
-	/* No physical recovery GPIO. */
-	Package () { 0x0001, 0, 0xFFFFFFFF, "INT3452:01" },
-	/* Firmware write protect GPIO. */
-	Package () { 0x0003, 1, PAD_NW(GPIO_75), "INT3452:01" },
-})

src/mainboard/intel/amenia/chromeos.c

@@ -18,6 +18,7 @@
 #include "ec.h"
 
 #include <ec/google/chromeec/ec.h>
+#include <soc/gpio_defs.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
 int get_lid_switch(void)
@@ -48,3 +49,13 @@ int get_write_protect_state(void)
 {
 	return 0;
 }
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, GPIO_COMM_NW_NAME),
+	CROS_GPIO_WP_AH(PAD_NW(GPIO_75), GPIO_COMM_NW_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}

src/mainboard/intel/amenia/dsdt.asl

@@ -39,10 +39,7 @@ DefinitionBlock(
 		}
 	}
 
-	#if IS_ENABLED(CONFIG_CHROMEOS)
-	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
-	#endif
 
 	/* Mainboard Specific devices */
 	#include "acpi/mainboard.asl"

src/mainboard/intel/baskingridge/acpi/chromeos.asl

@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
-	Package () { 0x0001, 1, 69, "LynxPoint" }, // recovery
-	Package () { 0x0002, 0, 48, "LynxPoint" }, // developer
-	Package () { 0x0003, 0, 22, "LynxPoint" }, // firmware write protect
-})

src/mainboard/intel/baskingridge/chromeos.c

@@ -20,6 +20,7 @@
 #include <device/pci.h>
 #include <southbridge/intel/lynxpoint/pch.h>
 #include <southbridge/intel/common/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 #ifndef __PRE_RAM__
 #include <boot/coreboot_tables.h>
@@ -102,3 +103,14 @@ int get_write_protect_state(void)
 {
 	return 0;
 }
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AH(69, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_DEV_AL(48, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AL(22, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}

src/mainboard/intel/baskingridge/dsdt.asl

@@ -48,7 +48,6 @@ DefinitionBlock(
 		}
 	}
 
-	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	/* Chipset specific sleep states */

src/mainboard/intel/baskingridge/mainboard.c

@@ -28,6 +28,7 @@
 #include <arch/interrupt.h>
 #include <boot/coreboot_tables.h>
 #include <southbridge/intel/lynxpoint/pch.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 void mainboard_suspend_resume(void)
 {
@@ -35,13 +36,12 @@ void mainboard_suspend_resume(void)
 	outb(0xcb, 0xb2);
 }
 
-
-
 // mainboard_enable is executed as first thing after
 // enumerate_buses().
 
 static void mainboard_enable(device_t dev)
 {
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
 }
 

src/mainboard/intel/emeraldlake2/acpi/chromeos.asl

@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Name(OIPG, Package() {
-	Package() { 0x001, 0, 22, "CougarPoint" }, // recovery button
-	Package() { 0x002, 1, 57, "CougarPoint" }, // developer switch
-	Package() { 0x003, 0, 48, "CougarPoint" }, // firmware write protect
-})

src/mainboard/intel/emeraldlake2/chromeos.c

@@ -20,6 +20,7 @@
 #include <device/pci.h>
 #include <southbridge/intel/bd82x6x/pch.h>
 #include <southbridge/intel/common/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 #ifndef __PRE_RAM__
 #include <boot/coreboot_tables.h>
@@ -91,3 +92,14 @@ int get_recovery_mode_switch(void)
 	/* Recovery: GPIO22, active low */
 	return !get_gpio(22);
 }
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(22, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_DEV_AH(57, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AL(48, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}

src/mainboard/intel/emeraldlake2/dsdt.asl

@@ -49,7 +49,6 @@ DefinitionBlock(
 		}
 	}
 
-	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	/* Chipset specific sleep states */

src/mainboard/intel/emeraldlake2/mainboard.c

@@ -28,12 +28,14 @@
 #include <arch/interrupt.h>
 #include <boot/coreboot_tables.h>
 #include <southbridge/intel/bd82x6x/pch.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 
 // mainboard_enable is executed as first thing after
 // enumerate_buses().
 
 static void mainboard_enable(device_t dev)
 {
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 	install_intel_vga_int15_handler(GMA_INT15_ACTIVE_LFP_EDP, GMA_INT15_PANEL_FIT_CENTERING, GMA_INT15_BOOT_DISPLAY_DEFAULT, 0);
 }
 

src/mainboard/intel/kunimitsu/acpi/chromeos.asl

@@ -1,24 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2015 Intel Corporation.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include "../gpio.h"
-
-Name (OIPG, Package () {
-	/* No physical recovery GPIO. */
-	Package () { 0x0001, 0, 0xFFFFFFFF, "INT344B:00" },
-	/* Firmware write protect GPIO. */
-	Package () { 0x0003, 1, GPIO_PCH_WP, "INT344B:00" },
-})

src/mainboard/intel/kunimitsu/chromeos.c

@@ -82,3 +82,13 @@ int get_write_protect_state(void)
 	/* Read PCH_WP GPIO. */
 	return gpio_get(GPIO_PCH_WP);
 }
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+	CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME),
+};
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	chromeos_acpi_gpio_generate(cros_gpios, ARRAY_SIZE(cros_gpios));
+}

src/mainboard/intel/kunimitsu/dsdt.asl

@@ -45,7 +45,6 @@ DefinitionBlock(
 	}
 
 	// Chrome OS specific
-	#include "acpi/chromeos.asl"
 	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
 
 	// Chipset specific sleep states

src/mainboard/intel/kunimitsu/mainboard.c

@@ -22,6 +22,7 @@
 #include <stdlib.h>
 #include <string.h>
 #include <soc/nhlt.h>
+#include <vendorcode/google/chromeos/chromeos.h>
 #include "ec.h"
 #include "gpio.h"
 
@@ -99,6 +100,7 @@ static void mainboard_enable(device_t dev)
 {
 	dev->ops->init = mainboard_init;
 	dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
 }
 
 struct chip_operations mainboard_ops = {

src/mainboard/intel/strago/acpi/chromeos.asl

@@ -1,33 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- * Copyright (C) 2015 Intel Corp.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-/*
- * Fields are in the following order.
- * - Type: recovery = 1 developer mode = 2 write protect = 3
- * - Active Level - if -1 not a valid gpio
- * - GPIO number encoding - if -1 not a valid gpio
- * - Chipset Name
- *
- * Note: We need to encode gpios within the 4 separate banks
- * with the MMIO offset of each banks space. e.g. MF_ISH_GPIO_4 would be encoded
- * as 0x10013 where the SUS offset (COMMUNITY_OFFSET_GPEAST) is 0x10000.
- */
-
-Name(OIPG, Package() {
-	/* No physical recovery button */
-	Package () { 0x0001, 0, 0xFFFFFFFF, "Braswell" },
-	Package () { 0x0003, 1, 0x10013, "Braswell" },
-})