mb/google/rex: Skip UART0 config in FSP

UART0 is already configured in coreboot, so this change sets SerialIo
config for UART0 to PchSerialIoSkipInit to skip initialization in FSP.

BUG=none
TEST=Able to build and boot google/rex0. Able to see all debug prints
over CPU uart.

Change-Id: I37744f05083eb82ba8ca579b628b69aa976e3d1f
Signed-off-by: Subrata Banik <subratabanik@google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83750
Reviewed-by: Eric Lai <ericllai@google.com>
Reviewed-by: Dinesh Gehlot <digehlot@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/mainboard/google/rex/variants/baseboard/rex/devicetree.cb

@@ -73,7 +73,7 @@ chip soc/intel/meteorlake
 	register "skip_ext_gfx_scan" = "1"
 
 	register "serial_io_uart_mode" = "{
-		[PchSerialIoIndexUART0] = PchSerialIoPci,
+		[PchSerialIoIndexUART0] = PchSerialIoSkipInit,
 		[PchSerialIoIndexUART1] = PchSerialIoDisabled,
 		[PchSerialIoIndexUART2] = PchSerialIoDisabled,
 	}"