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soc/amd/*/data_fabric: rename define for MMIO decode register set count

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This should make it a bit clearer that those registers are in the data
fabric configuration registers. Also move those defines right after the
register definition those are related to.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic107bd217f4af0a9ddfbe41aafd3c882aa968e22
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72876
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Fred Reitberger <reitbergerfred@gmail.com>
This commit is contained in:
Felix Held 2023-02-07 12:06:41 +01:00
parent 7c7294fa27
commit b307ed66b0
6 changed files with 13 additions and 13 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

4
src/soc/amd/cezanne/include/soc/data_fabric.h
View File

@ -11,14 +11,14 @@
#define D18F0_MMIO_SHIFT 16
#define D18F0_MMIO_CTRL0 0x208
#define DF_MMIO_REG_SET_COUNT 8
#define DF_FICAA_BIOS 0x5C
#define DF_FICAD_LO 0x98
#define DF_FICAD_HI 0x9C
#define IOMS0_FABRIC_ID 10
#define NUM_NB_MMIO_REGS 8
union df_mmio_control {
struct {
uint32_t re : 1; /* [ 0.. 0] */

6
src/soc/amd/common/block/data_fabric/data_fabric_helper.c
View File

@ -52,7 +52,7 @@ void data_fabric_print_mmio_conf(void)
printk(BIOS_SPEW,
"=== Data Fabric MMIO configuration registers ===\n"
"idx control base limit\n");
for (unsigned int i = 0; i < NUM_NB_MMIO_REGS; i++) {
for (unsigned int i = 0; i < DF_MMIO_REG_SET_COUNT; i++) {
control = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i));
/* Base and limit address registers don't contain the lower address bits, but
are shifted by D18F0_MMIO_SHIFT bits */
@ -84,7 +84,7 @@ static bool is_mmio_reg_disabled(unsigned int reg)
int data_fabric_find_unused_mmio_reg(void)
{
for (unsigned int i = 0; i < NUM_NB_MMIO_REGS; i++) {
for (unsigned int i = 0; i < DF_MMIO_REG_SET_COUNT; i++) {
if (is_mmio_reg_disabled(i))
return i;
}
@ -122,7 +122,7 @@ void data_fabric_set_mmio_np(void)
data_fabric_print_mmio_conf();
for (i = 0; i < NUM_NB_MMIO_REGS; i++) {
for (i = 0; i < DF_MMIO_REG_SET_COUNT; i++) {
/* Adjust all registers that overlap */
ctrl.raw = data_fabric_broadcast_read32(0, NB_MMIO_CONTROL(i));
if (!(ctrl.we || ctrl.re))

4
src/soc/amd/glinda/include/soc/data_fabric.h
View File

@ -11,14 +11,14 @@
#define D18F0_MMIO_SHIFT 16
#define D18F0_MMIO_CTRL0 0xD88
#define DF_MMIO_REG_SET_COUNT 8
#define DF_FICAA_BIOS 0x8C
#define DF_FICAD_LO 0xB8
#define DF_FICAD_HI 0xBC
#define IOMS0_FABRIC_ID 15
#define NUM_NB_MMIO_REGS 8
union df_mmio_control {
struct {
uint32_t re : 1; /* [ 0.. 0] */

4
src/soc/amd/mendocino/include/soc/data_fabric.h
View File

@ -11,14 +11,14 @@
#define D18F0_MMIO_SHIFT 16
#define D18F0_MMIO_CTRL0 0x208
#define DF_MMIO_REG_SET_COUNT 8
#define DF_FICAA_BIOS 0x5C
#define DF_FICAD_LO 0x98
#define DF_FICAD_HI 0x9C
#define IOMS0_FABRIC_ID 9
#define NUM_NB_MMIO_REGS 8
union df_mmio_control {
struct {
uint32_t re : 1; /* [ 0.. 0] */

4
src/soc/amd/phoenix/include/soc/data_fabric.h
View File

@ -11,14 +11,14 @@
#define D18F0_MMIO_SHIFT 16
#define D18F0_MMIO_CTRL0 0xD88
#define DF_MMIO_REG_SET_COUNT 8
#define DF_FICAA_BIOS 0x8C
#define DF_FICAD_LO 0xB8
#define DF_FICAD_HI 0xBC
#define IOMS0_FABRIC_ID 14
#define NUM_NB_MMIO_REGS 8
union df_mmio_control {
struct {
uint32_t re : 1; /* [ 0.. 0] */

4
src/soc/amd/picasso/include/soc/data_fabric.h
View File

@ -11,14 +11,14 @@
#define D18F0_MMIO_SHIFT 16
#define D18F0_MMIO_CTRL0 0x208
#define DF_MMIO_REG_SET_COUNT 8
#define DF_FICAA_BIOS 0x5C
#define DF_FICAD_LO 0x98
#define DF_FICAD_HI 0x9C
#define IOMS0_FABRIC_ID 9
#define NUM_NB_MMIO_REGS 8
union df_mmio_control {
struct {
uint32_t re : 1; /* [ 0.. 0] */