Drop GX1, CS5330 and related boards
There is no Cache As Ram for these boards, let's get rid of them. Change-Id: Ib41f8cd64fc9a440838aea86076d6514aacb301c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7117 Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This commit is contained in:
Stefan Reinauer
@@ -12,7 +12,6 @@ source src/cpu/amd/socket_S1G1/Kconfig
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source src/cpu/amd/model_fxx/Kconfig
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source src/cpu/amd/model_10xxx/Kconfig
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source src/cpu/amd/geode_gx1/Kconfig
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source src/cpu/amd/geode_gx2/Kconfig
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source src/cpu/amd/geode_lx/Kconfig
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@@ -8,7 +8,6 @@ subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2R2) += socket_AM2r2
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subdirs-$(CONFIG_CPU_AMD_SOCKET_AM3) += socket_AM3
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subdirs-$(CONFIG_CPU_AMD_SOCKET_ASB2) += socket_ASB2
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subdirs-$(CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA) += socket_C32
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subdirs-$(CONFIG_CPU_AMD_GEODE_GX1) += geode_gx1
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subdirs-$(CONFIG_CPU_AMD_GEODE_GX2) += geode_gx2
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subdirs-$(CONFIG_CPU_AMD_GEODE_LX) += geode_lx
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subdirs-$(CONFIG_CPU_AMD_SC520) += sc520
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@@ -1,36 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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config CPU_AMD_GEODE_GX1
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bool
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select ARCH_BOOTBLOCK_X86_32
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select ARCH_ROMSTAGE_X86_32
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select ARCH_RAMSTAGE_X86_32
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if CPU_AMD_GEODE_GX1
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config DCACHE_RAM_BASE
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hex
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default 0xc0000
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config DCACHE_RAM_SIZE
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hex
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default 0x01000
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endif # CPU_AMD_GEODE_GX1
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@@ -1,28 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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subdirs-y += ../../x86/tsc
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subdirs-y += ../../x86/lapic
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subdirs-y += ../../x86/cache
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subdirs-y += ../../x86/smm
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ramstage-y += geode_gx1_init.c
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cpu_incs += $(src)/cpu/amd/geode_gx1/cpu_setup.inc
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cpu_incs += $(src)/cpu/amd/geode_gx1/gx_setup.inc
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@@ -1,68 +0,0 @@
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/*
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freebios/src/northbridge/nsc/gx1/cpu_setup.inc
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Copyright (c) 2002 Christer Weinigel <wingel@hack.org>
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Initialize the GX1 CPU configuration registers
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*/
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/* USES: esi, ecx, eax */
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#include <cpu/amd/gx1def.h>
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movl %eax, %ebp /* preserve bist */
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cpu_setup_start:
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leal cpu_setup_table, %esi
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movl $cpu_setup_len, %ecx
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cpu_setup_loop:
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movw (%esi), %ax
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addl $2, %esi
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outb %al, $0x22
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movb %ah, %al
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outb %al, $0x23
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loop cpu_setup_loop
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movb $0xff, %al /* DIR1 -- Identification Register 1 */
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outb %al, $0x22
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inb $0x23, %al
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cmpb $0x63, %al /* Revision for GXLV rev 3 */
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jbe cpu_no_ccr4
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movb $0xe8, %al /* CCR4 */
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outb %al, $0x22
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inb $0x23, %al
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orb $0x20, %al /* Enable FPU Fast Mode */
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outb %al, $0x23
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movb $0xf0, %al /* PCR1 --- Performace Control */
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outb %al, $0x22
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inb $0x23, %al
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orb $0x02, %al /* Incrementor on, whatever that is */
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outb %al, $0x23
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movb $0x20, %al /* PCR0 --- Performace Control */
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outb %al, $0x22
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inb $0x23, %al
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orb $0x20, %al /* Must be 1 according to data book */
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orb $0x04, %al /* Incrementor Margin 10 */
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outb %al, $0x23
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cpu_no_ccr4:
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jmp cpu_setup_end
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cpu_setup_table:
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.byte 0xc1, 0x00 /* NO SMIs */
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.byte 0xc3, 0x14 /* Enable CPU config register */
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.byte 0x20, 0x00
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.byte 0xb8, GX_BASE>>30 /* Enable GXBASE address */
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.byte 0xc2, 0x00
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.byte 0xe8, 0x98
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.byte 0xc3, 0xf8 /* Enable CPU config register */
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cpu_setup_len = (.-cpu_setup_table)/2
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cpu_setup_end:
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nop
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movl %ebp, %eax /* Restore bist */
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@@ -1,100 +0,0 @@
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#include <console/console.h>
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#include <device/device.h>
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#include <string.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/cache.h>
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#if 0
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#include <cpu/amd/gx1def.h>
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#include <arch/io.h>
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static void gx1_cpu_setup(void)
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{
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unsigned char rreg;
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unsigned char cpu_table[] = {
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0xc1, 0x00, /* NO SMIs */
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0xc3, 0x14, /* Enable CPU config register */
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0x20, 0x00, /* */
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0xb8, GX_BASE>>30, /* Enable GXBASE address */
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0xc2, 0x00,
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0xe8, 0x98,
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0xc3, 0xf8, /* Enable CPU config register */
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0x00, 0x00
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};
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unsigned char *cPtr = cpu_table;
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while(rreg = *cPtr++) {
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unsigned char rval = *cPtr++;
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outb(rreg, 0x22);
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outb(rval, 0x23);
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}
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outb(0xff, 0x22); /* DIR1 -- Identification register 1 */
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if(inb(0x23) > 0x63) { /* Rev greater than R3 */
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outb(0xe8, 0x22);
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outb(inb(0x23) | 0x20, 0x23); /* Enable FPU Fast Mode */
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outb(0xf0, 0x22);
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outb(inb(0x23) | 0x02, 0x23); /* Incrementor on */
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outb(0x20, 0x22);
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outb(inb(0x23) | 0x24, 0x23); /* Bit 5 must be on */
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/* Bit 2 Incrementor margin 10 */
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}
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}
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static void gx1_gx_setup(void)
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{
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unsigned long gx_setup_table[] = {
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GX_BASE + DC_UNLOCK, DC_UNLOCK_MAGIC,
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GX_BASE + DC_GENERAL_CFG, 0,
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GX_BASE + DC_UNLOCK, 0,
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GX_BASE + BC_DRAM_TOP, 0x3fffffff,
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GX_BASE + BC_XMAP_1, 0x60,
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GX_BASE + BC_XMAP_2, 0,
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GX_BASE + BC_XMAP_3, 0,
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GX_BASE + MC_BANK_CFG, 0x00700070,
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GX_BASE + MC_MEM_CNTRL1, XBUSARB,
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GX_BASE + MC_GBASE_ADD, 0xff,
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0, 0
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};
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unsigned long *gxPtr = gx_setup_table;
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unsigned long *gxdPtr;
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unsigned long addr;
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while(addr = *gxPtr++) {
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gxdPtr = (unsigned long *)addr;
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*gxdPtr = *gxPtr++;
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}
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}
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#endif
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static void geode_gx1_init(device_t dev)
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{
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#if 0
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gx1_cpu_setup();
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gx1_gx_setup();
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#endif
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/* Turn on caching if we haven't already */
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x86_enable_cache();
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/* Enable the local cpu apics */
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setup_lapic();
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};
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static struct device_operations cpu_dev_ops = {
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.init = geode_gx1_init,
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};
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static struct cpu_device_id cpu_table[] = {
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{ X86_VENDOR_CYRIX, 0x0540 },
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{ 0, 0 },
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};
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static const struct cpu_driver driver __cpu_driver = {
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.ops = &cpu_dev_ops,
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.id_table = cpu_table,
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};
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@@ -1,47 +0,0 @@
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/*
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freebios/src/northbridge/nsc/gx1/gx_setup.inc
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Copyright (c) 2002 Christer Weinigel <wingel@hack.org>
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Setup the GX_BASE registers on a National Semiconductor Geode CPU
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*/
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#include <cpu/amd/gx1def.h>
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movl %eax, %ebp /* Preserve bist */
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gx_setup_start:
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leal gx_setup_table, %esi
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movl $gx_setup_len, %ecx
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movl $GX_BASE, %edi
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gx_setup_loop:
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movw (%esi), %di /* Only read the low word of address */
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addl $4, %esi
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movl (%esi), %eax /* Data */
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addl $4, %esi
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movl %eax, (%edi)
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loop gx_setup_loop
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jmp gx_setup_end
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gx_setup_table:
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/* Allow writes to config registers */
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.long DC_UNLOCK, DC_UNLOCK_MAGIC
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.long DC_GENERAL_CFG, 0
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.long DC_UNLOCK, 0
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.long BC_DRAM_TOP, 0x3fffffff
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.long BC_XMAP_1, 0x60
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.long BC_XMAP_2, 0
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.long BC_XMAP_3, 0
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.long MC_BANK_CFG, 0x00700070 /* No DIMMS installed */
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.long MC_MEM_CNTRL1, XBUSARB
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.long MC_GBASE_ADD, 0x7ff /* Almost 1GB */
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gx_setup_len = (.-gx_setup_table)/8
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gx_setup_end:
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nop
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movl %ebp, %eax /* Restore bist */
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