Drop GX1, CS5330 and related boards
There is no Cache As Ram for these boards, let's get rid of them. Change-Id: Ib41f8cd64fc9a440838aea86076d6514aacb301c Signed-off-by: Stefan Reinauer <stefan.reinauer@coreboot.org> Reviewed-on: http://review.coreboot.org/7117 Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This commit is contained in:
@@ -12,7 +12,6 @@ source src/cpu/amd/socket_S1G1/Kconfig
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source src/cpu/amd/model_fxx/Kconfig
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source src/cpu/amd/model_10xxx/Kconfig
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source src/cpu/amd/geode_gx1/Kconfig
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source src/cpu/amd/geode_gx2/Kconfig
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source src/cpu/amd/geode_lx/Kconfig
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@@ -8,7 +8,6 @@ subdirs-$(CONFIG_CPU_AMD_SOCKET_AM2R2) += socket_AM2r2
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subdirs-$(CONFIG_CPU_AMD_SOCKET_AM3) += socket_AM3
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subdirs-$(CONFIG_CPU_AMD_SOCKET_ASB2) += socket_ASB2
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subdirs-$(CONFIG_CPU_AMD_SOCKET_C32_NON_AGESA) += socket_C32
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subdirs-$(CONFIG_CPU_AMD_GEODE_GX1) += geode_gx1
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subdirs-$(CONFIG_CPU_AMD_GEODE_GX2) += geode_gx2
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subdirs-$(CONFIG_CPU_AMD_GEODE_LX) += geode_lx
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subdirs-$(CONFIG_CPU_AMD_SC520) += sc520
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@@ -1,36 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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config CPU_AMD_GEODE_GX1
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bool
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select ARCH_BOOTBLOCK_X86_32
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select ARCH_ROMSTAGE_X86_32
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select ARCH_RAMSTAGE_X86_32
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if CPU_AMD_GEODE_GX1
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config DCACHE_RAM_BASE
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hex
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default 0xc0000
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config DCACHE_RAM_SIZE
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hex
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default 0x01000
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endif # CPU_AMD_GEODE_GX1
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@@ -1,28 +0,0 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; either version 2 of the License, or
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## (at your option) any later version.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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subdirs-y += ../../x86/tsc
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subdirs-y += ../../x86/lapic
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subdirs-y += ../../x86/cache
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subdirs-y += ../../x86/smm
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ramstage-y += geode_gx1_init.c
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cpu_incs += $(src)/cpu/amd/geode_gx1/cpu_setup.inc
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cpu_incs += $(src)/cpu/amd/geode_gx1/gx_setup.inc
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@@ -1,68 +0,0 @@
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/*
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freebios/src/northbridge/nsc/gx1/cpu_setup.inc
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Copyright (c) 2002 Christer Weinigel <wingel@hack.org>
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Initialize the GX1 CPU configuration registers
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*/
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/* USES: esi, ecx, eax */
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#include <cpu/amd/gx1def.h>
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movl %eax, %ebp /* preserve bist */
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cpu_setup_start:
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leal cpu_setup_table, %esi
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movl $cpu_setup_len, %ecx
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cpu_setup_loop:
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movw (%esi), %ax
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addl $2, %esi
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outb %al, $0x22
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movb %ah, %al
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outb %al, $0x23
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loop cpu_setup_loop
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movb $0xff, %al /* DIR1 -- Identification Register 1 */
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outb %al, $0x22
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inb $0x23, %al
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cmpb $0x63, %al /* Revision for GXLV rev 3 */
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jbe cpu_no_ccr4
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movb $0xe8, %al /* CCR4 */
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outb %al, $0x22
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inb $0x23, %al
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orb $0x20, %al /* Enable FPU Fast Mode */
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outb %al, $0x23
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movb $0xf0, %al /* PCR1 --- Performace Control */
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outb %al, $0x22
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inb $0x23, %al
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orb $0x02, %al /* Incrementor on, whatever that is */
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outb %al, $0x23
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movb $0x20, %al /* PCR0 --- Performace Control */
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outb %al, $0x22
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inb $0x23, %al
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orb $0x20, %al /* Must be 1 according to data book */
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orb $0x04, %al /* Incrementor Margin 10 */
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outb %al, $0x23
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cpu_no_ccr4:
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jmp cpu_setup_end
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cpu_setup_table:
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.byte 0xc1, 0x00 /* NO SMIs */
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.byte 0xc3, 0x14 /* Enable CPU config register */
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.byte 0x20, 0x00
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.byte 0xb8, GX_BASE>>30 /* Enable GXBASE address */
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.byte 0xc2, 0x00
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.byte 0xe8, 0x98
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.byte 0xc3, 0xf8 /* Enable CPU config register */
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cpu_setup_len = (.-cpu_setup_table)/2
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cpu_setup_end:
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nop
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movl %ebp, %eax /* Restore bist */
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@@ -1,100 +0,0 @@
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#include <console/console.h>
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#include <device/device.h>
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#include <string.h>
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#include <cpu/cpu.h>
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#include <cpu/x86/lapic.h>
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#include <cpu/x86/cache.h>
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#if 0
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#include <cpu/amd/gx1def.h>
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#include <arch/io.h>
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static void gx1_cpu_setup(void)
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{
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unsigned char rreg;
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unsigned char cpu_table[] = {
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0xc1, 0x00, /* NO SMIs */
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0xc3, 0x14, /* Enable CPU config register */
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0x20, 0x00, /* */
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0xb8, GX_BASE>>30, /* Enable GXBASE address */
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0xc2, 0x00,
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0xe8, 0x98,
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0xc3, 0xf8, /* Enable CPU config register */
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0x00, 0x00
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};
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unsigned char *cPtr = cpu_table;
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while(rreg = *cPtr++) {
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unsigned char rval = *cPtr++;
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outb(rreg, 0x22);
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outb(rval, 0x23);
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}
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outb(0xff, 0x22); /* DIR1 -- Identification register 1 */
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if(inb(0x23) > 0x63) { /* Rev greater than R3 */
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outb(0xe8, 0x22);
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outb(inb(0x23) | 0x20, 0x23); /* Enable FPU Fast Mode */
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outb(0xf0, 0x22);
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outb(inb(0x23) | 0x02, 0x23); /* Incrementor on */
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outb(0x20, 0x22);
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outb(inb(0x23) | 0x24, 0x23); /* Bit 5 must be on */
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/* Bit 2 Incrementor margin 10 */
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}
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}
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static void gx1_gx_setup(void)
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{
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unsigned long gx_setup_table[] = {
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GX_BASE + DC_UNLOCK, DC_UNLOCK_MAGIC,
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GX_BASE + DC_GENERAL_CFG, 0,
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GX_BASE + DC_UNLOCK, 0,
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GX_BASE + BC_DRAM_TOP, 0x3fffffff,
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GX_BASE + BC_XMAP_1, 0x60,
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GX_BASE + BC_XMAP_2, 0,
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GX_BASE + BC_XMAP_3, 0,
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GX_BASE + MC_BANK_CFG, 0x00700070,
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GX_BASE + MC_MEM_CNTRL1, XBUSARB,
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GX_BASE + MC_GBASE_ADD, 0xff,
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0, 0
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};
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unsigned long *gxPtr = gx_setup_table;
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unsigned long *gxdPtr;
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unsigned long addr;
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while(addr = *gxPtr++) {
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gxdPtr = (unsigned long *)addr;
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*gxdPtr = *gxPtr++;
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}
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}
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#endif
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static void geode_gx1_init(device_t dev)
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{
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#if 0
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gx1_cpu_setup();
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gx1_gx_setup();
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#endif
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/* Turn on caching if we haven't already */
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x86_enable_cache();
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/* Enable the local cpu apics */
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setup_lapic();
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};
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static struct device_operations cpu_dev_ops = {
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.init = geode_gx1_init,
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};
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static struct cpu_device_id cpu_table[] = {
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{ X86_VENDOR_CYRIX, 0x0540 },
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{ 0, 0 },
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};
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static const struct cpu_driver driver __cpu_driver = {
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.ops = &cpu_dev_ops,
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.id_table = cpu_table,
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};
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@@ -1,47 +0,0 @@
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/*
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freebios/src/northbridge/nsc/gx1/gx_setup.inc
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Copyright (c) 2002 Christer Weinigel <wingel@hack.org>
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Setup the GX_BASE registers on a National Semiconductor Geode CPU
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*/
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#include <cpu/amd/gx1def.h>
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movl %eax, %ebp /* Preserve bist */
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gx_setup_start:
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leal gx_setup_table, %esi
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movl $gx_setup_len, %ecx
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movl $GX_BASE, %edi
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gx_setup_loop:
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movw (%esi), %di /* Only read the low word of address */
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addl $4, %esi
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movl (%esi), %eax /* Data */
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addl $4, %esi
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movl %eax, (%edi)
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loop gx_setup_loop
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jmp gx_setup_end
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gx_setup_table:
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/* Allow writes to config registers */
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.long DC_UNLOCK, DC_UNLOCK_MAGIC
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.long DC_GENERAL_CFG, 0
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.long DC_UNLOCK, 0
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.long BC_DRAM_TOP, 0x3fffffff
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.long BC_XMAP_1, 0x60
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.long BC_XMAP_2, 0
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.long BC_XMAP_3, 0
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.long MC_BANK_CFG, 0x00700070 /* No DIMMS installed */
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.long MC_MEM_CNTRL1, XBUSARB
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.long MC_GBASE_ADD, 0x7ff /* Almost 1GB */
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gx_setup_len = (.-gx_setup_table)/8
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gx_setup_end:
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nop
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movl %ebp, %eax /* Restore bist */
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@@ -1,54 +0,0 @@
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/*
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freebios/src/northbridge/nsc/gx1/gx1def.inc
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Copyright (c) 2002 Christer Weinigel <wingel@hack.org>
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Defines for the GX1 processor
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*/
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#define GX_BASE 0x040000000
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/**********************************************************************/
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/* Display Controller Registers, offset from GX_BASE */
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#define DC_UNLOCK 0x8300
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#define DC_UNLOCK_MAGIC 0x4758
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#define DC_GENERAL_CFG 0x8304
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/**********************************************************************/
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/* Bus Controller Registers, offset from GX_BASE */
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#define BC_DRAM_TOP 0x8000
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#define BC_XMAP_1 0x8004
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#define BC_XMAP_2 0x8008
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#define BC_XMAP_3 0x800c
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/**********************************************************************/
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/* Memory Controller Registers, offset from GX_BASE */
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#define MC_MEM_CNTRL1 0x8400
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#define SDCLKSTRT (1<<17)
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#define RFSHRATE (0x1ff<<8)
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#define RFSHSTAG (0x3<<6)
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#define X2CLKADDR (1<<5)
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#define RFSHTST (1<<4)
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#define XBUSARB (1<<3)
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#define SMM_MAP (1<<2)
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#define PROGRAM_SDRAM (1<<0)
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|
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#define MC_MEM_CNTRL2 0x8404
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#define SDCLK_MASK 0x000003c0
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#define SDCLKOUT_MASK 0x00000400
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#define MC_BANK_CFG 0x8408
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#define DIMM_PG_SZ 0x00000070
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#define DIMM_SZ 0x00000700
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#define DIMM_COMP_BNK 0x00001000
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#define DIMM_MOD_BNK 0x00004000
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|
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#define MC_SYNC_TIM1 0x840c
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|
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#define MC_GBASE_ADD 0x8414
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||||
|
@@ -12,8 +12,6 @@ config VENDOR_ADLINK
|
||||
bool "ADLINK"
|
||||
config VENDOR_ADVANSUS
|
||||
bool "Advansus"
|
||||
config VENDOR_ADVANTECH
|
||||
bool "Advantech"
|
||||
config VENDOR_AMD
|
||||
bool "AMD"
|
||||
config VENDOR_AOPEN
|
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@@ -24,8 +22,6 @@ config VENDOR_ARIMA
|
||||
bool "Arima"
|
||||
config VENDOR_ARTECGROUP
|
||||
bool "Artec Group"
|
||||
config VENDOR_ASI
|
||||
bool "ASI"
|
||||
config VENDOR_ASROCK
|
||||
bool "ASROCK"
|
||||
config VENDOR_ASUS
|
||||
@@ -34,8 +30,6 @@ config VENDOR_A_TREND
|
||||
bool "A-Trend"
|
||||
config VENDOR_AVALUE
|
||||
bool "AVALUE"
|
||||
config VENDOR_AXUS
|
||||
bool "AXUS"
|
||||
config VENDOR_AZZA
|
||||
bool "AZZA"
|
||||
config VENDOR_BACHMANN
|
||||
@@ -56,8 +50,6 @@ config VENDOR_DIGITALLOGIC
|
||||
bool "DIGITAL-LOGIC"
|
||||
config VENDOR_DMP
|
||||
bool "DMP"
|
||||
config VENDOR_EAGLELION
|
||||
bool "EagleLion"
|
||||
config VENDOR_ECS
|
||||
bool "ECS"
|
||||
config VENDOR_EMULATION
|
||||
@@ -130,8 +122,6 @@ config VENDOR_TECHNEXION
|
||||
bool "Technexion"
|
||||
config VENDOR_TECHNOLOGIC
|
||||
bool "Technologic"
|
||||
config VENDOR_TELEVIDEO
|
||||
bool "TeleVideo"
|
||||
config VENDOR_TI
|
||||
bool "TI"
|
||||
config VENDOR_THOMSON
|
||||
@@ -154,17 +144,14 @@ source "src/mainboard/aaeon/Kconfig"
|
||||
source "src/mainboard/abit/Kconfig"
|
||||
source "src/mainboard/adlink/Kconfig"
|
||||
source "src/mainboard/advansus/Kconfig"
|
||||
source "src/mainboard/advantech/Kconfig"
|
||||
source "src/mainboard/amd/Kconfig"
|
||||
source "src/mainboard/aopen/Kconfig"
|
||||
source "src/mainboard/apple/Kconfig"
|
||||
source "src/mainboard/arima/Kconfig"
|
||||
source "src/mainboard/artecgroup/Kconfig"
|
||||
source "src/mainboard/asi/Kconfig"
|
||||
source "src/mainboard/asrock/Kconfig"
|
||||
source "src/mainboard/asus/Kconfig"
|
||||
source "src/mainboard/avalue/Kconfig"
|
||||
source "src/mainboard/axus/Kconfig"
|
||||
source "src/mainboard/azza/Kconfig"
|
||||
source "src/mainboard/bachmann/Kconfig"
|
||||
source "src/mainboard/bcom/Kconfig"
|
||||
@@ -175,7 +162,6 @@ source "src/mainboard/compaq/Kconfig"
|
||||
source "src/mainboard/cubietech/Kconfig"
|
||||
source "src/mainboard/digitallogic/Kconfig"
|
||||
source "src/mainboard/dmp/Kconfig"
|
||||
source "src/mainboard/eaglelion/Kconfig"
|
||||
source "src/mainboard/ecs/Kconfig"
|
||||
source "src/mainboard/emulation/Kconfig"
|
||||
source "src/mainboard/getac/Kconfig"
|
||||
@@ -212,7 +198,6 @@ source "src/mainboard/sunw/Kconfig"
|
||||
source "src/mainboard/supermicro/Kconfig"
|
||||
source "src/mainboard/technexion/Kconfig"
|
||||
source "src/mainboard/technologic/Kconfig"
|
||||
source "src/mainboard/televideo/Kconfig"
|
||||
source "src/mainboard/thomson/Kconfig"
|
||||
source "src/mainboard/ti/Kconfig"
|
||||
source "src/mainboard/traverse/Kconfig"
|
||||
|
@@ -1,35 +0,0 @@
|
||||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
if VENDOR_ADVANTECH
|
||||
|
||||
choice
|
||||
prompt "Mainboard model"
|
||||
|
||||
config BOARD_ADVANTECH_PCM_5820
|
||||
bool "PCM-5820"
|
||||
|
||||
endchoice
|
||||
|
||||
source "src/mainboard/advantech/pcm-5820/Kconfig"
|
||||
|
||||
config MAINBOARD_VENDOR
|
||||
string
|
||||
default "Advantech"
|
||||
|
||||
endif # VENDOR_ADVANTECH
|
@@ -1,45 +0,0 @@
|
||||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
if BOARD_ADVANTECH_PCM_5820
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
select CPU_AMD_GEODE_GX1
|
||||
select NORTHBRIDGE_AMD_GX1
|
||||
select SOUTHBRIDGE_AMD_CS5530
|
||||
select SUPERIO_WINBOND_W83977F
|
||||
select ROMCC
|
||||
select HAVE_PIRQ_TABLE
|
||||
select PIRQ_ROUTE
|
||||
select UDELAY_TSC
|
||||
select BOARD_ROMSIZE_KB_256
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default advantech/pcm-5820
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "PCM-5820"
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 2
|
||||
|
||||
endif # BOARD_ADVANTECH_PCM_5820
|
@@ -1,5 +0,0 @@
|
||||
Category: half
|
||||
Board URL: http://taiwan.advantech.com.tw/products/Model_Detail.asp?model_id=1-1TGZL8
|
||||
ROM package: PLCC32
|
||||
ROM socketed: y
|
||||
Flashrom support: y
|
@@ -1,56 +0,0 @@
|
||||
chip northbridge/amd/gx1 # Northbridge
|
||||
device domain 0 on # PCI domain
|
||||
device pci 0.0 on end # Host bridge
|
||||
chip southbridge/amd/cs5530 # Southbridge
|
||||
device pci 12.0 on # ISA bridge
|
||||
chip superio/winbond/w83977f # SUper I/O
|
||||
device pnp 3f0.0 on # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 3f0.1 on # Parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 3f0.2 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 3f0.3 on # COM2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 3f0.4 on # RTC / On-Now control
|
||||
io 0x60 = 0x70
|
||||
irq 0x70 = 8
|
||||
end
|
||||
device pnp 3f0.5 on # PS/2 keyboard / mouse
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1 # PS/2 keyboard interrupt
|
||||
irq 0x72 = 12 # PS/2 mouse interrupt
|
||||
end
|
||||
device pnp 3f0.6 on # IR
|
||||
# TODO?
|
||||
end
|
||||
device pnp 3f0.7 on # GPIO 1
|
||||
# TODO?
|
||||
end
|
||||
device pnp 3f0.8 on # GPIO 2
|
||||
# TODO?
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 12.1 on end # SMI
|
||||
device pci 12.2 on end # IDE
|
||||
device pci 12.3 on end # Audio (onboard)
|
||||
device pci 12.4 on end # VGA
|
||||
device pci 13.0 on end # USB
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
end
|
||||
end
|
||||
chip cpu/amd/geode_gx1 # CPU
|
||||
end
|
||||
end
|
@@ -1,45 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
static const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE,
|
||||
PIRQ_VERSION,
|
||||
32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
|
||||
0x00, /* Interrupt router bus */
|
||||
(0x12 << 3) | 0x0, /* Interrupt router device */
|
||||
0xc00, /* IRQs devoted exclusively to PCI usage */
|
||||
0x1078, /* Vendor */
|
||||
0x2, /* Device */
|
||||
0, /* Miniport data */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0xde, /* Checksum */
|
||||
{
|
||||
/* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
{0x00, (0x0b << 3) | 0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},
|
||||
{0x00, (0x13 << 3) | 0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
|
||||
}
|
||||
};
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
|
||||
}
|
@@ -1,40 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <console/console.h>
|
||||
#include "northbridge/amd/gx1/raminit.c"
|
||||
#include "cpu/x86/bist.h"
|
||||
#include "superio/winbond/w83977f/early_serial.c"
|
||||
#include "southbridge/amd/cs5530/enable_rom.c"
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x3f0, W83977F_SP1)
|
||||
|
||||
#include <cpu/intel/romstage.h>
|
||||
static void main(unsigned long bist)
|
||||
{
|
||||
w83977f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
report_bist_failure(bist);
|
||||
cs5530_enable_rom();
|
||||
sdram_init();
|
||||
}
|
@@ -1,38 +0,0 @@
|
||||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
if VENDOR_ASI
|
||||
|
||||
choice
|
||||
prompt "Mainboard model"
|
||||
|
||||
config BOARD_ASI_MB_5BLGP
|
||||
bool "MB-5BLGP"
|
||||
config BOARD_ASI_MB_5BLMP
|
||||
bool "MB-5BLMP"
|
||||
|
||||
endchoice
|
||||
|
||||
source "src/mainboard/asi/mb_5blgp/Kconfig"
|
||||
source "src/mainboard/asi/mb_5blmp/Kconfig"
|
||||
|
||||
config MAINBOARD_VENDOR
|
||||
string
|
||||
default "ASI"
|
||||
|
||||
endif # VENDOR_ASI
|
@@ -1,45 +0,0 @@
|
||||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
if BOARD_ASI_MB_5BLGP
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
select CPU_AMD_GEODE_GX1
|
||||
select NORTHBRIDGE_AMD_GX1
|
||||
select SOUTHBRIDGE_AMD_CS5530
|
||||
select SUPERIO_NSC_PC87351
|
||||
select ROMCC
|
||||
select HAVE_PIRQ_TABLE
|
||||
select PIRQ_ROUTE
|
||||
select UDELAY_TSC
|
||||
select BOARD_ROMSIZE_KB_256
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default asi/mb_5blgp
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "MB-5BLGP"
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 3
|
||||
|
||||
endif # BOARD_ASI_MB_5BLGP
|
@@ -1,2 +0,0 @@
|
||||
Board name: MB-5BLGP (Neoware Eon 4000s)
|
||||
Category: settop
|
@@ -1,55 +0,0 @@
|
||||
chip northbridge/amd/gx1 # Northbridge
|
||||
device domain 0 on # PCI domain
|
||||
device pci 0.0 on end # Host bridge
|
||||
chip southbridge/amd/cs5530 # Southbridge
|
||||
device pci 0f.0 on end # Ethernet
|
||||
device pci 12.0 on # ISA bridge
|
||||
chip superio/nsc/pc87351 # Super I/O
|
||||
device pnp 2e.0 off # Floppy
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.1 on # Parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.2 on # COM2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.e on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.4 on # System wake-up control (SWC)
|
||||
irq 0x60 = 0x500
|
||||
end
|
||||
device pnp 2e.5 on # PS/2 mouse
|
||||
irq 0x70 = 12
|
||||
end
|
||||
device pnp 2e.6 on # PS/2 keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 2e.7 on # GPIO
|
||||
irq 0x60 = 0x800
|
||||
end
|
||||
device pnp 2e.8 on # Fan speed control
|
||||
irq 0x60 = 0x900
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 12.1 off end # SMI
|
||||
device pci 12.2 on end # IDE
|
||||
device pci 12.3 on end # Audio
|
||||
device pci 12.4 on end # VGA
|
||||
device pci 13.0 on end # USB
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "0" # No connector on this board
|
||||
end
|
||||
end
|
||||
chip cpu/amd/geode_gx1 # CPU
|
||||
end
|
||||
end
|
@@ -1,46 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
static const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE,
|
||||
PIRQ_VERSION,
|
||||
32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. number of devices on the bus */
|
||||
0x00, /* Interrupt router bus */
|
||||
(0x12 << 3) | 0x0, /* Interrupt router device */
|
||||
0x8800, /* IRQs devoted exclusively to PCI usage */
|
||||
0x1078, /* Vendor */
|
||||
0x2, /* Device */
|
||||
0, /* Miniport data */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0x96, /* Checksum */
|
||||
{
|
||||
/* bus, dev | fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
{0x00, (0x07 << 3) | 0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0}, /* ISA slot (?) */
|
||||
{0x00, (0x0f << 3) | 0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0}, /* NIC */
|
||||
{0x00, (0x13 << 3) | 0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0}, /* USB */
|
||||
}
|
||||
};
|
||||
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
|
||||
}
|
@@ -1,40 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2008 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <console/console.h>
|
||||
#include "northbridge/amd/gx1/raminit.c"
|
||||
#include "cpu/x86/bist.h"
|
||||
#include "superio/nsc/pc87351/early_serial.c"
|
||||
#include "southbridge/amd/cs5530/enable_rom.c"
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1)
|
||||
|
||||
#include <cpu/intel/romstage.h>
|
||||
static void main(unsigned long bist)
|
||||
{
|
||||
pc87351_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
report_bist_failure(bist);
|
||||
cs5530_enable_rom();
|
||||
sdram_init();
|
||||
}
|
@@ -1,45 +0,0 @@
|
||||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
if BOARD_ASI_MB_5BLMP
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
select CPU_AMD_GEODE_GX1
|
||||
select NORTHBRIDGE_AMD_GX1
|
||||
select SOUTHBRIDGE_AMD_CS5530
|
||||
select SUPERIO_NSC_PC87351
|
||||
select ROMCC
|
||||
select HAVE_PIRQ_TABLE
|
||||
select PIRQ_ROUTE
|
||||
select UDELAY_TSC
|
||||
select BOARD_ROMSIZE_KB_256
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default asi/mb_5blmp
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "MB-5BLMP"
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 5
|
||||
|
||||
endif # BOARD_ASI_MB_5BLMP
|
@@ -1,4 +0,0 @@
|
||||
Board name: MB-5BLMP (IGEL WinNET III)
|
||||
Category: settop
|
||||
Board URL: http://www.hojerteknik.com/winnet.htm
|
||||
Flashrom support: y
|
@@ -1,48 +0,0 @@
|
||||
chip northbridge/amd/gx1 # Northbridge
|
||||
device domain 0 on
|
||||
device pci 0.0 on end # Host bridge
|
||||
chip southbridge/amd/cs5530 # Southbridge
|
||||
device pci 0f.0 off end # Ethernet (Realtek RTL8139B)
|
||||
device pci 12.0 on # ISA bridge
|
||||
chip superio/nsc/pc87351 # Super I/O
|
||||
device pnp 2e.4 on # PS/2 keyboard (+ mouse?)
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
# irq 0x72 = 12
|
||||
end
|
||||
device pnp 2e.a on # PS/2 mouse
|
||||
irq 0x70 = 12
|
||||
end
|
||||
device pnp 2e.e on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.f off # Floppy
|
||||
io 0x60 = 0x3f2
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.10 on # Parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.12 on # COM2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 12.1 off end # SMI
|
||||
device pci 12.2 on end # IDE
|
||||
device pci 12.3 on end # Audio
|
||||
device pci 12.4 on end # VGA (onboard)
|
||||
device pci 13.0 on end # USB
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "1"
|
||||
end
|
||||
end
|
||||
chip cpu/amd/geode_gx1 # CPU
|
||||
end
|
||||
end
|
||||
|
@@ -1,39 +0,0 @@
|
||||
/* TODO: This is currently copied from the IEI NOVA-4899R target, but it's
|
||||
* quite surely wrong for this board. It gets me further in the boot process
|
||||
* than using no irq_tables.c file at all, though!
|
||||
*/
|
||||
|
||||
/* TODO: Add license header. */
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
static const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
|
||||
0x00, /* Where the interrupt router lies (bus) */
|
||||
(0x12<<3)|0x0, /* Where the interrupt router lies (dev) */
|
||||
0xe00, /* IRQs devoted exclusively to PCI usage */
|
||||
0x1078, /* Vendor */
|
||||
0x0002, /* Device */
|
||||
0, /* Miniport data */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0x2d, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||
{
|
||||
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
// USB
|
||||
{0x00,(0x13<<3)|0x0, {{0x01, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
|
||||
// eth0
|
||||
{0x00,(0x0a<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},//0x3, 0x0},
|
||||
// eth1
|
||||
{0x00,(0x0b<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x02, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},//0x2, 0x0},
|
||||
// eth2
|
||||
{0x00,(0x0c<<3)|0x0, {{0x04, 0xdeb8}, {0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},//0x1, 0x0},
|
||||
// PCI slot
|
||||
{0x00,(0x0f<<3)|0x0, {{0x04, 0xdeb8}, {0x03, 0xdeb8}, {0x02, 0xdeb8}, {0x00, 0x0deb8}}, 0x0, 0x0},
|
||||
}
|
||||
};
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
|
||||
}
|
@@ -1,41 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <console/console.h>
|
||||
#include "northbridge/amd/gx1/raminit.c"
|
||||
#include "superio/nsc/pc87351/early_serial.c"
|
||||
#include "cpu/x86/bist.h"
|
||||
#include "southbridge/amd/cs5530/enable_rom.c"
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, PC87351_SP1)
|
||||
|
||||
#include <cpu/intel/romstage.h>
|
||||
static void main(unsigned long bist)
|
||||
{
|
||||
pc87351_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
report_bist_failure(bist);
|
||||
cs5530_enable_rom();
|
||||
sdram_init();
|
||||
}
|
@@ -1,35 +0,0 @@
|
||||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
if VENDOR_AXUS
|
||||
|
||||
choice
|
||||
prompt "Mainboard model"
|
||||
|
||||
config BOARD_AXUS_TC320
|
||||
bool "TC320"
|
||||
|
||||
endchoice
|
||||
|
||||
source "src/mainboard/axus/tc320/Kconfig"
|
||||
|
||||
config MAINBOARD_VENDOR
|
||||
string
|
||||
default "AXUS"
|
||||
|
||||
endif # VENDOR_AXUS
|
@@ -1,46 +0,0 @@
|
||||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
if BOARD_AXUS_TC320
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
select CPU_AMD_GEODE_GX1
|
||||
select NORTHBRIDGE_AMD_GX1
|
||||
select SOUTHBRIDGE_AMD_CS5530
|
||||
select SUPERIO_NSC_PC97317
|
||||
select ROMCC
|
||||
select HAVE_PIRQ_TABLE
|
||||
select PIRQ_ROUTE
|
||||
select UDELAY_TSC
|
||||
select BOARD_ROMSIZE_KB_256
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default axus/tc320
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "TC320"
|
||||
|
||||
# Soldered NIC, internal USB, no real PCI slots.
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 2
|
||||
|
||||
endif # BOARD_AXUS_TC320
|
@@ -1,2 +0,0 @@
|
||||
Category: settop
|
||||
Board URL: http://www.keyton.co.jp/products/UAXT/TC-320.html
|
@@ -1,55 +0,0 @@
|
||||
chip northbridge/amd/gx1 # Northbridge
|
||||
device domain 0 on # PCI domain
|
||||
device pci 0.0 on end # Host bridge
|
||||
chip southbridge/amd/cs5530 # Southbridge
|
||||
device pci 12.0 on # ISA bridge
|
||||
chip superio/nsc/pc97317 # Super I/O
|
||||
device pnp 2e.0 on # PS/2 keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 2e.1 on # PS/2 mouse
|
||||
irq 0x70 = 12
|
||||
end
|
||||
device pnp 2e.2 on # RTC, advanced power control (APC)
|
||||
io 0x60 = 0x70
|
||||
irq 0x70 = 8
|
||||
end
|
||||
device pnp 2e.3 off # Floppy (N/A on this board)
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.4 on # Parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.5 off # COM2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.6 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.7 on # GPIO
|
||||
io 0x60 = 0xe0
|
||||
end
|
||||
device pnp 2e.8 on # Power management
|
||||
io 0x60 = 0xe800
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 12.1 off end # SMI
|
||||
device pci 12.2 off end # IDE
|
||||
device pci 12.3 on end # Audio
|
||||
device pci 12.4 on end # VGA (onboard)
|
||||
device pci 13.0 on end # USB
|
||||
# register "ide0_enable" = "1"
|
||||
# register "ide1_enable" = "1"
|
||||
end
|
||||
end
|
||||
chip cpu/amd/geode_gx1 # CPU
|
||||
end
|
||||
end
|
@@ -1,122 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Juergen Beisert <juergen@kreuzholzen.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* Interrupt routing description for the AXUS TC320 board.
|
||||
* It was not possible to read back the PIRQ table. There was no BIOS to ask
|
||||
* for it, only a bootloader for an embedded OS.
|
||||
* But with the method described here:
|
||||
* http://coreboot.org/Creating_Valid_IRQ_Tables
|
||||
* it was possible to detect the physical IRQ routing on this board.
|
||||
*
|
||||
* This is the physical routing on this board:
|
||||
*
|
||||
* IRQ 5530 USB Network
|
||||
* controller northbridge device device
|
||||
* 00.13.0 00.0e.00
|
||||
* --------------------------------------------
|
||||
* 11 INTA# INTA# n.c.
|
||||
* 15 INTB# n.c. INTA#
|
||||
* INTC# n.c. n.c.
|
||||
* INTD# n.c. n.c.
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
#define INT_A 0x01
|
||||
#define INT_B 0x02
|
||||
#define INT_C 0x03
|
||||
#define INT_D 0x04
|
||||
|
||||
/*
|
||||
* The USB controller should be connected to IRQ11,
|
||||
* the network controller should be connected to IRQ15.
|
||||
*/
|
||||
|
||||
#define IRQ_BITMAP_LINK0 0x0800
|
||||
#define IRQ_BITMAP_LINK1 0x8000
|
||||
#define IRQ_BITMAP_LINK2 0x0000
|
||||
#define IRQ_BITMAP_LINK3 0x0000
|
||||
|
||||
/** Reserved interrupt channels for exclusive PCI usage. */
|
||||
#define IRQ_DEVOTED_TO_PCI (IRQ_BITMAP_LINK0 | IRQ_BITMAP_LINK1)
|
||||
|
||||
/**
|
||||
* Routing description.
|
||||
* Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx
|
||||
*/
|
||||
static const struct irq_routing_table intel_irq_routing_table = {
|
||||
.signature = PIRQ_SIGNATURE, /* PIRQ signature */
|
||||
.version = PIRQ_VERSION, /* PIRQ version */
|
||||
.size = 32 + 16 * CONFIG_IRQ_SLOT_COUNT,/* Max. CONFIG_IRQ_SLOT_COUNT devices */
|
||||
.rtr_bus = 0x00, /* Interrupt router bus */
|
||||
.rtr_devfn = (0x12 << 3) | 0x0, /* Interrupt router device */
|
||||
.exclusive_irqs = IRQ_DEVOTED_TO_PCI, /* IRQs devoted to PCI */
|
||||
.rtr_vendor = 0x1078, /* Vendor */
|
||||
.rtr_device = 0x0100, /* Device */
|
||||
.miniport_data = 0, /* Miniport data */
|
||||
.checksum = 0xe3, /* Checksum */
|
||||
.slots = {
|
||||
/*
|
||||
* Definition for "slot#1". There is no real slot,
|
||||
* the USB device is embedded...
|
||||
*/
|
||||
[0] = {
|
||||
.bus = 0x00,
|
||||
.devfn = (0x13 << 3) | 0x0,
|
||||
.irq = {
|
||||
/* Link Bitmap */
|
||||
[0] = { INT_A, IRQ_BITMAP_LINK0 },
|
||||
[1] = { INT_B, IRQ_BITMAP_LINK1 },
|
||||
[2] = { INT_C, IRQ_BITMAP_LINK2 },
|
||||
[3] = { INT_D, IRQ_BITMAP_LINK3 },
|
||||
},
|
||||
.slot = 0x0,
|
||||
},
|
||||
/*
|
||||
* Definition for "slot#2". There is no real slot,
|
||||
* the network device is soldered...
|
||||
*/
|
||||
[1] = {
|
||||
.bus = 0x00,
|
||||
.devfn = (0x0e << 3) | 0x0,
|
||||
.irq = {
|
||||
/* Link Bitmap */
|
||||
[0] = { INT_B, IRQ_BITMAP_LINK1 },
|
||||
[1] = { INT_C, IRQ_BITMAP_LINK2 },
|
||||
[2] = { INT_D, IRQ_BITMAP_LINK3 },
|
||||
[3] = { INT_A, IRQ_BITMAP_LINK0 },
|
||||
},
|
||||
.slot = 0x0,
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
/**
|
||||
* Copy the IRQ routing table to memory.
|
||||
*
|
||||
* @param[in] addr Destination address (between 0xF0000...0x100000).
|
||||
* @return TODO.
|
||||
*/
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
|
||||
}
|
@@ -1,41 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Juergen Beisert <juergen@kreuzholzen.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <console/console.h>
|
||||
#include "northbridge/amd/gx1/raminit.c"
|
||||
#include "superio/nsc/pc97317/early_serial.c"
|
||||
#include "cpu/x86/bist.h"
|
||||
#include "southbridge/amd/cs5530/enable_rom.c"
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
|
||||
|
||||
#include <cpu/intel/romstage.h>
|
||||
static void main(unsigned long bist)
|
||||
{
|
||||
pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
report_bist_failure(bist);
|
||||
cs5530_enable_rom();
|
||||
sdram_init();
|
||||
}
|
@@ -21,14 +21,11 @@ if VENDOR_BCOM
|
||||
choice
|
||||
prompt "Mainboard model"
|
||||
|
||||
config BOARD_BCOM_WINNET100
|
||||
bool "WinNET100"
|
||||
config BOARD_BCOM_WINNETP680
|
||||
bool "WinNET P680"
|
||||
|
||||
endchoice
|
||||
|
||||
source "src/mainboard/bcom/winnet100/Kconfig"
|
||||
source "src/mainboard/bcom/winnetp680/Kconfig"
|
||||
|
||||
config MAINBOARD_VENDOR
|
||||
|
@@ -1,46 +0,0 @@
|
||||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
if BOARD_BCOM_WINNET100
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
select CPU_AMD_GEODE_GX1
|
||||
select NORTHBRIDGE_AMD_GX1
|
||||
select SOUTHBRIDGE_AMD_CS5530
|
||||
select SUPERIO_NSC_PC97317
|
||||
select ROMCC
|
||||
select HAVE_PIRQ_TABLE
|
||||
select PIRQ_ROUTE
|
||||
select UDELAY_TSC
|
||||
select BOARD_ROMSIZE_KB_256
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default bcom/winnet100
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "WinNET100"
|
||||
|
||||
# Soldered NIC, internal USB, no real PCI slots.
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 2
|
||||
|
||||
endif # BOARD_BCOM_WINNET100
|
@@ -1,4 +0,0 @@
|
||||
Category: settop
|
||||
Board name: WinNET100 (IGEL-316)
|
||||
Board URL: http://web.archive.org/web/20031207003521/http://www.igel.co.za/igel_316_compact.htm
|
||||
Flashrom support: y
|
@@ -1,56 +0,0 @@
|
||||
chip northbridge/amd/gx1 # Northbridge
|
||||
device domain 0 on # PCI domain
|
||||
device pci 0.0 on end # Host bridge
|
||||
chip southbridge/amd/cs5530 # Southbridge
|
||||
device pci 0f.0 on end # Ethernet (onboard)
|
||||
device pci 12.0 on # ISA bridge
|
||||
chip superio/nsc/pc97317 # Super I/O
|
||||
device pnp 2e.0 on # PS/2 keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 2e.1 on # PS/2 mouse
|
||||
irq 0x70 = 12
|
||||
end
|
||||
device pnp 2e.2 on # RTC, Advanced power control (APC)
|
||||
io 0x60 = 0x70
|
||||
irq 0x70 = 8
|
||||
end
|
||||
device pnp 2e.3 off # Floppy (N/A on this board)
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.4 on # Parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.5 on # COM2 (used for smartcard reader)
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.6 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.7 on # GPIO
|
||||
io 0x60 = 0xe0
|
||||
end
|
||||
device pnp 2e.8 on # Power management
|
||||
io 0x60 = 0xe8
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 12.1 off end # SMI
|
||||
device pci 12.2 on end # IDE
|
||||
device pci 12.3 on end # Audio
|
||||
device pci 12.4 on end # VGA (onboard)
|
||||
device pci 13.0 on end # USB
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "0" # Not available/needed on this board
|
||||
end
|
||||
end
|
||||
chip cpu/amd/geode_gx1 # CPU
|
||||
end
|
||||
end
|
@@ -1,121 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Juergen Beisert <juergen@kreuzholzen.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/**
|
||||
* @file
|
||||
* Interrupt routing description for BCOM's Winnet100 board.
|
||||
* It was not possible to read back the pirq-Table. In the 0xF segment was
|
||||
* no string like $PIRQ...
|
||||
* But the already running 2.4.21 kernel provides eth0 IRQ15 and USB IRQ 11.
|
||||
* The Realtek was device 0.f.0, the USB 0.13.0.
|
||||
*
|
||||
* This is the physical routing on this board:
|
||||
*
|
||||
* 5530 USB Network
|
||||
* northbridge device device
|
||||
* 00.13.0 00.0f.00
|
||||
* ------------------------------------
|
||||
* INTA# INTA# n.c.
|
||||
* INTB# n.c. n.c.
|
||||
* INTC# n.c. INTA#
|
||||
* INTD# n.c. n.c.
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
#define INT_A 0x01
|
||||
#define INT_B 0x02
|
||||
#define INT_C 0x03
|
||||
#define INT_D 0x04
|
||||
|
||||
/*
|
||||
* The USB controller should be connected to IRQ11,
|
||||
* the network controller should be connected to IRQ15.
|
||||
*/
|
||||
#define IRQ_BITMAP_LINK0 0x0800
|
||||
#define IRQ_BITMAP_LINK1 0x0400
|
||||
#define IRQ_BITMAP_LINK2 0x8000
|
||||
#define IRQ_BITMAP_LINK3 0x0200
|
||||
|
||||
/** Reserved interrupt channels for exclusive PCI usage. */
|
||||
#define IRQ_DEVOTED_TO_PCI (IRQ_BITMAP_LINK0 | IRQ_BITMAP_LINK2)
|
||||
|
||||
/**
|
||||
* Routing description.
|
||||
* Documentation at: http://www.microsoft.com/whdc/archive/pciirq.mspx
|
||||
*/
|
||||
static const struct irq_routing_table intel_irq_routing_table = {
|
||||
.signature = PIRQ_SIGNATURE, /* PIRQ signature */
|
||||
.version = PIRQ_VERSION, /* PIRQ version */
|
||||
.size = 32 +16 * CONFIG_IRQ_SLOT_COUNT,/* Max. CONFIG_IRQ_SLOT_COUNT devices */
|
||||
.rtr_bus = 0x00, /* Interrupt router bus */
|
||||
.rtr_devfn = (0x12 << 3) | 0x0, /* Interrupt router device */
|
||||
.exclusive_irqs = IRQ_DEVOTED_TO_PCI, /* IRQs devoted to PCI */
|
||||
.rtr_vendor = 0x1078, /* Vendor */
|
||||
.rtr_device = 0x0100, /* Device */
|
||||
.miniport_data = 0, /* Miniport data */
|
||||
.checksum = 0xbf + 16, /* Checksum */
|
||||
.slots = {
|
||||
/*
|
||||
* Definition for "slot#1". There is no real slot,
|
||||
* the USB device is embedded...
|
||||
*/
|
||||
[0] = {
|
||||
.bus = 0x00,
|
||||
.devfn = (0x13 << 3) | 0x0,
|
||||
.irq = {
|
||||
/* Link Bitmap */
|
||||
[0] = { INT_A, IRQ_BITMAP_LINK0 },
|
||||
[1] = { INT_B, IRQ_BITMAP_LINK1 },
|
||||
[2] = { INT_C, IRQ_BITMAP_LINK2 },
|
||||
[3] = { INT_D, IRQ_BITMAP_LINK3 },
|
||||
},
|
||||
.slot = 0x0,
|
||||
},
|
||||
|
||||
/*
|
||||
* Definition for "slot#3". There is no real slot,
|
||||
* the network device is soldered...
|
||||
*/
|
||||
[1] = {
|
||||
.bus = 0x00,
|
||||
.devfn = (0x0f << 3) | 0x0,
|
||||
.irq = {
|
||||
/* Link Bitmap */
|
||||
[0] = { INT_C, IRQ_BITMAP_LINK2 },
|
||||
[1] = { INT_D, IRQ_BITMAP_LINK3 },
|
||||
[2] = { INT_A, IRQ_BITMAP_LINK0 },
|
||||
[3] = { INT_B, IRQ_BITMAP_LINK1 },
|
||||
},
|
||||
.slot = 0x0,
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
/**
|
||||
* Copy the IRQ routing table to memory.
|
||||
*
|
||||
* @param[in] addr Destination address (between 0xF0000...0x100000).
|
||||
* @return TODO.
|
||||
*/
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
|
||||
}
|
@@ -1,41 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Juergen Beisert <juergen@kreuzholzen.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <console/console.h>
|
||||
#include "northbridge/amd/gx1/raminit.c"
|
||||
#include "superio/nsc/pc97317/early_serial.c"
|
||||
#include "cpu/x86/bist.h"
|
||||
#include "southbridge/amd/cs5530/enable_rom.c"
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
|
||||
|
||||
#include <cpu/intel/romstage.h>
|
||||
static void main(unsigned long bist)
|
||||
{
|
||||
pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
report_bist_failure(bist);
|
||||
cs5530_enable_rom();
|
||||
sdram_init();
|
||||
}
|
@@ -1,45 +0,0 @@
|
||||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
if BOARD_EAGLELION_5BCM
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
select CPU_AMD_GEODE_GX1
|
||||
select NORTHBRIDGE_AMD_GX1
|
||||
select SOUTHBRIDGE_AMD_CS5530
|
||||
select SUPERIO_NSC_PC97317
|
||||
select ROMCC
|
||||
select HAVE_PIRQ_TABLE
|
||||
select PIRQ_ROUTE
|
||||
select UDELAY_TSC
|
||||
select BOARD_ROMSIZE_KB_256
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default eaglelion/5bcm
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "5BCM"
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 2
|
||||
|
||||
endif # BOARD_EAGLELION_5BCM
|
@@ -1 +0,0 @@
|
||||
Category: half
|
@@ -1,72 +0,0 @@
|
||||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
#0 8 r 0 seconds
|
||||
#8 8 r 0 alarm_seconds
|
||||
#16 8 r 0 minutes
|
||||
#24 8 r 0 alarm_minutes
|
||||
#32 8 r 0 hours
|
||||
#40 8 r 0 alarm_hours
|
||||
#48 8 r 0 day_of_week
|
||||
#56 8 r 0 day_of_month
|
||||
#64 8 r 0 month
|
||||
#72 8 r 0 year
|
||||
#80 4 r 0 rate_select
|
||||
#84 3 r 0 REF_Clock
|
||||
#87 1 r 0 UIP
|
||||
#88 1 r 0 auto_switch_DST
|
||||
#89 1 r 0 24_hour_mode
|
||||
#90 1 r 0 binary_values_enable
|
||||
#91 1 r 0 square-wave_out_enable
|
||||
#92 1 r 0 update_finished_enable
|
||||
#93 1 r 0 alarm_interrupt_enable
|
||||
#94 1 r 0 periodic_interrupt_enable
|
||||
#95 1 r 0 disable_clock_updates
|
||||
#96 288 r 0 temporary_filler
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
385 1 e 4 last_boot
|
||||
386 1 e 1 ECC_memory
|
||||
388 4 r 0 reboot_bits
|
||||
392 3 e 5 baud_rate
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
416 4 e 7 boot_first
|
||||
420 4 e 7 boot_second
|
||||
424 4 e 7 boot_third
|
||||
428 4 h 0 boot_index
|
||||
432 8 h 0 boot_countdown
|
||||
1008 16 h 0 check_sum
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
7 0 Network
|
||||
7 1 HDD
|
||||
7 2 Floppy
|
||||
7 8 Fallback_Network
|
||||
7 9 Fallback_HDD
|
||||
7 10 Fallback_Floppy
|
||||
#7 3 ROM
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 1007 1008
|
@@ -1,52 +0,0 @@
|
||||
chip northbridge/amd/gx1
|
||||
device domain 0 on
|
||||
device pci 0.0 on end
|
||||
chip southbridge/amd/cs5530
|
||||
device pci 12.0 on
|
||||
chip superio/nsc/pc97317
|
||||
device pnp 2e.0 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 2e.1 on # Mouse
|
||||
irq 0x70 = 12
|
||||
end
|
||||
device pnp 2e.2 on # RTC
|
||||
io 0x60 = 0x70
|
||||
irq 0x70 = 8
|
||||
end
|
||||
device pnp 2e.3 off # FDC
|
||||
end
|
||||
device pnp 2e.4 on # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.5 on # COM2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.6 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.7 on # GPIO
|
||||
io 0x60 = 0xe0
|
||||
end
|
||||
device pnp 2e.8 on # Power Management
|
||||
io 0x60 = 0xe800
|
||||
end
|
||||
end
|
||||
device pci 12.1 off end # SMI
|
||||
device pci 12.2 on end # IDE
|
||||
device pci 12.3 off end # Audio
|
||||
device pci 12.4 off end # VGA
|
||||
end
|
||||
end
|
||||
end
|
||||
|
||||
chip cpu/amd/geode_gx1
|
||||
end
|
||||
|
||||
end
|
||||
|
@@ -1,31 +0,0 @@
|
||||
/* This file was generated by getpir.c, do not modify!
|
||||
(but if you do, please run checkpir on it to verify)
|
||||
* Contains the IRQ Routing Table dumped directly from your memory, which BIOS sets up
|
||||
*
|
||||
* Documentation at : http://www.microsoft.com/hwdev/busbios/PCIIRQ.HTM
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
static const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32+16*CONFIG_IRQ_SLOT_COUNT, /* there can be total CONFIG_IRQ_SLOT_COUNT devices on the bus */
|
||||
0x00, /* Where the interrupt router lies (bus) */
|
||||
(0x12<<3)|0x0, /* Where the interrupt router lies (dev) */
|
||||
0x800, /* IRQs devoted exclusively to PCI usage */
|
||||
0x1078, /* Vendor */
|
||||
0x2, /* Device */
|
||||
0, /* Miniport data */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0xdf, /* u8 checksum , this hase to set to some value that would give 0 after the sum of all bytes for this structure (including checksum) */
|
||||
{
|
||||
/* bus, dev|fn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */
|
||||
{0x00,(0x0e<<3)|0x0, {{0x02, 0xdeb8}, {0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0x0deb8}}, 0x1, 0x0},
|
||||
{0x00,(0x0f<<3)|0x0, {{0x03, 0xdeb8}, {0x04, 0xdeb8}, {0x01, 0xdeb8}, {0x02, 0x0deb8}}, 0x2, 0x0},
|
||||
}
|
||||
};
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
|
||||
}
|
@@ -1,22 +0,0 @@
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <stdlib.h>
|
||||
#include <console/console.h>
|
||||
#include "superio/nsc/pc97317/early_serial.c"
|
||||
#include "cpu/x86/bist.h"
|
||||
#include "southbridge/amd/cs5530/enable_rom.c"
|
||||
#include "northbridge/amd/gx1/raminit.c"
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
|
||||
|
||||
#include <cpu/intel/romstage.h>
|
||||
static void main(unsigned long bist)
|
||||
{
|
||||
pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
report_bist_failure(bist);
|
||||
cs5530_enable_rom();
|
||||
sdram_init();
|
||||
}
|
@@ -1,35 +0,0 @@
|
||||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
if VENDOR_EAGLELION
|
||||
|
||||
choice
|
||||
prompt "Mainboard model"
|
||||
|
||||
config BOARD_EAGLELION_5BCM
|
||||
bool "5BCM"
|
||||
|
||||
endchoice
|
||||
|
||||
source "src/mainboard/eaglelion/5bcm/Kconfig"
|
||||
|
||||
config MAINBOARD_VENDOR
|
||||
string
|
||||
default "EagleLion"
|
||||
|
||||
endif # VENDOR_EAGLELION
|
@@ -21,14 +21,8 @@ if VENDOR_IEI
|
||||
choice
|
||||
prompt "Mainboard model"
|
||||
|
||||
config BOARD_IEI_JUKI_511P
|
||||
bool "JUKI-511P"
|
||||
config BOARD_IEI_ROCKY_512
|
||||
bool "ROCKY-512"
|
||||
config BOARD_IEI_KINO_FAM10
|
||||
bool "Kino-780AM2(Fam10)"
|
||||
config BOARD_IEI_NOVA_4899R
|
||||
bool "NOVA-4899R"
|
||||
config BOARD_IEI_PCISA_LX_800_R10
|
||||
bool "PCISA LX-800-R10"
|
||||
config BOARD_IEI_PM_LX_800_R11
|
||||
@@ -38,10 +32,7 @@ config BOARD_IEI_PM_LX2_800_R10
|
||||
|
||||
endchoice
|
||||
|
||||
source "src/mainboard/iei/juki-511p/Kconfig"
|
||||
source "src/mainboard/iei/rocky-512/Kconfig"
|
||||
source "src/mainboard/iei/kino-780am2-fam10/Kconfig"
|
||||
source "src/mainboard/iei/nova4899r/Kconfig"
|
||||
source "src/mainboard/iei/pcisa-lx-800-r10/Kconfig"
|
||||
source "src/mainboard/iei/pm-lx-800-r11/Kconfig"
|
||||
source "src/mainboard/iei/pm-lx2-800-r10/Kconfig"
|
||||
|
@@ -1,47 +0,0 @@
|
||||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
if BOARD_IEI_JUKI_511P || BOARD_IEI_ROCKY_512
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
select CPU_AMD_GEODE_GX1
|
||||
select NORTHBRIDGE_AMD_GX1
|
||||
select SOUTHBRIDGE_AMD_CS5530
|
||||
select SUPERIO_WINBOND_W83977F
|
||||
select ROMCC
|
||||
select PIRQ_ROUTE
|
||||
select HAVE_PIRQ_TABLE
|
||||
select HAVE_OPTION_TABLE
|
||||
select BOARD_ROMSIZE_KB_256
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default iei/juki-511p
|
||||
|
||||
if BOARD_IEI_JUKI_511P
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "JUKI-511P"
|
||||
endif # BOARD_IEI_JUKI_511P
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 2
|
||||
|
||||
endif # BOARD_IEI_JUKI_511P || BOARD_IEI_ROCKY_512
|
@@ -1,2 +0,0 @@
|
||||
Category: half
|
||||
Board URL: http://www.ieiworld.com/en/news_content.asp?id=erbium/projectOBJ00150613
|
@@ -1,72 +0,0 @@
|
||||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
#0 8 r 0 seconds
|
||||
#8 8 r 0 alarm_seconds
|
||||
#16 8 r 0 minutes
|
||||
#24 8 r 0 alarm_minutes
|
||||
#32 8 r 0 hours
|
||||
#40 8 r 0 alarm_hours
|
||||
#48 8 r 0 day_of_week
|
||||
#56 8 r 0 day_of_month
|
||||
#64 8 r 0 month
|
||||
#72 8 r 0 year
|
||||
#80 4 r 0 rate_select
|
||||
#84 3 r 0 REF_Clock
|
||||
#87 1 r 0 UIP
|
||||
#88 1 r 0 auto_switch_DST
|
||||
#89 1 r 0 24_hour_mode
|
||||
#90 1 r 0 binary_values_enable
|
||||
#91 1 r 0 square-wave_out_enable
|
||||
#92 1 r 0 update_finished_enable
|
||||
#93 1 r 0 alarm_interrupt_enable
|
||||
#94 1 r 0 periodic_interrupt_enable
|
||||
#95 1 r 0 disable_clock_updates
|
||||
#96 288 r 0 temporary_filler
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
385 1 e 4 last_boot
|
||||
386 1 e 1 ECC_memory
|
||||
388 4 r 0 reboot_bits
|
||||
392 3 e 5 baud_rate
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
416 4 e 7 boot_first
|
||||
420 4 e 7 boot_second
|
||||
424 4 e 7 boot_third
|
||||
428 4 h 0 boot_index
|
||||
432 8 h 0 boot_countdown
|
||||
1008 16 h 0 check_sum
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
7 0 Network
|
||||
7 1 HDD
|
||||
7 2 Floppy
|
||||
7 8 Fallback_Network
|
||||
7 9 Fallback_HDD
|
||||
7 10 Fallback_Floppy
|
||||
#7 3 ROM
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 1007 1008
|
@@ -1,57 +0,0 @@
|
||||
chip northbridge/amd/gx1
|
||||
device domain 0 on
|
||||
device pci 0.0 on end
|
||||
chip southbridge/amd/cs5530
|
||||
|
||||
device pci 12.0 on
|
||||
chip superio/winbond/w83977f
|
||||
device pnp 3f0.0 on # FDC
|
||||
irq 0x70 = 6
|
||||
end
|
||||
device pnp 3f0.1 on # Parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 3f0.2 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 3f0.3 on # COM2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 3f0.4 on # RTC
|
||||
io 0x60 = 0x070
|
||||
irq 0x70 = 8
|
||||
end
|
||||
device pnp 3f0.5 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1 # Int 1 for PS/2 keyboard
|
||||
irq 0x72 = 12 # Int 12 for PS/2 mouse
|
||||
end
|
||||
device pnp 3f0.6 off # IR
|
||||
end
|
||||
device pnp 3f0.7 off # GPIO1
|
||||
end
|
||||
device pnp 3f0.8 off # GPIO
|
||||
end
|
||||
end
|
||||
device pci 12.1 on end # SMI
|
||||
device pci 12.2 on end # IDE
|
||||
device pci 12.3 on end # Audio
|
||||
device pci 12.4 on end # VGA onboard
|
||||
|
||||
end
|
||||
|
||||
device pci 0e.0 on end # ETH0
|
||||
device pci 13.0 on end # USB
|
||||
|
||||
end
|
||||
end
|
||||
|
||||
chip cpu/amd/geode_gx1
|
||||
end
|
||||
|
||||
end
|
||||
|
@@ -1,103 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
#define IRQ_BITMAP_LINK0 0x0800 /* chipset's INTA# input should be routed to IRQ11 */
|
||||
#define IRQ_BITMAP_LINK1 0x0400 /* chipset's INTB# input should be routed to IRQ10 */
|
||||
#define IRQ_BITMAP_LINK2 0x0000 /* chipset's INTC# input should be routed to nothing (disabled) */
|
||||
#define IRQ_BITMAP_LINK3 0x0000 /* chipset's INTD# input should be routed to nothing (disabled) */
|
||||
|
||||
static const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be a total of CONFIG_IRQ_SLOT_COUNT devices on the bus */
|
||||
0x00, /* Where the interrupt router lies (bus) */
|
||||
(0x12<<3)|0x0, /* Where the interrupt router lies (dev) */
|
||||
0xc00, /* IRQs devoted exclusively to PCI usage */
|
||||
0x1078, /* Vendor */
|
||||
0x2, /* Device */
|
||||
0, /* Miniport data */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0x57, /* u8 checksum. This has to be set to some
|
||||
value that would give 0 after the sum of all
|
||||
bytes for this structure (including checksum) */
|
||||
|
||||
.slots = {
|
||||
[0] = {
|
||||
.slot = 0x0, /* should be 0 when it is no real slot. My device is soldered */
|
||||
.bus = 0x00,
|
||||
.devfn = (0x13<<3)|0x0, /* 0x13 is my USB OHCI */
|
||||
.irq = {
|
||||
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
|
||||
.link = 0x01, /* 0x01 means its connected to INTA# input at chipset */
|
||||
.bitmap = IRQ_BITMAP_LINK0
|
||||
},
|
||||
[1] = { /* <-- 1 means this is INTB# output from the device or slot */
|
||||
.link = 0x02, /* 0x02 means its connected to INTB# input at chipset */
|
||||
.bitmap = IRQ_BITMAP_LINK1
|
||||
},
|
||||
[2] = { /* <-- 2 means this is INTC# output from the device or slot */
|
||||
.link = 0x03, /* 0x03 means its connected to INTC# input at chipset */
|
||||
.bitmap = IRQ_BITMAP_LINK2
|
||||
},
|
||||
[3] = { /* <-- 3 means this is INTD# output from the device or slot */
|
||||
.link = 0x04, /* 0x04 means its connected to INTD# input at chipset */
|
||||
.bitmap = IRQ_BITMAP_LINK3
|
||||
}
|
||||
}
|
||||
},
|
||||
|
||||
[1] = {
|
||||
.slot = 0x0, /* means also "on board" */
|
||||
.bus = 0x00,
|
||||
.devfn = (0x0e<<3)|0x0, /* 0x0e is my Realtek Network device */
|
||||
.irq = {
|
||||
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
|
||||
.link = 0x02, /* 0x02 means its connected to INTB# input at chipset */
|
||||
.bitmap = IRQ_BITMAP_LINK1
|
||||
},
|
||||
[1] = { /* <-- 1 means this is INTB# output from the device or slot */
|
||||
.link = 0x03, /* 0x03 means its connected to INTC# input at chipset */
|
||||
.bitmap = IRQ_BITMAP_LINK2
|
||||
},
|
||||
[2] = { /* <-- 2 means this is INTC# output from the device or slot */
|
||||
.link = 0x04, /* 0x04 means its connected to INTD# input at chipset */
|
||||
.bitmap = IRQ_BITMAP_LINK3
|
||||
},
|
||||
[3] = { /* <-- 3 means this is INTD# output from the device or slot */
|
||||
.link = 0x01, /* 0x01 means its connected to INTA# input at chipset */
|
||||
.bitmap = IRQ_BITMAP_LINK0
|
||||
}
|
||||
}
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
/**
|
||||
* Copy the IRQ routing table to memory.
|
||||
*
|
||||
* @param addr Destination address (between 0xF0000...0x100000).
|
||||
* @return The end address of the pirq routing table in memory.
|
||||
*/
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
|
||||
}
|
@@ -1,47 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <console/console.h>
|
||||
#include "superio/winbond/w83977f/early_serial.c"
|
||||
#include "southbridge/amd/cs5530/enable_rom.c"
|
||||
#include "cpu/x86/bist.h"
|
||||
#include "drivers/pc80/udelay_io.c"
|
||||
#include "northbridge/amd/gx1/raminit.c"
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x3f0, W83977F_SP1)
|
||||
|
||||
#include <cpu/intel/romstage.h>
|
||||
static void main(unsigned long bist)
|
||||
{
|
||||
w83977f_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
report_bist_failure(bist);
|
||||
|
||||
/* Disable Watchdog Timer. */
|
||||
inb(0x043);
|
||||
inb(0x843);
|
||||
|
||||
cs5530_enable_rom();
|
||||
sdram_init();
|
||||
}
|
@@ -1,46 +0,0 @@
|
||||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
if BOARD_IEI_NOVA_4899R
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
select CPU_AMD_GEODE_GX1
|
||||
select NORTHBRIDGE_AMD_GX1
|
||||
select SOUTHBRIDGE_AMD_CS5530
|
||||
select SUPERIO_WINBOND_W83977TF
|
||||
select ROMCC
|
||||
select HAVE_PIRQ_TABLE
|
||||
select PIRQ_ROUTE
|
||||
select HAVE_OPTION_TABLE
|
||||
select UDELAY_TSC
|
||||
select BOARD_ROMSIZE_KB_256
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default iei/nova4899r
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "NOVA-4899R"
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 5
|
||||
|
||||
endif # BOARD_IEI_NOVA_4899R
|
@@ -1,2 +0,0 @@
|
||||
Category: half
|
||||
Board URL: http://www.icpamerica.com/products/single_board_computers/5_25_NOVA/NOVA-4899.html
|
@@ -1,72 +0,0 @@
|
||||
entries
|
||||
|
||||
#start-bit length config config-ID name
|
||||
#0 8 r 0 seconds
|
||||
#8 8 r 0 alarm_seconds
|
||||
#16 8 r 0 minutes
|
||||
#24 8 r 0 alarm_minutes
|
||||
#32 8 r 0 hours
|
||||
#40 8 r 0 alarm_hours
|
||||
#48 8 r 0 day_of_week
|
||||
#56 8 r 0 day_of_month
|
||||
#64 8 r 0 month
|
||||
#72 8 r 0 year
|
||||
#80 4 r 0 rate_select
|
||||
#84 3 r 0 REF_Clock
|
||||
#87 1 r 0 UIP
|
||||
#88 1 r 0 auto_switch_DST
|
||||
#89 1 r 0 24_hour_mode
|
||||
#90 1 r 0 binary_values_enable
|
||||
#91 1 r 0 square-wave_out_enable
|
||||
#92 1 r 0 update_finished_enable
|
||||
#93 1 r 0 alarm_interrupt_enable
|
||||
#94 1 r 0 periodic_interrupt_enable
|
||||
#95 1 r 0 disable_clock_updates
|
||||
#96 288 r 0 temporary_filler
|
||||
0 384 r 0 reserved_memory
|
||||
384 1 e 4 boot_option
|
||||
385 1 e 4 last_boot
|
||||
386 1 e 1 ECC_memory
|
||||
388 4 r 0 reboot_bits
|
||||
392 3 e 5 baud_rate
|
||||
400 1 e 1 power_on_after_fail
|
||||
412 4 e 6 debug_level
|
||||
416 4 e 7 boot_first
|
||||
420 4 e 7 boot_second
|
||||
424 4 e 7 boot_third
|
||||
428 4 h 0 boot_index
|
||||
432 8 h 0 boot_countdown
|
||||
1008 16 h 0 check_sum
|
||||
|
||||
enumerations
|
||||
|
||||
#ID value text
|
||||
1 0 Disable
|
||||
1 1 Enable
|
||||
2 0 Enable
|
||||
2 1 Disable
|
||||
4 0 Fallback
|
||||
4 1 Normal
|
||||
5 0 115200
|
||||
5 1 57600
|
||||
5 2 38400
|
||||
5 3 19200
|
||||
5 4 9600
|
||||
5 5 4800
|
||||
5 6 2400
|
||||
5 7 1200
|
||||
6 6 Notice
|
||||
6 7 Info
|
||||
6 8 Debug
|
||||
6 9 Spew
|
||||
7 0 Network
|
||||
7 1 HDD
|
||||
7 2 Floppy
|
||||
7 8 Fallback_Network
|
||||
7 9 Fallback_HDD
|
||||
7 10 Fallback_Floppy
|
||||
#7 3 ROM
|
||||
|
||||
checksums
|
||||
|
||||
checksum 392 1007 1008
|
@@ -1,64 +0,0 @@
|
||||
chip northbridge/amd/gx1
|
||||
device domain 0 on
|
||||
device pci 0.0 on end
|
||||
chip southbridge/amd/cs5530
|
||||
device pci 0a.0 on end # ETH0
|
||||
device pci 0b.0 off end # ETH1
|
||||
device pci 0c.0 on end # ETH2
|
||||
device pci 0f.0 on end # PCI slot
|
||||
device pci 12.0 on
|
||||
chip superio/winbond/w83977tf
|
||||
device pnp 2e.0 on # FDC
|
||||
irq 0x70 = 6
|
||||
end
|
||||
device pnp 2e.1 on # Parallel Port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.2 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.3 on # COM2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.4 off # Reserved
|
||||
end
|
||||
device pnp 2e.5 on # Keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 0x01 # Int 1 for PS/2 keyboard
|
||||
irq 0x72 = 0x0c # Int 12 for PS/2 mouse
|
||||
end
|
||||
device pnp 2e.6 on # IR
|
||||
io 0x60 = 0x2e8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.7 on # GAME/MIDI/GPIO1
|
||||
io 0x60 = 0x290
|
||||
end
|
||||
device pnp 2e.8 on # GPIO2
|
||||
io 0x60 = 0x110
|
||||
end
|
||||
device pnp 2e.9 on # GPIO3
|
||||
io 0x60 = 0x120
|
||||
end
|
||||
device pnp 2e.A on # Power Management
|
||||
io 0x60 = 0xe800
|
||||
end
|
||||
end
|
||||
device pci 12.1 on end # SMI
|
||||
device pci 12.2 on end # IDE
|
||||
device pci 12.3 on end # Audio
|
||||
device pci 12.4 on end # VGA onboard
|
||||
end
|
||||
device pci 13.0 on end # USB
|
||||
end
|
||||
end
|
||||
|
||||
chip cpu/amd/geode_gx1
|
||||
end
|
||||
|
||||
end
|
||||
|
@@ -1,214 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Luis Correia <luis.f.correia@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
|
||||
/*
|
||||
* IRQ 5530 USB Network Network Network free
|
||||
* controller northbridge device device#0 device#1 device#2 slot
|
||||
* 00.13.0 00.0a.00 00.0b.00 00.0c.00 00.0f.00
|
||||
* ------------------------------------------------------------------------
|
||||
* 14 INTA# INTA# n.c. n.c. n.c. INTA#
|
||||
* 5 INTB# n.c. n.c. n.c. INTA# n.c.
|
||||
* 10 INTC# n.c. n.c. INTA# n.c. n.c.
|
||||
* 11 INTD# n.c. INTA# n.c. n.c. n.c.
|
||||
*/
|
||||
|
||||
/*
|
||||
* - the USB controller should be connected to IRQ14
|
||||
* - the network controller #0 should be connected to IRQ11
|
||||
* - the network controller #1 should be connected to IRQ10
|
||||
* - the network controller #2 should be connected to IRQ5
|
||||
* - the additional PCI slot must share the IRQ with the internal USB
|
||||
*/
|
||||
|
||||
/* Bit 9 means IRQ 9 is available for this cs5530 INT input. */
|
||||
#define IRQ_BITMAP_LINK0 0x0200
|
||||
/* Bit 5 means IRQ 5 is available for this cs5530 INT input. */
|
||||
#define IRQ_BITMAP_LINK1 0x0020
|
||||
/* Bit 10 means IRQ10 is available for this cs5530 INT input. */
|
||||
#define IRQ_BITMAP_LINK2 0x0400
|
||||
/* Bit 11 means IRQ11 is available for this cs5530 INT input. */
|
||||
#define IRQ_BITMAP_LINK3 0x0800
|
||||
|
||||
static const struct irq_routing_table intel_irq_routing_table = {
|
||||
.signature = PIRQ_SIGNATURE, /* u32 signature */
|
||||
.version = PIRQ_VERSION, /* u16 version */
|
||||
.size = 32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be total 4 devices on the bus */
|
||||
.rtr_bus = 0x00, /* Where the interrupt router lies (bus) */
|
||||
.rtr_devfn = (0x12<<3)|0x0, /* Where the interrupt router lies (dev) */
|
||||
.exclusive_irqs = 0x4C20, /* IRQs devoted exclusively to PCI usage */
|
||||
.rtr_vendor = 0x1078, /* Vendor */
|
||||
.rtr_device = 0x0100, /* Device */
|
||||
.miniport_data = 0, /* Miniport data */
|
||||
.checksum = 0xBF+16, /* TODO! calculate correct sum ! */
|
||||
/*
|
||||
* Definition for "slot#0". There is no real slot,
|
||||
* the network device is soldered...
|
||||
*/
|
||||
.slots = {
|
||||
[0] = {
|
||||
.bus = 0x00,
|
||||
.devfn = (0x0a<<3)|0x0,
|
||||
.irq = {
|
||||
[0] = {
|
||||
.link = 0x03, /* INT C */
|
||||
.bitmap = IRQ_BITMAP_LINK2
|
||||
},
|
||||
[1] = {
|
||||
.link = 0x02, /* INT B */
|
||||
.bitmap = IRQ_BITMAP_LINK1
|
||||
},
|
||||
[2] = { /* = device INTA output */
|
||||
.link = 0x01, /* INT A */
|
||||
.bitmap = IRQ_BITMAP_LINK0
|
||||
},
|
||||
[3] = {
|
||||
.link = 0x04, /* = cs5530 INT D input */
|
||||
.bitmap = IRQ_BITMAP_LINK3
|
||||
}
|
||||
},
|
||||
.slot = 0x3, /* soldered */
|
||||
},
|
||||
/*
|
||||
* Definition for "slot#1". There is no real slot,
|
||||
* the network device is soldered...
|
||||
*
|
||||
* Configuration is ommited on purpose in the attempt of solving the
|
||||
* issue with IRQ panics (this is device is actually eth1).
|
||||
|
||||
[1] = {
|
||||
.bus = 0x00,
|
||||
.devfn = (0x0b<<3)|0x0,
|
||||
.irq = {
|
||||
[0] = {
|
||||
.link = 0x04,
|
||||
.bitmap = IRQ_BITMAP_LINK3
|
||||
},
|
||||
[1] = {
|
||||
.link = 0x03,
|
||||
.bitmap = IRQ_BITMAP_LINK2
|
||||
},
|
||||
[2] = {
|
||||
.link = 0x02,
|
||||
.bitmap = IRQ_BITMAP_LINK1
|
||||
},
|
||||
[3] = {
|
||||
.link = 0x01,
|
||||
.bitmap = IRQ_BITMAP_LINK0
|
||||
}
|
||||
},
|
||||
.slot = 0x2,
|
||||
},
|
||||
*/
|
||||
|
||||
/*
|
||||
* Definition for "slot#2". There is no real slot,
|
||||
* the network device is soldered...
|
||||
*/
|
||||
[2] = {
|
||||
.bus = 0x00,
|
||||
.devfn = (0x0c<<3)|0x0,
|
||||
.irq = {
|
||||
[0] = {
|
||||
.link = 0x01, /* INT A */
|
||||
.bitmap = IRQ_BITMAP_LINK0
|
||||
},
|
||||
[1] = {
|
||||
.link = 0x04, /* INT D */
|
||||
.bitmap = IRQ_BITMAP_LINK3
|
||||
},
|
||||
[2] = { /* = device INTA output */
|
||||
.link = 0x03, /* INT C */
|
||||
.bitmap = IRQ_BITMAP_LINK2
|
||||
},
|
||||
[3] = {
|
||||
.link = 0x02, /* = cs5530 INT B input */
|
||||
.bitmap = IRQ_BITMAP_LINK1
|
||||
}
|
||||
},
|
||||
.slot = 0x1, /* soldered */
|
||||
},
|
||||
/*
|
||||
* This is a free PCI slot.
|
||||
*/
|
||||
[3] = {
|
||||
.bus = 0x00,
|
||||
.devfn = (0x0f<<3)|0x0,
|
||||
.irq = {
|
||||
[0] = { /* = device INTA output */
|
||||
.link = 0x04, /* INT D */
|
||||
.bitmap = IRQ_BITMAP_LINK3
|
||||
},
|
||||
[1] = {
|
||||
.link = 0x03, /* = cs5530 INT C input */
|
||||
.bitmap = IRQ_BITMAP_LINK2
|
||||
},
|
||||
[2] = {
|
||||
.link = 0x02, /* INT B */
|
||||
.bitmap = IRQ_BITMAP_LINK1
|
||||
},
|
||||
[3] = {
|
||||
.link = 0x01, /* INT A */
|
||||
.bitmap = IRQ_BITMAP_LINK0
|
||||
}
|
||||
},
|
||||
.slot = 0x6, /* FIXME: should be not 0, as it defines a real slot */
|
||||
},
|
||||
/*
|
||||
* Definition for "slot#3". There is no real slot,
|
||||
* the USB device is embedded...
|
||||
*/
|
||||
[4] = {
|
||||
.bus = 0x00,
|
||||
.devfn = (0x13<<3)|0x0,
|
||||
.irq = {
|
||||
[0] = {
|
||||
.link = 0x02, /* INT B */
|
||||
.bitmap = IRQ_BITMAP_LINK1
|
||||
},
|
||||
[1] = {
|
||||
.link = 0x01, /* INT A */
|
||||
.bitmap = IRQ_BITMAP_LINK0
|
||||
},
|
||||
[2] = {
|
||||
.link = 0x04, /* INT D */
|
||||
.bitmap = IRQ_BITMAP_LINK3
|
||||
},
|
||||
[3] = {
|
||||
.link = 0x03, /* INT C */
|
||||
.bitmap = IRQ_BITMAP_LINK2
|
||||
}
|
||||
},
|
||||
.slot = 0x5, /* chip internal */
|
||||
}
|
||||
}
|
||||
};
|
||||
|
||||
/**
|
||||
* Copy the IRQ routing table to memory.
|
||||
*
|
||||
* @param addr Destination address (between 0xF0000...0x100000).
|
||||
* @return The end address of the pirq routing table in memory.
|
||||
**/
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
|
||||
}
|
@@ -1,42 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Luis Correia <luis.f.correia@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <console/console.h>
|
||||
#include "superio/winbond/w83977tf/early_serial.c"
|
||||
#include "southbridge/amd/cs5530/enable_rom.c"
|
||||
#include "cpu/x86/bist.h"
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x3f0, W83977TF_SP1)
|
||||
|
||||
#include "northbridge/amd/gx1/raminit.c"
|
||||
|
||||
#include <cpu/intel/romstage.h>
|
||||
static void main(unsigned long bist)
|
||||
{
|
||||
w83977tf_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
report_bist_failure(bist);
|
||||
cs5530_enable_rom();
|
||||
sdram_init();
|
||||
}
|
@@ -1,9 +0,0 @@
|
||||
if BOARD_IEI_ROCKY_512
|
||||
|
||||
# Dummy for abuild
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "ROCKY-512"
|
||||
|
||||
endif
|
@@ -1,3 +0,0 @@
|
||||
Category: half
|
||||
Board URL: http://www.ieiworld.com/en/product_IPC.asp?model=ROCKY-512
|
||||
Clone of: iei/juki-511p
|
@@ -1,35 +0,0 @@
|
||||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
if VENDOR_TELEVIDEO
|
||||
|
||||
choice
|
||||
prompt "Mainboard model"
|
||||
|
||||
config BOARD_TELEVIDEO_TC7020
|
||||
bool "TC7020"
|
||||
|
||||
endchoice
|
||||
|
||||
source "src/mainboard/televideo/tc7020/Kconfig"
|
||||
|
||||
config MAINBOARD_VENDOR
|
||||
string
|
||||
default "TeleVideo"
|
||||
|
||||
endif # VENDOR_TELEVIDEO
|
@@ -1,45 +0,0 @@
|
||||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
if BOARD_TELEVIDEO_TC7020
|
||||
|
||||
config BOARD_SPECIFIC_OPTIONS # dummy
|
||||
def_bool y
|
||||
select CPU_AMD_GEODE_GX1
|
||||
select NORTHBRIDGE_AMD_GX1
|
||||
select SOUTHBRIDGE_AMD_CS5530
|
||||
select SUPERIO_NSC_PC97317
|
||||
select ROMCC
|
||||
select HAVE_PIRQ_TABLE
|
||||
select PIRQ_ROUTE
|
||||
select UDELAY_TSC
|
||||
select BOARD_ROMSIZE_KB_256
|
||||
|
||||
config MAINBOARD_DIR
|
||||
string
|
||||
default televideo/tc7020
|
||||
|
||||
config MAINBOARD_PART_NUMBER
|
||||
string
|
||||
default "TC7020"
|
||||
|
||||
config IRQ_SLOT_COUNT
|
||||
int
|
||||
default 3
|
||||
|
||||
endif # BOARD_TELEVIDEO_TC7020
|
@@ -1,2 +0,0 @@
|
||||
Category: settop
|
||||
Board URL: http://www.televideo.com/TeleVideo/TC7000_WinCE_Series.htm
|
@@ -1,57 +0,0 @@
|
||||
chip northbridge/amd/gx1 # Northbridge
|
||||
device domain 0 on # PCI domain
|
||||
device pci 0.0 on end # Host bridge
|
||||
chip southbridge/amd/cs5530 # Southbridge
|
||||
device pci 12.0 on # ISA bridge
|
||||
chip superio/nsc/pc97317 # Super I/O
|
||||
device pnp 2e.0 on # PS/2 keyboard
|
||||
io 0x60 = 0x60
|
||||
io 0x62 = 0x64
|
||||
irq 0x70 = 1
|
||||
end
|
||||
device pnp 2e.1 on # PS/2 mouse
|
||||
irq 0x70 = 12
|
||||
end
|
||||
device pnp 2e.2 on # RTC, Advanced power control (APC)
|
||||
io 0x60 = 0x70
|
||||
irq 0x70 = 8
|
||||
end
|
||||
device pnp 2e.3 off # Floppy (N/A on this board)
|
||||
io 0x60 = 0x3f0
|
||||
irq 0x70 = 6
|
||||
drq 0x74 = 2
|
||||
end
|
||||
device pnp 2e.4 on # Parallel port
|
||||
io 0x60 = 0x378
|
||||
irq 0x70 = 7
|
||||
end
|
||||
device pnp 2e.5 on # COM2
|
||||
io 0x60 = 0x2f8
|
||||
irq 0x70 = 3
|
||||
end
|
||||
device pnp 2e.6 on # COM1
|
||||
io 0x60 = 0x3f8
|
||||
irq 0x70 = 4
|
||||
end
|
||||
device pnp 2e.7 on # GPIO
|
||||
io 0x60 = 0xe0
|
||||
end
|
||||
device pnp 2e.8 on # Power management
|
||||
io 0x60 = 0xe8
|
||||
end
|
||||
end
|
||||
end
|
||||
device pci 12.1 off end # SMI
|
||||
device pci 12.2 on end # IDE
|
||||
device pci 12.3 on end # Audio
|
||||
device pci 12.4 on end # VGA (onboard)
|
||||
device pci 13.0 on end # USB
|
||||
device pci 14.0 on end # MiniPCI slot
|
||||
device pci 15.0 on end # Ethernet (onboard)
|
||||
register "ide0_enable" = "1"
|
||||
register "ide1_enable" = "0" # Not available/needed on this board
|
||||
end
|
||||
end
|
||||
chip cpu/amd/geode_gx1 # CPU
|
||||
end
|
||||
end
|
@@ -1,148 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com>
|
||||
* Copyright (C) 2007 Kenji Noguchi <tokyo246@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
|
||||
/* Platform IRQs */
|
||||
#define PIRQA 11
|
||||
#define PIRQB 10
|
||||
#define PIRQC 9
|
||||
#define PIRQD 12
|
||||
|
||||
/* Link */
|
||||
#define LINK_PIRQA 1
|
||||
#define LINK_PIRQB 2
|
||||
#define LINK_PIRQC 3
|
||||
#define LINK_PIRQD 4
|
||||
#define LINK_NONE 0
|
||||
|
||||
/* Map */
|
||||
#define IRQ_BITMAP_LINKA (1 << PIRQA)
|
||||
#define IRQ_BITMAP_LINKB (1 << PIRQB)
|
||||
#define IRQ_BITMAP_LINKC (1 << PIRQC)
|
||||
#define IRQ_BITMAP_LINKD (1 << PIRQD)
|
||||
#define IRQ_BITMAP_NOLINK 0x0
|
||||
|
||||
#define EXCLUSIVE_PCI_IRQS (IRQ_BITMAP_LINKA | IRQ_BITMAP_LINKB | IRQ_BITMAP_LINKC | IRQ_BITMAP_LINKD)
|
||||
|
||||
static const struct irq_routing_table intel_irq_routing_table = {
|
||||
PIRQ_SIGNATURE, /* u32 signature */
|
||||
PIRQ_VERSION, /* u16 version */
|
||||
32+16*CONFIG_IRQ_SLOT_COUNT, /* There can be a total of CONFIG_IRQ_SLOT_COUNT devices on the bus */
|
||||
0x00, /* Where the interrupt router lies (bus) */
|
||||
(0x12<<3)|0x0, /* Where the interrupt router lies (dev) */
|
||||
EXCLUSIVE_PCI_IRQS, /* IRQs devoted exclusively to PCI usage */
|
||||
0x1078, /* Vendor */
|
||||
0x1, /* Device */
|
||||
0, /* Miniport data */
|
||||
{ 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */
|
||||
0x60, /* u8 checksum. This has to be set to some
|
||||
value that would give 0 after the sum of all
|
||||
bytes for this structure (including checksum) */
|
||||
|
||||
.slots = {
|
||||
[0] = {
|
||||
.slot = 0x0, /* means also "on board" */
|
||||
.bus = 0x00,
|
||||
.devfn = (0x13<<3)|0x0, /* 0x13 is USB OHCI */
|
||||
.irq = {
|
||||
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
|
||||
.link = LINK_PIRQA,
|
||||
.bitmap = IRQ_BITMAP_LINKA
|
||||
},
|
||||
[1] = { /* <-- 1 means this is INTB# output from the device or slot */
|
||||
.link = LINK_NONE,
|
||||
.bitmap = IRQ_BITMAP_NOLINK
|
||||
},
|
||||
[2] = { /* <-- 2 means this is INTC# output from the device or slot */
|
||||
.link = LINK_NONE,
|
||||
.bitmap = IRQ_BITMAP_NOLINK
|
||||
},
|
||||
[3] = { /* <-- 3 means this is INTD# output from the device or slot */
|
||||
.link = LINK_NONE,
|
||||
.bitmap = IRQ_BITMAP_NOLINK
|
||||
}
|
||||
}
|
||||
},
|
||||
|
||||
[1] = {
|
||||
.slot = 0x0, /* means also "on board" */
|
||||
.bus = 0x00,
|
||||
.devfn = (0x15<<3)|0x0, /* 0x15 is NSC Network device */
|
||||
.irq = {
|
||||
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
|
||||
.link = LINK_PIRQB,
|
||||
.bitmap = IRQ_BITMAP_LINKB
|
||||
},
|
||||
[1] = { /* <-- 1 means this is INTB# output from the device or slot */
|
||||
.link = LINK_NONE,
|
||||
.bitmap = IRQ_BITMAP_NOLINK
|
||||
},
|
||||
[2] = { /* <-- 2 means this is INTC# output from the device or slot */
|
||||
.link = LINK_NONE,
|
||||
.bitmap = IRQ_BITMAP_NOLINK
|
||||
},
|
||||
[3] = { /* <-- 3 means this is INTD# output from the device or slot */
|
||||
.link = LINK_NONE,
|
||||
.bitmap = IRQ_BITMAP_NOLINK
|
||||
}
|
||||
}
|
||||
},
|
||||
|
||||
[2] = {
|
||||
.slot = 0x1, /* This is a Mini PCI slot */
|
||||
.bus = 0x00,
|
||||
.devfn = (0x14<<3)|0x0,
|
||||
.irq = {
|
||||
[0] = { /* <-- 0 means this is INTA# output from the device or slot */
|
||||
.link = LINK_PIRQC,
|
||||
.bitmap = IRQ_BITMAP_LINKC
|
||||
},
|
||||
[1] = { /* <-- 1 means this is INTB# output from the device or slot */
|
||||
/* NEEDSWORK: not confirmed. No device to test which uses both INTA and INTB */
|
||||
.link = LINK_PIRQD,
|
||||
.bitmap = IRQ_BITMAP_LINKD
|
||||
},
|
||||
[2] = { /* No INTC# for Mini PCI */
|
||||
.link = LINK_NONE,
|
||||
.bitmap = IRQ_BITMAP_NOLINK
|
||||
},
|
||||
[3] = { /* No INTD# for Mini PCI */
|
||||
.link = LINK_NONE,
|
||||
.bitmap = IRQ_BITMAP_NOLINK
|
||||
}
|
||||
}
|
||||
},
|
||||
}
|
||||
};
|
||||
|
||||
/**
|
||||
* Copy the IRQ routing table to memory.
|
||||
*
|
||||
* @param addr Destination address (between 0xF0000...0x100000).
|
||||
* @return The end address of the pirq routing table in memory.
|
||||
*/
|
||||
unsigned long write_pirq_routing_table(unsigned long addr)
|
||||
{
|
||||
return copy_pirq_routing_table(addr, &intel_irq_routing_table);
|
||||
}
|
@@ -1,41 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Juergen Beisert <juergen@kreuzholzen.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include <device/pci_def.h>
|
||||
#include <arch/io.h>
|
||||
#include <device/pnp_def.h>
|
||||
#include <console/console.h>
|
||||
#include "northbridge/amd/gx1/raminit.c"
|
||||
#include "superio/nsc/pc97317/early_serial.c"
|
||||
#include "cpu/x86/bist.h"
|
||||
#include "southbridge/amd/cs5530/enable_rom.c"
|
||||
|
||||
#define SERIAL_DEV PNP_DEV(0x2e, PC97317_SP1)
|
||||
|
||||
#include <cpu/intel/romstage.h>
|
||||
static void main(unsigned long bist)
|
||||
{
|
||||
pc97317_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE);
|
||||
console_init();
|
||||
report_bist_failure(bist);
|
||||
cs5530_enable_rom();
|
||||
sdram_init();
|
||||
}
|
@@ -1,5 +1,4 @@
|
||||
source src/northbridge/amd/amdk8/Kconfig
|
||||
source src/northbridge/amd/gx1/Kconfig
|
||||
source src/northbridge/amd/gx2/Kconfig
|
||||
source src/northbridge/amd/amdfam10/Kconfig
|
||||
source src/northbridge/amd/lx/Kconfig
|
||||
|
@@ -1,6 +1,5 @@
|
||||
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AMDFAM10) += amdfam10
|
||||
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AMDK8) += amdk8
|
||||
subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX1) += gx1
|
||||
subdirs-$(CONFIG_NORTHBRIDGE_AMD_GX2) += gx2
|
||||
subdirs-$(CONFIG_NORTHBRIDGE_AMD_LX) += lx
|
||||
subdirs-$(CONFIG_NORTHBRIDGE_AMD_AGESA) += agesa
|
||||
|
@@ -1,22 +0,0 @@
|
||||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
config NORTHBRIDGE_AMD_GX1
|
||||
bool
|
||||
|
@@ -1,21 +0,0 @@
|
||||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
ramstage-y += northbridge.c
|
@@ -1,162 +0,0 @@
|
||||
#include <console/console.h>
|
||||
#include <arch/io.h>
|
||||
#include <stdint.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <stdlib.h>
|
||||
#include <string.h>
|
||||
#include <cpu/amd/gx1def.h>
|
||||
#include <cpu/x86/cache.h>
|
||||
#include <cpu/cpu.h>
|
||||
|
||||
#define NORTHBRIDGE_FILE "northbridge.c"
|
||||
/*
|
||||
*/
|
||||
|
||||
static void optimize_xbus(device_t dev)
|
||||
{
|
||||
/* Optimise X-Bus performance */
|
||||
pci_write_config8(dev, 0x40, 0x1e);
|
||||
pci_write_config8(dev, 0x41, 0x52);
|
||||
pci_write_config8(dev, 0x43, 0xc1);
|
||||
pci_write_config8(dev, 0x44, 0x00);
|
||||
}
|
||||
|
||||
/**
|
||||
* Enables memory from 0xC0000 up to 0xFFFFF.
|
||||
* So this region is read/write and cache able
|
||||
*
|
||||
* FIXME: What about PCI master access into
|
||||
* this region?
|
||||
**/
|
||||
|
||||
static void enable_shadow(device_t dev)
|
||||
{
|
||||
write32(GX_BASE+BC_XMAP_2, 0x77777777);
|
||||
write32(GX_BASE+BC_XMAP_3, 0x77777777);
|
||||
}
|
||||
|
||||
static void northbridge_init(device_t dev)
|
||||
{
|
||||
printk(BIOS_DEBUG, "northbridge: %s()\n", __func__);
|
||||
|
||||
optimize_xbus(dev);
|
||||
enable_shadow(dev);
|
||||
printk(BIOS_SPEW, "Calling enable_cache()\n");
|
||||
enable_cache();
|
||||
}
|
||||
|
||||
|
||||
static struct device_operations northbridge_operations = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = northbridge_init,
|
||||
.enable = 0,
|
||||
.ops_pci = 0,
|
||||
};
|
||||
|
||||
static const struct pci_driver northbridge_driver __pci_driver = {
|
||||
.ops = &northbridge_operations,
|
||||
.vendor = PCI_VENDOR_ID_CYRIX,
|
||||
.device = PCI_DEVICE_ID_CYRIX_PCI_MASTER,
|
||||
};
|
||||
|
||||
#include <cbmem.h>
|
||||
|
||||
static void pci_domain_set_resources(device_t dev)
|
||||
{
|
||||
device_t mc_dev;
|
||||
uint32_t pci_tolm;
|
||||
|
||||
pci_tolm = find_pci_tolm(dev->link_list);
|
||||
mc_dev = dev->link_list->children;
|
||||
if (mc_dev) {
|
||||
unsigned int tomk, tolmk;
|
||||
unsigned int ramreg = 0;
|
||||
int i, idx;
|
||||
unsigned int *bcdramtop = (unsigned int *)(GX_BASE + BC_DRAM_TOP);
|
||||
unsigned int *mcgbaseadd = (unsigned int *)(GX_BASE + MC_GBASE_ADD);
|
||||
|
||||
for(i=0; i<0x20; i+= 0x10) {
|
||||
unsigned int *mcreg = (unsigned int *)(GX_BASE + MC_BANK_CFG);
|
||||
unsigned int mem_config = *mcreg;
|
||||
|
||||
if (((mem_config & (DIMM_PG_SZ << i)) >> (4 + i)) == 7)
|
||||
continue;
|
||||
ramreg += 1 << (((mem_config & (DIMM_SZ << i)) >> (i + 8)) + 2);
|
||||
}
|
||||
|
||||
tomk = ramreg << 10;
|
||||
|
||||
/* Sort out the framebuffer size */
|
||||
tomk -= CONFIG_VIDEO_MB * 1024;
|
||||
*bcdramtop = ((tomk << 10) - 1);
|
||||
*mcgbaseadd = (tomk >> 9);
|
||||
|
||||
printk(BIOS_DEBUG, "BC_DRAM_TOP = 0x%08x\n", *bcdramtop);
|
||||
printk(BIOS_DEBUG, "MC_GBASE_ADD = 0x%08x\n", *mcgbaseadd);
|
||||
|
||||
printk(BIOS_DEBUG, "I would set ram size to %d Mbytes\n", (tomk >> 10));
|
||||
|
||||
/* Compute the top of Low memory */
|
||||
tolmk = pci_tolm >> 10;
|
||||
if (tolmk >= tomk) {
|
||||
/* The PCI hole does does not overlap the memory.
|
||||
*/
|
||||
tolmk = tomk;
|
||||
}
|
||||
|
||||
set_top_of_ram(tolmk * 1024);
|
||||
|
||||
/* Report the memory regions */
|
||||
idx = 10;
|
||||
ram_resource(dev, idx++, 0, tolmk);
|
||||
}
|
||||
assign_resources(dev->link_list);
|
||||
}
|
||||
|
||||
static struct device_operations pci_domain_ops = {
|
||||
.read_resources = pci_domain_read_resources,
|
||||
.set_resources = pci_domain_set_resources,
|
||||
.enable_resources = NULL,
|
||||
.init = NULL,
|
||||
.scan_bus = pci_domain_scan_bus,
|
||||
.ops_pci_bus = pci_bus_default_ops,
|
||||
};
|
||||
|
||||
static void cpu_bus_init(device_t dev)
|
||||
{
|
||||
printk(BIOS_SPEW, "%s:%s()\n", NORTHBRIDGE_FILE, __func__);
|
||||
initialize_cpus(dev->link_list);
|
||||
}
|
||||
|
||||
static struct device_operations cpu_bus_ops = {
|
||||
.read_resources = DEVICE_NOOP,
|
||||
.set_resources = DEVICE_NOOP,
|
||||
.enable_resources = DEVICE_NOOP,
|
||||
.init = cpu_bus_init,
|
||||
.scan_bus = 0,
|
||||
};
|
||||
|
||||
static void enable_dev(struct device *dev)
|
||||
{
|
||||
printk(BIOS_SPEW, "%s:%s()\n", NORTHBRIDGE_FILE, __func__);
|
||||
/* Set the operations if it is a special bus type */
|
||||
if (dev->path.type == DEVICE_PATH_DOMAIN) {
|
||||
printk(BIOS_SPEW, "DEVICE_PATH_DOMAIN\n");
|
||||
dev->ops = &pci_domain_ops;
|
||||
}
|
||||
else if (dev->path.type == DEVICE_PATH_CPU_CLUSTER) {
|
||||
printk(BIOS_SPEW, "DEVICE_PATH_CPU_CLUSTER\n");
|
||||
dev->ops = &cpu_bus_ops;
|
||||
} else {
|
||||
printk(BIOS_SPEW, "device path type %d\n",dev->path.type);
|
||||
}
|
||||
}
|
||||
|
||||
struct chip_operations northbridge_amd_gx1_ops = {
|
||||
CHIP_NAME("AMD GX1 Northbridge")
|
||||
.enable_dev = enable_dev,
|
||||
};
|
@@ -1,354 +0,0 @@
|
||||
#include <cpu/amd/gx1def.h>
|
||||
|
||||
/*
|
||||
This software and ancillary information (herein called SOFTWARE )
|
||||
called LinuxBIOS is made available under the terms described
|
||||
here. The SOFTWARE has been approved for release with associated
|
||||
LA-CC Number 00-34 . Unless otherwise indicated, this SOFTWARE has
|
||||
been authored by an employee or employees of the University of
|
||||
California, operator of the Los Alamos National Laboratory under
|
||||
Contract No. W-7405-ENG-36 with the U.S. Department of Energy. The
|
||||
U.S. Government has rights to use, reproduce, and distribute this
|
||||
SOFTWARE. The public may copy, distribute, prepare derivative works
|
||||
and publicly display this SOFTWARE without charge, provided that this
|
||||
Notice and any statement of authorship are reproduced on all copies.
|
||||
Neither the Government nor the University makes any warranty, express
|
||||
or implied, or assumes any liability or responsibility for the use of
|
||||
this SOFTWARE. If SOFTWARE is modified to produce derivative works,
|
||||
such modified SOFTWARE should be clearly marked, so as not to confuse
|
||||
it with the version available from LANL.
|
||||
*/
|
||||
/* Copyright 2000, Ron Minnich, Advanced Computing Lab, LANL
|
||||
* rminnich@lanl.gov
|
||||
*/
|
||||
|
||||
/* SDRAM initialization for GX1 - translated from Christer Weinigel's
|
||||
assembler version into C.
|
||||
|
||||
Hamish Guthrie 10/4/2005 hamish@prodigi.ch
|
||||
*/
|
||||
|
||||
#define NUM_REFRESH 8
|
||||
#define TEST_DATA1 0x05A5A5A5A
|
||||
#define TEST_DATA2 0x0DEADBEEF
|
||||
|
||||
void setGX1Mem(unsigned int addr, unsigned int data)
|
||||
{
|
||||
write32(addr, data);
|
||||
}
|
||||
|
||||
unsigned int getGX1Mem(unsigned int addr)
|
||||
{
|
||||
return (unsigned int)read32(addr);
|
||||
}
|
||||
|
||||
void do_refresh(void)
|
||||
{
|
||||
unsigned int tval, i;
|
||||
|
||||
post_code(0x71);
|
||||
tval = getGX1Mem(GX_BASE + MC_MEM_CNTRL1);
|
||||
tval |= RFSHTST;
|
||||
for(i=0; i>NUM_REFRESH; i++)
|
||||
setGX1Mem(GX_BASE + MC_MEM_CNTRL1, tval);
|
||||
post_code(0x72);
|
||||
}
|
||||
|
||||
|
||||
void enable_dimm(void)
|
||||
{
|
||||
unsigned int tval, i;
|
||||
|
||||
post_code(0x73);
|
||||
|
||||
/* start SDCLCK's */
|
||||
tval = getGX1Mem(GX_BASE + MC_MEM_CNTRL1);
|
||||
tval &= ~SDCLKSTRT;
|
||||
setGX1Mem(GX_BASE + MC_MEM_CNTRL1, tval);
|
||||
tval |= SDCLKSTRT;
|
||||
setGX1Mem(GX_BASE + MC_MEM_CNTRL1, tval);
|
||||
|
||||
/* Unmask SDCLK's */
|
||||
tval = getGX1Mem(GX_BASE + MC_MEM_CNTRL2);
|
||||
tval &= ~(SDCLK_MASK | SDCLKOUT_MASK);
|
||||
setGX1Mem(GX_BASE + MC_MEM_CNTRL2, tval);
|
||||
tval = getGX1Mem(GX_BASE + MC_MEM_CNTRL2);
|
||||
|
||||
/* Wait for clocks to unmask */
|
||||
for(i=0; i<5000; i++)
|
||||
outb(0, 0xed);
|
||||
|
||||
/* Refresh memory */
|
||||
tval = getGX1Mem(GX_BASE + MC_MEM_CNTRL1);
|
||||
tval |= RFSHTST;
|
||||
for(i=0; i<NUM_REFRESH; i++)
|
||||
setGX1Mem(GX_BASE + MC_MEM_CNTRL1, tval);
|
||||
tval &= ~RFSHTST;
|
||||
|
||||
/* Start the SDCLK's */
|
||||
tval &= ~PROGRAM_SDRAM;
|
||||
setGX1Mem(GX_BASE + MC_MEM_CNTRL1, tval);
|
||||
tval |= PROGRAM_SDRAM | 0x00002000; /* Set refresh timing */
|
||||
setGX1Mem(GX_BASE + MC_MEM_CNTRL1, tval);
|
||||
tval &= ~PROGRAM_SDRAM;
|
||||
setGX1Mem(GX_BASE + MC_MEM_CNTRL1, tval);
|
||||
|
||||
/* Refresh memory again */
|
||||
tval = getGX1Mem(GX_BASE + MC_MEM_CNTRL1);
|
||||
tval |= RFSHTST;
|
||||
for(i=0; i>NUM_REFRESH; i++)
|
||||
setGX1Mem(GX_BASE + MC_MEM_CNTRL1, tval);
|
||||
|
||||
for(i=0; i<2000; i++)
|
||||
outb(0, 0xed);
|
||||
post_code(0x74);
|
||||
}
|
||||
|
||||
static unsigned int size_dimm(int dimm_shift)
|
||||
{
|
||||
int bank_cfg = 0x700; /* MC_BANK_CFG for 512M */
|
||||
unsigned int offset = 0x10000000; /* Offset 256M */
|
||||
int failed_flag = 1;
|
||||
|
||||
do {
|
||||
setGX1Mem(0, TEST_DATA1);
|
||||
setGX1Mem(offset, TEST_DATA2);
|
||||
setGX1Mem(0x100, 0); /* Clear the bus */
|
||||
if (getGX1Mem(0) != TEST_DATA1) {
|
||||
setGX1Mem(GX_BASE + MC_BANK_CFG,
|
||||
getGX1Mem(GX_BASE + MC_BANK_CFG) & ~(DIMM_SZ << dimm_shift));
|
||||
bank_cfg -= 0x100;
|
||||
setGX1Mem(GX_BASE + MC_BANK_CFG,
|
||||
getGX1Mem(GX_BASE + MC_BANK_CFG) | (bank_cfg << dimm_shift));
|
||||
do_refresh();
|
||||
offset >>= 1;
|
||||
} else {
|
||||
failed_flag = 0;
|
||||
break;
|
||||
}
|
||||
} while (bank_cfg >= 0);
|
||||
|
||||
if (failed_flag)
|
||||
return (0x0070 << dimm_shift);
|
||||
else
|
||||
return(getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_SZ << dimm_shift));
|
||||
|
||||
}
|
||||
|
||||
static unsigned int module_banks(int dimm_shift)
|
||||
{
|
||||
int page_size = 0x800; /* Smallest page = 1K * 2 banks */
|
||||
int comp_banks;
|
||||
|
||||
#if 0
|
||||
print_debug("MC_BANK_CFG = ");
|
||||
print_debug_hex32(getGX1Mem(GX_BASE + MC_BANK_CFG));
|
||||
print_debug("\n");
|
||||
#endif
|
||||
|
||||
/* retrieve the page size from the MC register */
|
||||
page_size <<= (((getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_PG_SZ << dimm_shift)) >> dimm_shift) >> 4);
|
||||
|
||||
#if 0
|
||||
print_debug(" page_size = ");
|
||||
print_debug_hex32(page_size);
|
||||
print_debug("\n");
|
||||
#endif
|
||||
|
||||
comp_banks = (((getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_COMP_BNK << dimm_shift)) >> dimm_shift) >> 12);
|
||||
page_size <<= comp_banks;
|
||||
|
||||
setGX1Mem(0, TEST_DATA1);
|
||||
setGX1Mem(page_size, TEST_DATA2);
|
||||
setGX1Mem(0x100, 0); /* Clear the bus */
|
||||
if (getGX1Mem(page_size) != TEST_DATA2) {
|
||||
setGX1Mem(GX_BASE + MC_BANK_CFG,
|
||||
getGX1Mem(GX_BASE + MC_BANK_CFG) & ~(DIMM_MOD_BNK << dimm_shift));
|
||||
do_refresh();
|
||||
}
|
||||
#if 0
|
||||
print_debug("MC_BANK_CFG = ");
|
||||
print_debug_hex32(getGX1Mem(GX_BASE + MC_BANK_CFG));
|
||||
print_debug("\n");
|
||||
#endif
|
||||
return(getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_MOD_BNK << dimm_shift));
|
||||
}
|
||||
|
||||
static unsigned int component_banks(int dimm_shift)
|
||||
{
|
||||
int page_size = 0x800; /* Smallest page = 1K * 2 banks */
|
||||
|
||||
#if 0
|
||||
print_debug("MC_BANK_CFG = ");
|
||||
print_debug_hex32(getGX1Mem(GX_BASE + MC_BANK_CFG));
|
||||
print_debug("\n");
|
||||
#endif
|
||||
|
||||
page_size = page_size << (((getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_PG_SZ << dimm_shift)) >> dimm_shift) >> 4);
|
||||
|
||||
#if 0
|
||||
print_debug(" page_size = ");
|
||||
print_debug_hex32(page_size);
|
||||
print_debug("\n");
|
||||
#endif
|
||||
|
||||
setGX1Mem(0, TEST_DATA1);
|
||||
setGX1Mem(page_size, TEST_DATA2);
|
||||
setGX1Mem(0x100, 0); /* Clear the bus */
|
||||
if (getGX1Mem(0) != TEST_DATA1) {
|
||||
setGX1Mem(GX_BASE + MC_BANK_CFG,
|
||||
getGX1Mem(GX_BASE + MC_BANK_CFG) & ~(DIMM_COMP_BNK << dimm_shift));
|
||||
do_refresh();
|
||||
}
|
||||
#if 0
|
||||
print_debug("MC_BANK_CFG = ");
|
||||
print_debug_hex32(getGX1Mem(GX_BASE + MC_BANK_CFG));
|
||||
print_debug("\n");
|
||||
#endif
|
||||
return(getGX1Mem(GX_BASE + MC_BANK_CFG) & (DIMM_COMP_BNK << dimm_shift));
|
||||
}
|
||||
|
||||
static unsigned int page_size(int dimm_shift)
|
||||
{
|
||||
unsigned int page_test_offset = 0x2000;
|
||||
unsigned int temp;
|
||||
int page_size_config = 0x40;
|
||||
unsigned int probe_config;
|
||||
|
||||
do {
|
||||
setGX1Mem(0, TEST_DATA1);
|
||||
setGX1Mem(page_test_offset, TEST_DATA2);
|
||||
setGX1Mem(0x100, 0);
|
||||
temp = getGX1Mem(0);
|
||||
setGX1Mem(0, 0);
|
||||
if(temp == TEST_DATA1) {
|
||||
#if 0
|
||||
print_debug(" Page size Config = ");
|
||||
print_debug_hex32(page_size_config << dimm_shift);
|
||||
print_debug("\n");
|
||||
#endif
|
||||
return(page_size_config << dimm_shift);
|
||||
}
|
||||
|
||||
temp = ~(DIMM_PG_SZ << dimm_shift);
|
||||
|
||||
probe_config = getGX1Mem(GX_BASE + MC_BANK_CFG);
|
||||
probe_config &= temp;
|
||||
|
||||
page_size_config -= 0x10;
|
||||
page_size_config <<= dimm_shift;
|
||||
|
||||
probe_config |= page_size_config;
|
||||
|
||||
page_size_config >>= dimm_shift;
|
||||
|
||||
page_test_offset >>= 1;
|
||||
|
||||
setGX1Mem(GX_BASE + MC_BANK_CFG, probe_config);
|
||||
do_refresh();
|
||||
} while (page_size_config >= 0);
|
||||
|
||||
return 0x70;
|
||||
}
|
||||
|
||||
static int dimm_detect(int dimm_shift)
|
||||
{
|
||||
unsigned int test;
|
||||
|
||||
print_debug("Probing for DIMM");
|
||||
print_debug_char((dimm_shift >> 4) + 0x30);
|
||||
print_debug("\n");
|
||||
|
||||
setGX1Mem(0, TEST_DATA1);
|
||||
setGX1Mem(0x100, 0);
|
||||
test = getGX1Mem(0);
|
||||
setGX1Mem(0, 0);
|
||||
|
||||
if (test != TEST_DATA1)
|
||||
return 0;
|
||||
|
||||
print_debug(" Found DIMM");
|
||||
print_debug_char((dimm_shift >> 4) + 0x30);
|
||||
print_debug("\n");
|
||||
|
||||
return 1;
|
||||
}
|
||||
|
||||
static int size_memory(int dimm_shift, unsigned int mem_config)
|
||||
{
|
||||
|
||||
if (!dimm_detect(dimm_shift))
|
||||
return (mem_config);
|
||||
|
||||
mem_config &= (~(DIMM_PG_SZ << dimm_shift));
|
||||
mem_config |= (page_size(dimm_shift));
|
||||
|
||||
print_debug(" Page Size: ");
|
||||
print_debug_hex32(0x400 << ((mem_config & (DIMM_PG_SZ << dimm_shift)) >> (dimm_shift + 4)));
|
||||
print_debug("\n");
|
||||
|
||||
/* Now do component banks detection */
|
||||
|
||||
mem_config &= (~(DIMM_COMP_BNK << dimm_shift));
|
||||
mem_config |= (component_banks(dimm_shift));
|
||||
|
||||
print_debug(" Component Banks: ");
|
||||
print_debug_char((((mem_config & (DIMM_COMP_BNK << dimm_shift)) >> (dimm_shift + 12)) ? 4 : 2) + 0x30);
|
||||
print_debug("\n");
|
||||
|
||||
/* Now do module banks */
|
||||
|
||||
mem_config &= (~(DIMM_MOD_BNK << dimm_shift));
|
||||
mem_config |= (module_banks(dimm_shift));
|
||||
|
||||
print_debug(" Module Banks: ");
|
||||
print_debug_char((((mem_config & (DIMM_MOD_BNK << dimm_shift)) >> (dimm_shift + 14)) ? 2 : 1) + 0x30);
|
||||
print_debug("\n");
|
||||
|
||||
mem_config &= (~(DIMM_SZ << dimm_shift));
|
||||
mem_config |= (size_dimm(dimm_shift));
|
||||
|
||||
print_debug(" DIMM size: ");
|
||||
print_debug_hex32(1 <<
|
||||
((mem_config & (DIMM_SZ << dimm_shift)) >> (dimm_shift + 8)) + 22);
|
||||
print_debug("\n");
|
||||
|
||||
return (mem_config);
|
||||
}
|
||||
|
||||
static void sdram_init(void)
|
||||
{
|
||||
unsigned int mem_config = 0x00700070;
|
||||
|
||||
print_debug("Setting up default parameters for memory\n");
|
||||
post_code(0x70);
|
||||
|
||||
setGX1Mem(GX_BASE + MC_MEM_CNTRL2, 0x000007d8); /* Disable all CLKS, Shift = 3 */
|
||||
setGX1Mem(GX_BASE + MC_MEM_CNTRL1, 0x92140000); /* MD_DS=2, MA_DS=2, CNTL_DS=2 SDCLKRATE=4 */
|
||||
setGX1Mem(GX_BASE + MC_BANK_CFG, 0x00700070); /* No DIMMS installed */
|
||||
setGX1Mem(GX_BASE + MC_SYNC_TIM1, 0x3a733225); /* LTMODE=3, RC=10, RAS=7, RP=3, RCD=3, RRD=2, DPL=2 */
|
||||
setGX1Mem(GX_BASE + MC_BANK_CFG, 0x57405740); /* Largest DIMM size
|
||||
0x4000 -- 2 module banks
|
||||
0x1000 -- 4 component banks
|
||||
0x0700 -- DIMM size 512MB
|
||||
0x0040 -- Page Size 16kB */
|
||||
|
||||
enable_dimm();
|
||||
|
||||
print_debug("Sizing memory\n");
|
||||
|
||||
setGX1Mem(GX_BASE + MC_BANK_CFG, 0x00705740);
|
||||
do_refresh();
|
||||
mem_config = size_memory(0, mem_config);
|
||||
setGX1Mem(GX_BASE + MC_BANK_CFG, 0x57400070);
|
||||
do_refresh();
|
||||
mem_config = size_memory(16, mem_config);
|
||||
|
||||
print_debug("MC_BANK_CFG = ");
|
||||
print_debug_hex32(mem_config);
|
||||
print_debug("\n");
|
||||
|
||||
setGX1Mem(GX_BASE + MC_BANK_CFG, mem_config);
|
||||
enable_dimm();
|
||||
post_code(0x7e);
|
||||
}
|
@@ -1,11 +0,0 @@
|
||||
#ifndef RAMINIT_H
|
||||
#define RAMINIT_H
|
||||
|
||||
#define DIMM_SOCKETS 4
|
||||
struct mem_controller {
|
||||
device_t d0;
|
||||
uint16_t channel0[DIMM_SOCKETS];
|
||||
};
|
||||
|
||||
|
||||
#endif /* RAMINIT_H */
|
@@ -4,7 +4,6 @@ source src/southbridge/amd/cs5536/Kconfig
|
||||
#source src/southbridge/amd/amd8131-disable/Kconfig
|
||||
source src/southbridge/amd/amd8132/Kconfig
|
||||
source src/southbridge/amd/amd8151/Kconfig
|
||||
source src/southbridge/amd/cs5530/Kconfig
|
||||
source src/southbridge/amd/cs5535/Kconfig
|
||||
source src/southbridge/amd/rs690/Kconfig
|
||||
source src/southbridge/amd/sb600/Kconfig
|
||||
|
@@ -8,7 +8,6 @@ subdirs-$(CONFIG_SOUTHBRIDGE_AMD_RS780) += rs780
|
||||
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SB700) += sb700
|
||||
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SB800) += sb800
|
||||
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_SR5650) += sr5650
|
||||
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5530) += cs5530
|
||||
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5535) += cs5535
|
||||
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CS5536) += cs5536
|
||||
subdirs-$(CONFIG_SOUTHBRIDGE_AMD_CIMX_SB700) += cimx
|
||||
|
@@ -1,74 +0,0 @@
|
||||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; version 2 of the License.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
config SOUTHBRIDGE_AMD_CS5530
|
||||
bool
|
||||
|
||||
menu "AMD Geode GX1 video support"
|
||||
depends on SOUTHBRIDGE_AMD_CS5530
|
||||
|
||||
config GX1_VIDEO
|
||||
bool "AMD Geode GX1 video mode support"
|
||||
default y
|
||||
depends on SOUTHBRIDGE_AMD_CS5530
|
||||
|
||||
choice
|
||||
prompt "AMD Geode GX1 video mode"
|
||||
default GX1_VIDEOMODE_0
|
||||
depends on GX1_VIDEO
|
||||
|
||||
config GX1_VIDEOMODE_0
|
||||
bool "640x480"
|
||||
config GX1_VIDEOMODE_1
|
||||
bool "800x600"
|
||||
config GX1_VIDEOMODE_2
|
||||
bool "1024x768"
|
||||
config GX1_VIDEOMODE_3
|
||||
bool "1280x960"
|
||||
config GX1_VIDEOMODE_4
|
||||
bool "1280x1024"
|
||||
|
||||
endchoice
|
||||
|
||||
config GX1_VIDEOMODE
|
||||
int
|
||||
default 0 if GX1_VIDEOMODE_0
|
||||
default 1 if GX1_VIDEOMODE_1
|
||||
default 2 if GX1_VIDEOMODE_2
|
||||
default 3 if GX1_VIDEOMODE_3
|
||||
default 4 if GX1_VIDEOMODE_4
|
||||
depends on GX1_VIDEO
|
||||
|
||||
# TODO: Check how much RAM each of the modes actually needs.
|
||||
config VIDEO_MB
|
||||
int
|
||||
default 2 if GX1_VIDEOMODE_0
|
||||
default 2 if GX1_VIDEOMODE_1
|
||||
default 2 if GX1_VIDEOMODE_2
|
||||
default 2 if GX1_VIDEOMODE_3
|
||||
default 2 if GX1_VIDEOMODE_4
|
||||
depends on GX1_VIDEO
|
||||
|
||||
config SPLASH_GRAPHIC
|
||||
bool "Enable splash screen on AMD Geode GX1 boards"
|
||||
default y
|
||||
depends on GX1_VIDEO
|
||||
|
||||
endmenu
|
||||
|
@@ -1,25 +0,0 @@
|
||||
##
|
||||
## This file is part of the coreboot project.
|
||||
##
|
||||
## Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
##
|
||||
## This program is free software; you can redistribute it and/or modify
|
||||
## it under the terms of the GNU General Public License as published by
|
||||
## the Free Software Foundation; either version 2 of the License, or
|
||||
## (at your option) any later version.
|
||||
##
|
||||
## This program is distributed in the hope that it will be useful,
|
||||
## but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
## GNU General Public License for more details.
|
||||
##
|
||||
## You should have received a copy of the GNU General Public License
|
||||
## along with this program; if not, write to the Free Software
|
||||
## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
##
|
||||
|
||||
ramstage-y += cs5530.c
|
||||
ramstage-y += isa.c
|
||||
ramstage-y += ide.c
|
||||
ramstage-y += vga.c
|
||||
ramstage-y += pirq.c
|
@@ -1,304 +0,0 @@
|
||||
/* do not edit
|
||||
This is an image of size 51 x 60 with 234 colours */
|
||||
static const int width=51;
|
||||
static const int height=60;
|
||||
static const int colours=234;
|
||||
static const unsigned long colour_map[234] = {
|
||||
0x00000000, /* 0 */
|
||||
0x00000001, /* 1 */
|
||||
0x00000020, /* 2 */
|
||||
0x00000021, /* 3 */
|
||||
0x00000040, /* 4 */
|
||||
0x00000800, /* 5 */
|
||||
0x00000821, /* 6 */
|
||||
0x00000840, /* 7 */
|
||||
0x00000841, /* 8 */
|
||||
0x00000861, /* 9 */
|
||||
0x00001040, /* 10 */
|
||||
0x00001081, /* 11 */
|
||||
0x00001082, /* 12 */
|
||||
0x00001083, /* 13 */
|
||||
0x000010A2, /* 14 */
|
||||
0x00001881, /* 15 */
|
||||
0x000018C3, /* 16 */
|
||||
0x000018E3, /* 17 */
|
||||
0x000020A0, /* 18 */
|
||||
0x000020E4, /* 19 */
|
||||
0x00002103, /* 20 */
|
||||
0x00002104, /* 21 */
|
||||
0x00002124, /* 22 */
|
||||
0x00002921, /* 23 */
|
||||
0x00002945, /* 24 */
|
||||
0x00002946, /* 25 */
|
||||
0x00002965, /* 26 */
|
||||
0x00002966, /* 27 */
|
||||
0x00003186, /* 28 */
|
||||
0x000031A6, /* 29 */
|
||||
0x00003942, /* 30 */
|
||||
0x00003982, /* 31 */
|
||||
0x000039A7, /* 32 */
|
||||
0x000039C7, /* 33 */
|
||||
0x000039E7, /* 34 */
|
||||
0x000039E8, /* 35 */
|
||||
0x000041A2, /* 36 */
|
||||
0x000041C2, /* 37 */
|
||||
0x000041E7, /* 38 */
|
||||
0x00004207, /* 39 */
|
||||
0x00004208, /* 40 */
|
||||
0x00004228, /* 41 */
|
||||
0x00004229, /* 42 */
|
||||
0x000049E3, /* 43 */
|
||||
0x000049E5, /* 44 */
|
||||
0x00004A46, /* 45 */
|
||||
0x00004A47, /* 46 */
|
||||
0x00004A48, /* 47 */
|
||||
0x00004A49, /* 48 */
|
||||
0x00004A69, /* 49 */
|
||||
0x00004A8A, /* 50 */
|
||||
0x00005228, /* 51 */
|
||||
0x00005247, /* 52 */
|
||||
0x00005287, /* 53 */
|
||||
0x0000528A, /* 54 */
|
||||
0x000052AA, /* 55 */
|
||||
0x00005A21, /* 56 */
|
||||
0x00005A43, /* 57 */
|
||||
0x00005A63, /* 58 */
|
||||
0x00005AA9, /* 59 */
|
||||
0x00005AAA, /* 60 */
|
||||
0x00005ACA, /* 61 */
|
||||
0x00005ACB, /* 62 */
|
||||
0x00005AEB, /* 63 */
|
||||
0x00006222, /* 64 */
|
||||
0x00006261, /* 65 */
|
||||
0x000062A8, /* 66 */
|
||||
0x000062C7, /* 67 */
|
||||
0x000062E8, /* 68 */
|
||||
0x000062EB, /* 69 */
|
||||
0x000062EC, /* 70 */
|
||||
0x0000630B, /* 71 */
|
||||
0x0000630C, /* 72 */
|
||||
0x0000632C, /* 73 */
|
||||
0x00006A41, /* 74 */
|
||||
0x00006B05, /* 75 */
|
||||
0x00006B28, /* 76 */
|
||||
0x00006B29, /* 77 */
|
||||
0x00006B2D, /* 78 */
|
||||
0x00006B4D, /* 79 */
|
||||
0x00006B6D, /* 80 */
|
||||
0x00006B6E, /* 81 */
|
||||
0x00006B8D, /* 82 */
|
||||
0x000072A2, /* 83 */
|
||||
0x000072E2, /* 84 */
|
||||
0x000072E5, /* 85 */
|
||||
0x00007306, /* 86 */
|
||||
0x00007329, /* 87 */
|
||||
0x0000738E, /* 88 */
|
||||
0x000073AE, /* 89 */
|
||||
0x000073AF, /* 90 */
|
||||
0x000073CF, /* 91 */
|
||||
0x00007B28, /* 92 */
|
||||
0x00007B44, /* 93 */
|
||||
0x00007B48, /* 94 */
|
||||
0x00007B67, /* 95 */
|
||||
0x00007B69, /* 96 */
|
||||
0x00007BCE, /* 97 */
|
||||
0x00007BCF, /* 98 */
|
||||
0x00007BEF, /* 99 */
|
||||
0x00008323, /* 100 */
|
||||
0x00008345, /* 101 */
|
||||
0x000083AA, /* 102 */
|
||||
0x00008410, /* 103 */
|
||||
0x00008430, /* 104 */
|
||||
0x00008B02, /* 105 */
|
||||
0x00008B63, /* 106 */
|
||||
0x00008B83, /* 107 */
|
||||
0x00008B84, /* 108 */
|
||||
0x00008BA6, /* 109 */
|
||||
0x00008BC7, /* 110 */
|
||||
0x00008BEA, /* 111 */
|
||||
0x00008BEE, /* 112 */
|
||||
0x00008C51, /* 113 */
|
||||
0x00008C71, /* 114 */
|
||||
0x00009362, /* 115 */
|
||||
0x00009363, /* 116 */
|
||||
0x00009383, /* 117 */
|
||||
0x000093C5, /* 118 */
|
||||
0x000093C7, /* 119 */
|
||||
0x00009405, /* 120 */
|
||||
0x00009492, /* 121 */
|
||||
0x00009493, /* 122 */
|
||||
0x000094B2, /* 123 */
|
||||
0x00009B82, /* 124 */
|
||||
0x00009BC3, /* 125 */
|
||||
0x00009C2D, /* 126 */
|
||||
0x00009CB3, /* 127 */
|
||||
0x00009CD3, /* 128 */
|
||||
0x00009CF3, /* 129 */
|
||||
0x00009CF4, /* 130 */
|
||||
0x00009D14, /* 131 */
|
||||
0x0000A401, /* 132 */
|
||||
0x0000A403, /* 133 */
|
||||
0x0000A423, /* 134 */
|
||||
0x0000A44C, /* 135 */
|
||||
0x0000A489, /* 136 */
|
||||
0x0000A4F1, /* 137 */
|
||||
0x0000A514, /* 138 */
|
||||
0x0000A533, /* 139 */
|
||||
0x0000A534, /* 140 */
|
||||
0x0000ABE1, /* 141 */
|
||||
0x0000AC22, /* 142 */
|
||||
0x0000AC24, /* 143 */
|
||||
0x0000AC42, /* 144 */
|
||||
0x0000AC44, /* 145 */
|
||||
0x0000AC48, /* 146 */
|
||||
0x0000AC69, /* 147 */
|
||||
0x0000AC8A, /* 148 */
|
||||
0x0000ACEE, /* 149 */
|
||||
0x0000AD0A, /* 150 */
|
||||
0x0000AD2E, /* 151 */
|
||||
0x0000AD55, /* 152 */
|
||||
0x0000AD75, /* 153 */
|
||||
0x0000AD76, /* 154 */
|
||||
0x0000B423, /* 155 */
|
||||
0x0000B441, /* 156 */
|
||||
0x0000B444, /* 157 */
|
||||
0x0000B464, /* 158 */
|
||||
0x0000B484, /* 159 */
|
||||
0x0000B4A3, /* 160 */
|
||||
0x0000B4C4, /* 161 */
|
||||
0x0000B533, /* 162 */
|
||||
0x0000B596, /* 163 */
|
||||
0x0000B5B6, /* 164 */
|
||||
0x0000BC65, /* 165 */
|
||||
0x0000BC83, /* 166 */
|
||||
0x0000BC84, /* 167 */
|
||||
0x0000BCC9, /* 168 */
|
||||
0x0000BD03, /* 169 */
|
||||
0x0000BD2A, /* 170 */
|
||||
0x0000BD54, /* 171 */
|
||||
0x0000BD97, /* 172 */
|
||||
0x0000BDB5, /* 173 */
|
||||
0x0000BDD7, /* 174 */
|
||||
0x0000BDD8, /* 175 */
|
||||
0x0000BDF7, /* 176 */
|
||||
0x0000BE19, /* 177 */
|
||||
0x0000C4A2, /* 178 */
|
||||
0x0000C4C2, /* 179 */
|
||||
0x0000C4C3, /* 180 */
|
||||
0x0000C5CE, /* 181 */
|
||||
0x0000C5F9, /* 182 */
|
||||
0x0000C618, /* 183 */
|
||||
0x0000C61A, /* 184 */
|
||||
0x0000C638, /* 185 */
|
||||
0x0000CCE2, /* 186 */
|
||||
0x0000CD03, /* 187 */
|
||||
0x0000CD43, /* 188 */
|
||||
0x0000CD61, /* 189 */
|
||||
0x0000CD88, /* 190 */
|
||||
0x0000CE39, /* 191 */
|
||||
0x0000CE58, /* 192 */
|
||||
0x0000CE59, /* 193 */
|
||||
0x0000CE79, /* 194 */
|
||||
0x0000CE7A, /* 195 */
|
||||
0x0000CE7B, /* 196 */
|
||||
0x0000CE9A, /* 197 */
|
||||
0x0000D502, /* 198 */
|
||||
0x0000D522, /* 199 */
|
||||
0x0000D62C, /* 200 */
|
||||
0x0000D69A, /* 201 */
|
||||
0x0000D69B, /* 202 */
|
||||
0x0000D6BA, /* 203 */
|
||||
0x0000DD23, /* 204 */
|
||||
0x0000DD41, /* 205 */
|
||||
0x0000DD81, /* 206 */
|
||||
0x0000DDA1, /* 207 */
|
||||
0x0000DDA4, /* 208 */
|
||||
0x0000DE9C, /* 209 */
|
||||
0x0000DEDB, /* 210 */
|
||||
0x0000DEFB, /* 211 */
|
||||
0x0000DEFD, /* 212 */
|
||||
0x0000E5A2, /* 213 */
|
||||
0x0000E71C, /* 214 */
|
||||
0x0000E73C, /* 215 */
|
||||
0x0000EDC1, /* 216 */
|
||||
0x0000EF3E, /* 217 */
|
||||
0x0000EF5D, /* 218 */
|
||||
0x0000EF7D, /* 219 */
|
||||
0x0000EF7E, /* 220 */
|
||||
0x0000EF7F, /* 221 */
|
||||
0x0000F79D, /* 222 */
|
||||
0x0000F79E, /* 223 */
|
||||
0x0000F7BE, /* 224 */
|
||||
0x0000F7BF, /* 225 */
|
||||
0x0000F7DE, /* 226 */
|
||||
0x0000FFB8, /* 227 */
|
||||
0x0000FFBF, /* 228 */
|
||||
0x0000FFDD, /* 229 */
|
||||
0x0000FFDE, /* 230 */
|
||||
0x0000FFDF, /* 231 */
|
||||
0x0000FFFB, /* 232 */
|
||||
0x0000FFFF, /* 233 */
|
||||
};
|
||||
|
||||
static const unsigned char bitmap[3060] = {
|
||||
0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE7,0xA4,0xD3,0xE9,0xDF,0xDF,0x8C,0xE7,0xE0,0xDF,0xB0,0xDB,0xE7,0xE0,0xE0,0xC2,0xE7,0xE7,0xE0,0xD3,0xE9,0xE9,0xE0,0xDF,0xDF,0xE7,0xE7,0xD6,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,
|
||||
0xE9,0xE9,0xE9,0xE9,0xE0,0xDB,0xDA,0xDF,0xE9,0x67,0xA3,0xD7,0xDA,0xE9,0x71,0xD7,0xA3,0xE9,0xD6,0xD7,0xD2,0xD6,0xE9,0xC1,0xDF,0x68,0xE9,0xDA,0xE0,0x99,0xAE,0xE9,0xD7,0xB9,0xE9,0xA3,0xDF,0xE0,0xE7,0xE7,0xE7,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,
|
||||
0xE9,0xE9,0xE9,0xD6,0x71,0x67,0x63,0x72,0xE9,0x31,0x4F,0x58,0x99,0xD6,0x1D,0x67,0x50,0xB7,0x67,0x36,0x4F,0x99,0xD6,0x28,0x49,0x3F,0xDB,0x71,0x48,0x48,0x80,0xDB,0x37,0x48,0xE9,0x8C,0x58,0x68,0xDA,0xDB,0xDF,0xE0,0xE7,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,
|
||||
0xE9,0xE9,0xE9,0x79,0x63,0x63,0x58,0x29,0x7B,0x1A,0x28,0x30,0x30,0x63,0x0C,0x50,0x10,0x50,0x28,0x21,0x1D,0x31,0x62,0x11,0x36,0x10,0x68,0x30,0x30,0x16,0x3E,0x68,0x15,0x29,0x8C,0x3E,0x11,0x36,0x4F,0xC2,0xD7,0xDA,0xDF,0xE7,0xE7,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,
|
||||
0xE9,0xE9,0xE7,0x62,0x62,0x63,0x63,0x22,0x37,0x16,0x28,0x36,0x1C,0x28,0x0C,0x49,0x15,0x29,0x16,0x21,0x1D,0x22,0x22,0x0C,0x31,0x11,0x29,0x15,0x21,0x15,0x22,0x22,0x10,0x22,0x48,0x1D,0x08,0x3E,0x29,0x3E,0xB9,0xD2,0xD7,0xDB,0xE0,0xE7,0xE9,0xE9,0xE9,0xE9,0xE9,
|
||||
0xE9,0xE9,0xDB,0x62,0x4F,0x4F,0x3F,0x30,0x21,0x15,0x28,0x31,0x22,0x1A,0x0C,0x50,0x18,0x1D,0x0E,0x29,0x1D,0x22,0x16,0x10,0x37,0x1D,0x1D,0x0C,0x28,0x1A,0x29,0x1A,0x18,0x21,0x21,0x16,0x0E,0x3E,0x29,0x30,0x48,0xB0,0xC9,0xD3,0xDB,0xE0,0xE7,0xE9,0xE9,0xE9,0xE9,
|
||||
0xE9,0xE9,0xE7,0xA3,0x72,0x21,0x15,0x31,0x36,0x30,0x49,0x36,0x3F,0x29,0x30,0x4F,0x29,0x36,0x21,0x3F,0x28,0x30,0x1A,0x28,0x3E,0x22,0x18,0x16,0x3E,0x1D,0x21,0x11,0x22,0x21,0x10,0x11,0x37,0x11,0x15,0x28,0x48,0x80,0xA4,0xC1,0xD3,0xDA,0xE0,0xE7,0xE9,0xE9,0xE9,
|
||||
0xE9,0xD3,0xE9,0xE9,0xE9,0xB7,0x59,0x22,0x58,0x48,0x48,0x48,0x37,0x37,0x3E,0x36,0x36,0x36,0x36,0x37,0x31,0x36,0x36,0x37,0x36,0x30,0x29,0x31,0x36,0x30,0x31,0x31,0x31,0x30,0x30,0x37,0x15,0x15,0xC1,0xE9,0xE9,0x8A,0x59,0x99,0xC1,0xD3,0xDB,0xE0,0xE9,0xE9,0xE9,
|
||||
0xE9,0x68,0x50,0x1C,0x16,0x31,0x30,0x1A,0x58,0x49,0x3F,0x3E,0x3E,0x37,0x36,0x37,0x31,0x30,0x30,0x31,0x36,0x30,0x29,0x29,0x29,0x29,0x28,0x28,0x29,0x22,0x28,0x22,0x29,0x29,0x30,0x31,0x15,0x1C,0x59,0x50,0x36,0x36,0x49,0x7B,0xA3,0xC2,0xD6,0xDB,0xE7,0xE9,0xE9,
|
||||
0xE9,0xA4,0x50,0x58,0x36,0x29,0x37,0x4F,0x50,0x3F,0x3E,0x31,0x31,0x31,0x36,0x36,0x36,0x31,0x30,0x30,0x29,0x30,0x30,0x29,0x28,0x22,0x28,0x28,0x22,0x28,0x22,0x21,0x22,0x22,0x22,0x36,0x28,0x29,0x1A,0x15,0x0C,0x1A,0x37,0x63,0x80,0xAE,0xC9,0xD7,0xDF,0xE7,0xE9,
|
||||
0xE9,0xE7,0xC9,0x80,0x28,0x16,0x15,0x15,0x49,0x37,0x37,0x37,0x30,0x30,0x29,0x30,0x31,0x30,0x29,0x29,0x28,0x36,0x28,0x28,0x48,0x29,0x21,0x22,0x28,0x21,0x21,0x22,0x1D,0x22,0x22,0x30,0x21,0x16,0x1C,0x21,0x31,0x31,0x37,0x4F,0x68,0x8C,0xB7,0xD3,0xDB,0xE7,0xE9,
|
||||
0xE9,0xC2,0xE9,0xDA,0xB0,0x4F,0x1D,0x1D,0x4F,0x37,0x31,0x36,0x36,0x30,0x30,0x30,0x31,0x29,0x30,0x28,0x36,0x81,0x50,0x15,0x0C,0x31,0x28,0x21,0x22,0x22,0x22,0x21,0x22,0x21,0x1D,0x28,0x0E,0x11,0x81,0xDF,0xE0,0x80,0x36,0x3E,0x59,0x7B,0xA4,0xC9,0xDA,0xE0,0xE9,
|
||||
0xE7,0x72,0x67,0x3E,0x37,0x36,0x16,0x28,0x49,0x37,0x36,0x30,0x30,0x30,0x29,0x30,0x29,0x30,0x22,0x28,0x49,0xB7,0xB9,0x99,0x29,0x0E,0x31,0x28,0x1D,0x21,0x22,0x1D,0x1D,0x22,0x21,0x28,0x11,0x22,0x8C,0x98,0x8A,0x4F,0x30,0x36,0x4F,0x71,0x99,0xC2,0xD7,0xE0,0xE7,
|
||||
0xDF,0x80,0x3E,0x18,0x10,0x21,0x31,0x3F,0x48,0x36,0x36,0x30,0x30,0x29,0x30,0x30,0x30,0x29,0x28,0x28,0x50,0xA4,0x8C,0x98,0xA4,0x3E,0x10,0x31,0x22,0x22,0x1D,0x1D,0x22,0x21,0x22,0x22,0x18,0x30,0x10,0x09,0x08,0x0C,0x1D,0x30,0x49,0x68,0x98,0xC1,0xD6,0xDF,0xE7,
|
||||
0xE9,0xE7,0xB0,0x50,0x22,0x28,0x22,0x28,0x3E,0x36,0x31,0x30,0x30,0x30,0x29,0x29,0x29,0x28,0x29,0x28,0x4F,0x80,0x48,0x48,0x63,0x98,0x3F,0x16,0x29,0x21,0x1D,0x21,0x21,0x1D,0x21,0x22,0x1D,0x21,0x29,0x31,0x1D,0x1A,0x22,0x30,0x48,0x67,0x8C,0xB9,0xD6,0xDF,0xE7,
|
||||
0xDF,0xD3,0xE9,0xD7,0x81,0x31,0x10,0x16,0x3E,0x36,0x31,0x30,0x29,0x30,0x29,0x29,0x28,0x28,0x28,0x28,0x37,0x67,0x48,0x48,0x47,0x50,0x7B,0x36,0x1A,0x30,0x1D,0x1D,0x1D,0x21,0x21,0x21,0x10,0x15,0x63,0xC1,0xC1,0x62,0x31,0x30,0x48,0x67,0x8C,0xB9,0xD6,0xDF,0xE7,
|
||||
0xE0,0x8A,0xAE,0x67,0x4F,0x37,0x18,0x22,0x3F,0x36,0x30,0x30,0x29,0x22,0x29,0x29,0x22,0x28,0x28,0x21,0x29,0x61,0x47,0x47,0x48,0x48,0x4F,0x79,0x31,0x22,0x37,0x1D,0x1D,0x1D,0x1C,0x21,0x15,0x36,0xC1,0xD6,0xB7,0x59,0x28,0x30,0x48,0x63,0x8A,0xB9,0xD6,0xDF,0xE7,
|
||||
0xD2,0x59,0x36,0x10,0x0C,0x1C,0x15,0x29,0x3F,0x30,0x36,0x30,0x30,0x28,0x22,0x1D,0x28,0x31,0x22,0x21,0x22,0x3E,0x48,0x48,0x48,0x48,0x48,0x50,0x68,0x30,0x30,0x28,0x1D,0x1C,0x21,0x1D,0x11,0x1C,0x0C,0x00,0x02,0x09,0x21,0x30,0x48,0x63,0x8A,0xB9,0xD6,0xDF,0xE7,
|
||||
0xE9,0xDB,0x80,0x4F,0x30,0x3E,0x48,0x49,0x36,0x30,0x31,0x30,0x29,0x22,0x2E,0x2D,0x4C,0x6D,0x76,0x94,0x4D,0x31,0x4E,0x48,0x47,0x48,0x48,0x48,0x50,0x62,0x30,0x37,0x1D,0x1D,0x1D,0x1D,0x21,0x29,0x22,0x21,0x1C,0x16,0x21,0x30,0x48,0x63,0x8C,0xB9,0xD6,0xDF,0xE7,
|
||||
0xE7,0xE0,0xB9,0x72,0x1D,0x16,0x10,0x16,0x36,0x29,0x29,0x30,0x29,0x44,0xB5,0xC8,0x5D,0x6E,0x9E,0x9D,0x78,0x5F,0x70,0x46,0x47,0x47,0x48,0x3F,0x3F,0x58,0x4F,0x36,0x36,0x1A,0x1A,0x1C,0x15,0x10,0x1D,0x49,0x63,0x37,0x36,0x30,0x48,0x67,0x8C,0xB9,0xD6,0xDF,0xE7,
|
||||
0xDA,0xAE,0xE9,0xC2,0x8A,0x3F,0x1A,0x21,0x31,0x29,0x29,0x28,0x29,0x89,0xE5,0xE3,0xAA,0x66,0x38,0x4A,0x41,0x40,0x5C,0x45,0x3E,0x3E,0x3E,0x3E,0x3E,0x3F,0x58,0x48,0x48,0x31,0x18,0x21,0x10,0x21,0xD7,0xE9,0xE7,0x80,0x30,0x30,0x48,0x67,0x8C,0xB9,0xD6,0xDF,0xE7,
|
||||
0xD2,0x62,0x62,0x29,0x28,0x28,0x11,0x22,0x36,0x28,0x28,0x28,0x29,0x7E,0xE4,0xE8,0x96,0x3A,0x86,0x8E,0x85,0x75,0x53,0x57,0x3C,0x37,0x37,0x37,0x37,0x37,0x3E,0x4F,0x49,0x4F,0x1C,0x1C,0x16,0x1D,0x31,0x31,0x22,0x1D,0x21,0x30,0x48,0x67,0x8C,0xB9,0xD6,0xDF,0xE7,
|
||||
0xDA,0xB0,0x62,0x16,0x10,0x21,0x31,0x48,0x37,0x28,0x28,0x3B,0x6F,0x78,0x95,0x97,0x64,0xA1,0xCF,0xCE,0xC6,0xBB,0x90,0x65,0x3B,0x32,0x36,0x36,0x36,0x31,0x36,0x3F,0x4F,0x4F,0x37,0x1C,0x18,0x22,0x16,0x10,0x0E,0x0C,0x1D,0x30,0x48,0x63,0x8C,0xB9,0xD6,0xDF,0xE7,
|
||||
0xE9,0xE0,0x98,0x37,0x1C,0x22,0x22,0x21,0x30,0x31,0x88,0xA5,0xA7,0xB2,0x9F,0x91,0x9F,0xB4,0xC7,0xD0,0x9C,0xA6,0x7C,0x73,0x60,0x30,0x30,0x30,0x30,0x30,0x30,0x30,0x3F,0x58,0x49,0x1C,0x1A,0x1D,0x1D,0x1C,0x21,0x1D,0x22,0x30,0x48,0x63,0x8A,0xB9,0xD6,0xDF,0xE7,
|
||||
0xDF,0xD6,0xDA,0x8A,0x49,0x21,0x11,0x18,0x30,0x29,0x35,0x34,0x42,0x2B,0x24,0x1F,0x17,0x25,0x39,0x55,0x54,0x6B,0x69,0x7D,0x5E,0x3C,0x22,0x10,0x1C,0x28,0x28,0x29,0x30,0x3F,0x63,0x3F,0x10,0x10,0x67,0xB9,0xC9,0x72,0x48,0x36,0x3F,0x63,0x8A,0xB9,0xD6,0xDF,0xE7,
|
||||
0xD6,0xA4,0xDB,0x98,0x68,0x31,0x1A,0x21,0x30,0x22,0x21,0x22,0x21,0x13,0x7F,0x4E,0x02,0x18,0x98,0xAF,0x19,0x0A,0x12,0x43,0x27,0x30,0x16,0x00,0x0E,0x1D,0x22,0x22,0x28,0x29,0x58,0x67,0x1C,0x1D,0xA3,0xD3,0xB9,0x67,0x29,0x30,0x3F,0x63,0x8A,0xB9,0xD3,0xDF,0xE7,
|
||||
0xC1,0x62,0x30,0x0C,0x0E,0x1A,0x15,0x28,0x29,0x22,0x21,0x1C,0x2F,0x2F,0x51,0x9A,0x11,0x52,0x58,0x48,0x7A,0x02,0x05,0x30,0x1C,0x21,0x22,0x02,0x00,0x16,0x1D,0x21,0x21,0x22,0x36,0x72,0x48,0x18,0x02,0x00,0x02,0x08,0x1A,0x29,0x3F,0x63,0x8A,0xB7,0xD3,0xDF,0xE7,
|
||||
0xE9,0xE0,0xAE,0x1D,0x1A,0x30,0x49,0x48,0x22,0x21,0x1D,0x21,0x29,0x23,0x33,0x56,0x74,0x77,0x2C,0x18,0x83,0x02,0x03,0x30,0x21,0x1A,0x22,0x09,0x00,0x0E,0x1C,0x1C,0x1D,0x1D,0x21,0x59,0x79,0x29,0x22,0x21,0x1C,0x18,0x21,0x30,0x3F,0x62,0x81,0xB7,0xD3,0xDF,0xE7,
|
||||
0xE7,0xDA,0x98,0x3F,0x11,0x15,0x0E,0x16,0x29,0x21,0x1D,0x1D,0x29,0x14,0x93,0xCC,0xB3,0x84,0xA0,0xBE,0x4B,0x02,0x01,0x28,0x1D,0x1D,0x1D,0x18,0x00,0x02,0x18,0x1A,0x1C,0x1A,0x1C,0x29,0x81,0x15,0x30,0x62,0x7B,0x48,0x3E,0x36,0x3F,0x62,0x81,0xB7,0xD3,0xDB,0xE7,
|
||||
0xD7,0xC2,0xE9,0xB0,0x71,0x31,0x15,0x1C,0x28,0x21,0x1D,0x1D,0x28,0x1E,0xA6,0xD8,0xBD,0xA9,0xBC,0xC7,0x6A,0x04,0x02,0x20,0x1A,0x1C,0x1C,0x18,0x00,0x00,0x11,0x18,0x18,0x18,0x18,0x1A,0x68,0x1C,0xD2,0xE9,0xE9,0x80,0x36,0x29,0x3E,0x62,0x80,0xB0,0xD2,0xDB,0xE7,
|
||||
0xC1,0x79,0x72,0x3F,0x31,0x21,0x0E,0x1D,0x28,0x1C,0x1D,0x1A,0x30,0x0F,0x6C,0xCD,0xD5,0xBA,0x8D,0xA8,0x57,0x0E,0x2A,0x10,0x21,0x1C,0x48,0x02,0x00,0x00,0x0E,0x16,0x16,0x16,0x16,0x18,0x31,0x18,0x18,0x15,0x11,0x10,0x1C,0x29,0x3E,0x59,0x80,0xB0,0xD2,0xDB,0xE7,
|
||||
0xDA,0xD2,0x72,0x0E,0x0C,0x1D,0x30,0x37,0x22,0x1C,0x1D,0x1C,0x30,0x06,0xA2,0x92,0x9B,0x8F,0x87,0xBF,0xB1,0x0D,0x1B,0x09,0x1A,0x37,0x1A,0x02,0x00,0x00,0x10,0x18,0x16,0x16,0x16,0x18,0x11,0x21,0x18,0x11,0x11,0x11,0x1D,0x29,0x3E,0x59,0x80,0xB0,0xD2,0xDB,0xE7,
|
||||
0xE9,0xE0,0x99,0x37,0x1A,0x22,0x21,0x21,0x22,0x1D,0x1C,0x29,0x1D,0x16,0xAE,0xAC,0xAB,0xAD,0xD1,0xDD,0xD6,0x46,0x02,0x04,0x0B,0x0E,0x00,0x00,0x00,0x00,0x1D,0x1C,0x18,0x18,0x16,0x18,0x10,0x1A,0x1D,0x30,0x30,0x30,0x29,0x29,0x3E,0x59,0x80,0xB0,0xD2,0xDB,0xE7,
|
||||
0xDF,0xB9,0x98,0x62,0x22,0x1A,0x0C,0x16,0x22,0x1C,0x21,0x26,0x09,0x5B,0x8B,0xC5,0xCA,0xDC,0xE2,0xC0,0x72,0x7B,0x07,0x07,0x03,0x00,0x00,0x00,0x00,0x0C,0x18,0x1D,0x1C,0x18,0x18,0x18,0x10,0x3F,0xD6,0xE9,0xD3,0x59,0x29,0x29,0x3E,0x59,0x80,0xB0,0xD2,0xDB,0xE7,
|
||||
0xCB,0xB0,0xE9,0xAE,0x72,0x30,0x11,0x1D,0x22,0x22,0x11,0x09,0x21,0xCB,0xCB,0xE0,0xE7,0xE9,0xDE,0x99,0x79,0xB7,0x1C,0x03,0x01,0x00,0x00,0x00,0x02,0x1A,0x15,0x15,0x21,0x1C,0x18,0x18,0x0E,0x31,0x67,0x62,0x29,0x1A,0x28,0x29,0x3E,0x62,0x81,0xB0,0xD3,0xDB,0xE7,
|
||||
0xB9,0x8A,0x4F,0x11,0x10,0x18,0x0E,0x21,0x29,0x11,0x18,0x10,0x3F,0xCB,0xD2,0xD7,0xDC,0xE9,0xE6,0xC9,0xB6,0xB8,0x5A,0x01,0x00,0x00,0x00,0x00,0x08,0x29,0x29,0x16,0x15,0x1A,0x1A,0x15,0x02,0x0E,0x08,0x00,0x08,0x09,0x1D,0x29,0x3E,0x62,0x81,0xB7,0xD3,0xDB,0xE7,
|
||||
0xE9,0xE0,0x98,0x15,0x11,0x1D,0x3E,0x37,0x02,0x0E,0x1C,0x02,0x8A,0xA3,0x71,0xB7,0xE1,0xE9,0xE6,0xDC,0xD9,0xD4,0xC4,0x28,0x02,0x00,0x00,0x09,0x02,0x00,0x00,0x02,0x0C,0x16,0x30,0x21,0x0E,0x21,0x28,0x21,0x1D,0x1A,0x22,0x29,0x3F,0x62,0x81,0xB7,0xD3,0xDF,0xE7,
|
||||
0xE9,0xC1,0x67,0x28,0x0E,0x11,0x10,0x16,0x02,0x00,0x08,0x00,0x48,0x8C,0x8C,0xC3,0xDF,0xE0,0xD3,0x7B,0x82,0xCB,0xC9,0x71,0x01,0x00,0x09,0x0C,0x00,0x00,0x00,0x00,0x00,0x00,0x08,0x1C,0x18,0x28,0x98,0xDF,0xC1,0x58,0x3E,0x29,0x3F,0x62,0x81,0xB7,0xD3,0xDF,0xE7,
|
||||
0xD6,0xB9,0xD7,0x8C,0x59,0x31,0x10,0x1A,0x0C,0x00,0x00,0x00,0x02,0x18,0x1C,0x21,0x31,0x37,0x31,0x1A,0x1D,0x37,0x3D,0x28,0x03,0x00,0x0C,0x02,0x00,0x02,0x09,0x0E,0x0C,0x10,0x18,0x18,0x15,0x4F,0xC1,0xC9,0x71,0x30,0x21,0x29,0x3F,0x62,0x8A,0xB7,0xD3,0xDF,0xE7,
|
||||
0xC2,0x8A,0xAE,0x63,0x49,0x28,0x09,0x1C,0x22,0x16,0x08,0x00,0x00,0x0C,0x18,0x11,0x10,0x10,0x0C,0x09,0x0C,0x0E,0x0E,0x10,0x11,0x15,0x1A,0x22,0x1C,0x1A,0x1D,0x1A,0x11,0x16,0x15,0x16,0x10,0x0C,0x00,0x00,0x00,0x00,0x1A,0x29,0x3F,0x62,0x81,0xB7,0xD3,0xDF,0xE7,
|
||||
0xDB,0xDA,0x72,0x08,0x09,0x16,0x22,0x31,0x21,0x18,0x1A,0x16,0x08,0x09,0x15,0x18,0x11,0x16,0x16,0x15,0x11,0x11,0x16,0x16,0x15,0x15,0x11,0x11,0x11,0x15,0x15,0x15,0x11,0x11,0x15,0x18,0x15,0x1C,0x18,0x16,0x1D,0x18,0x21,0x29,0x3E,0x62,0x81,0xB7,0xD3,0xDF,0xE7,
|
||||
0xE9,0xDF,0x8A,0x1D,0x15,0x1A,0x1C,0x21,0x22,0x1C,0x16,0x16,0x18,0x18,0x18,0x16,0x16,0x18,0x15,0x15,0x15,0x16,0x16,0x15,0x15,0x15,0x16,0x15,0x11,0x11,0x15,0x11,0x11,0x16,0x16,0x1A,0x16,0x16,0x58,0xC1,0xAE,0x59,0x3E,0x30,0x3E,0x62,0x81,0xB7,0xD3,0xDF,0xE7,
|
||||
0xE7,0x98,0x50,0x36,0x16,0x18,0x09,0x18,0x28,0x1D,0x1A,0x16,0x16,0x16,0x16,0x16,0x16,0x16,0x16,0x15,0x16,0x16,0x15,0x16,0x15,0x15,0x11,0x11,0x11,0x15,0x15,0x15,0x11,0x11,0x11,0x1A,0x15,0x31,0xD2,0xCB,0x59,0x29,0x22,0x29,0x3E,0x59,0x80,0xB0,0xD3,0xDB,0xE7,
|
||||
0xCB,0xB0,0xDB,0xA4,0x68,0x31,0x10,0x1C,0x28,0x21,0x1C,0x1A,0x16,0x18,0x18,0x1C,0x16,0x18,0x15,0x16,0x18,0x11,0x11,0x15,0x15,0x11,0x11,0x11,0x15,0x11,0x10,0x11,0x15,0x15,0x18,0x1C,0x15,0x18,0x15,0x00,0x02,0x09,0x08,0x21,0x3E,0x59,0x80,0xB0,0xD2,0xDB,0xE7,
|
||||
0xC9,0xC1,0x80,0x36,0x21,0x1A,0x10,0x29,0x16,0x11,0x1A,0x0E,0x0C,0x15,0x11,0x1A,0x09,0x0E,0x11,0x16,0x10,0x09,0x0E,0x0E,0x16,0x08,0x09,0x0C,0x11,0x0E,0x08,0x0E,0x0C,0x16,0x08,0x0E,0x18,0x18,0x0C,0x08,0x15,0x16,0x1C,0x28,0x37,0x59,0x80,0xB0,0xD2,0xDB,0xE7,
|
||||
0xE9,0xE0,0x81,0x0C,0x09,0x1A,0x29,0x08,0x0E,0x10,0x1C,0x0E,0x0C,0x11,0x16,0x1C,0x02,0x10,0x0E,0x1C,0x10,0x09,0x0E,0x10,0x1A,0x02,0x0E,0x0C,0x18,0x0E,0x09,0x0E,0x10,0x18,0x08,0x10,0x0C,0x18,0x18,0x16,0x10,0x16,0x21,0x29,0x37,0x58,0x7B,0xAE,0xD2,0xDB,0xE7,
|
||||
0xE9,0xE0,0x99,0x21,0x1D,0x21,0x1C,0x50,0x72,0x1A,0x1D,0x11,0x71,0x72,0x1A,0x1C,0x16,0x99,0x30,0x1C,0x11,0x59,0x80,0x18,0x1A,0x15,0xA4,0x37,0x18,0x10,0x58,0xAE,0x15,0x18,0x15,0xCB,0x49,0x18,0x11,0x10,0x11,0x16,0x21,0x29,0x3E,0x59,0x80,0xAE,0xD2,0xDB,0xE7,
|
||||
0xE9,0xE0,0xA3,0x1A,0x21,0x22,0x21,0xB9,0xCB,0x15,0x22,0x15,0xCB,0xC9,0x11,0x1D,0x22,0xE9,0x50,0x18,0x11,0x98,0xE7,0x10,0x1C,0x15,0xE9,0x68,0x16,0x10,0x71,0xE9,0x16,0x1A,0x10,0xE7,0x67,0x16,0x15,0x15,0x11,0x18,0x22,0x29,0x3E,0x62,0x80,0xB0,0xD2,0xDB,0xE7,
|
||||
0xE9,0xE7,0xA3,0x1D,0x1C,0x28,0x30,0xDF,0xCB,0x1D,0x29,0x28,0xE0,0xD2,0x1A,0x22,0x50,0xE9,0x62,0x21,0x21,0xB0,0xE9,0x16,0x1C,0x29,0xE0,0x79,0x1C,0x1C,0x71,0xDB,0x21,0x18,0x21,0xB9,0x79,0x1A,0x15,0x11,0x10,0x18,0x22,0x30,0x48,0x63,0x8A,0xB9,0xD3,0xDF,0xE7,
|
||||
0xE9,0xE7,0xD6,0x48,0x1C,0x31,0x18,0x7B,0x59,0x0C,0x16,0x18,0x62,0x50,0x0C,0x16,0x21,0x72,0x28,0x10,0x11,0x48,0x71,0x09,0x10,0x16,0x71,0x36,0x0E,0x0E,0x30,0x50,0x11,0x0E,0x0C,0x49,0x30,0x10,0x0C,0x08,0x10,0x1D,0x28,0x36,0x49,0x68,0x98,0xC2,0xD7,0xDF,0xE7,
|
||||
0xE9,0xE9,0xE0,0xDA,0xC9,0xAE,0x7B,0x49,0x28,0x10,0x22,0x22,0x28,0x22,0x15,0x21,0x1D,0x30,0x1C,0x1D,0x1C,0x22,0x22,0x18,0x1D,0x16,0x31,0x21,0x21,0x15,0x29,0x31,0x1D,0x1A,0x1A,0x29,0x1C,0x21,0x21,0x1D,0x22,0x28,0x30,0x3E,0x58,0x79,0xA4,0xCB,0xDA,0xE0,0xE9,
|
||||
0xE9,0xE9,0xE7,0xDF,0xD3,0xB9,0x98,0x59,0x36,0x22,0x31,0x3F,0x49,0x1D,0x21,0x28,0x67,0x1D,0x1C,0x22,0x29,0x4F,0x1A,0x1D,0x28,0x58,0x1C,0x1A,0x22,0x29,0x4F,0x1A,0x21,0x28,0x59,0x1C,0x22,0x28,0x28,0x28,0x29,0x31,0x37,0x4F,0x67,0x8A,0xB7,0xD3,0xDB,0xE7,0xE9,
|
||||
0xE9,0xE9,0xE7,0xE0,0xD7,0xC9,0xAE,0x81,0x67,0x58,0x48,0x3E,0x37,0x36,0x36,0x36,0x36,0x36,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x31,0x36,0x36,0x36,0x3E,0x48,0x50,0x63,0x7B,0xA3,0xC2,0xD7,0xDF,0xE7,0xE9,
|
||||
0xE9,0xE9,0xE9,0xE7,0xDB,0xD3,0xC1,0xA4,0x81,0x72,0x63,0x59,0x50,0x50,0x4F,0x4F,0x4F,0x4F,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x49,0x4F,0x50,0x58,0x63,0x71,0x80,0x99,0xB9,0xD2,0xDB,0xE0,0xE9,0xE9,
|
||||
0xE9,0xE9,0xE9,0xE7,0xE0,0xDA,0xD3,0xC2,0xB0,0x99,0x8A,0x7B,0x79,0x72,0x71,0x71,0x71,0x71,0x68,0x68,0x68,0x68,0x68,0x68,0x68,0x68,0x67,0x67,0x67,0x67,0x67,0x67,0x68,0x68,0x68,0x68,0x68,0x71,0x71,0x72,0x7B,0x8A,0x99,0xAE,0xC1,0xD2,0xDA,0xDF,0xE7,0xE9,0xE9,
|
||||
0xE9,0xE9,0xE9,0xE9,0xE7,0xE0,0xDB,0xD6,0xD2,0xC2,0xB7,0xAE,0xA3,0x99,0x99,0x99,0x99,0x98,0x98,0x98,0x98,0x98,0x98,0x98,0x98,0x8C,0x8C,0x8C,0x8C,0x8C,0x8C,0x8C,0x8C,0x98,0x98,0x98,0x98,0x98,0x99,0xA3,0xA4,0xB7,0xC2,0xCB,0xD6,0xDA,0xDF,0xE7,0xE9,0xE9,0xE9,
|
||||
0xE9,0xE9,0xE9,0xE9,0xE9,0xE7,0xE0,0xDF,0xDA,0xD7,0xD3,0xCB,0xC9,0xC2,0xC2,0xC2,0xC2,0xC1,0xC1,0xC1,0xC1,0xC1,0xC1,0xC1,0xC1,0xC1,0xB9,0xB9,0xB9,0xB9,0xB9,0xB9,0xC1,0xC1,0xC1,0xC1,0xC1,0xC1,0xC2,0xC2,0xCB,0xD3,0xD7,0xDA,0xDF,0xE0,0xE7,0xE9,0xE9,0xE9,0xE9,
|
||||
0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE7,0xE0,0xDF,0xDB,0xDA,0xDA,0xD7,0xD7,0xD7,0xD7,0xD6,0xD6,0xD6,0xD6,0xD6,0xD6,0xD6,0xD6,0xD6,0xD6,0xD6,0xD6,0xD6,0xD6,0xD6,0xD6,0xD6,0xD6,0xD6,0xD6,0xD7,0xD7,0xD7,0xDA,0xDB,0xDF,0xE0,0xE7,0xE7,0xE9,0xE9,0xE9,0xE9,0xE9,
|
||||
0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE7,0xE7,0xE0,0xE0,0xE0,0xE0,0xE0,0xDF,0xDF,0xDF,0xDF,0xDF,0xDF,0xDF,0xDF,0xDF,0xDF,0xDF,0xDF,0xDF,0xDF,0xDF,0xDF,0xDF,0xDF,0xDF,0xDF,0xDF,0xDF,0xDF,0xE0,0xE0,0xE7,0xE7,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,
|
||||
0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE7,0xE7,0xE7,0xE7,0xE7,0xE7,0xE7,0xE7,0xE7,0xE7,0xE7,0xE7,0xE7,0xE7,0xE7,0xE7,0xE7,0xE7,0xE7,0xE7,0xE7,0xE7,0xE7,0xE7,0xE7,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,0xE9,
|
||||
};
|
@@ -1,29 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef SOUTHBRIDGE_AMD_CS5530_CHIP_H
|
||||
#define SOUTHBRIDGE_AMD_CS5530_CHIP_H
|
||||
|
||||
struct southbridge_amd_cs5530_config {
|
||||
int ide0_enable:1;
|
||||
int ide1_enable:1;
|
||||
};
|
||||
|
||||
#endif /* SOUTHBRIDGE_AMD_CS5530_CHIP_H */
|
@@ -1,59 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
/* Datasheet:
|
||||
* - Name: Geode CS5530A I/O Companion Multi-Function South Bridge
|
||||
* - URL: http://www.national.com/pf/CS/CS5530A.html
|
||||
* - PDF: http://www.national.com/ds.cgi/CS/CS5530A.pdf
|
||||
* - Revision: 1.1 (May 2001)
|
||||
*/
|
||||
|
||||
/* Datasheet:
|
||||
* - Name: AMD Geode CS5530A Companion Device Data Book
|
||||
* - URL: http://www.amd.com/us-en/ConnectivitySolutions/ProductInformation/0,,50_2330_9863_9919,00.html
|
||||
* - PDF: http://www.amd.com/files/connectivitysolutions/geode/5530a_db_v11.pdf
|
||||
* - Date: October 2003
|
||||
* - Publication ID: May 2001, Revision 1.1
|
||||
*/
|
||||
|
||||
/* Datasheet:
|
||||
* - Name: AMD Geode Solutions
|
||||
* Integrated Processors, Companion Devices, and System Platforms
|
||||
* (Geode CS5530 I/O Companion Multi-Function South Bridge)
|
||||
* - URL: http://www.amd.com/us-en/ConnectivitySolutions/ProductInformation/0,,50_2330_9863_9919,00.html
|
||||
* - PDF: http://www.amd.com/files/connectivitysolutions/geode/5530_db_v41.pdf
|
||||
* - Date: September 2004
|
||||
*/
|
||||
|
||||
/* Note: The CS3350 / CS3350A are mostly identical. This code handles both. */
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include "cs5530.h"
|
||||
|
||||
void cs5530_enable(device_t dev)
|
||||
{
|
||||
}
|
||||
|
||||
struct chip_operations southbridge_amd_cs5530_ops = {
|
||||
CHIP_NAME("AMD Geode CS5530/CS5530A I/O Companion Southbridge")
|
||||
.enable_dev = cs5530_enable,
|
||||
};
|
@@ -1,46 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#ifndef SOUTHBRIDGE_AMD_CS5530_CS5530_H
|
||||
#define SOUTHBRIDGE_AMD_CS5530_CS5530_H
|
||||
|
||||
#if !defined(__PRE_RAM__)
|
||||
#include "chip.h"
|
||||
void cs5530_enable(device_t dev);
|
||||
#endif
|
||||
|
||||
#define DECODE_CONTROL_REG2 0x5b /* F0 index 0x5b */
|
||||
#define ROM_AT_LOGIC_CONTROL_REG 0x52 /* F0 index 0x52 */
|
||||
|
||||
#define LOWER_ROM_ADDRESS_RANGE (1 << 0)
|
||||
#define ROM_WRITE_ENABLE (1 << 1)
|
||||
#define UPPER_ROM_ADDRESS_RANGE (1 << 2)
|
||||
#define BIOS_ROM_POSITIVE_DECODE (1 << 5)
|
||||
|
||||
/* Selects PCI positive decoding for accesses to the configured ROM space. */
|
||||
#define BIOS_ROM_POSITIVE_DECODE (1 << 5)
|
||||
|
||||
/* Primary IDE Controller Positive Decode (i.e., enable it). */
|
||||
#define PRIMARY_IDE_ENABLE (1 << 3)
|
||||
|
||||
/* Secondary IDE Controller Positive Decode (i.e., enable it). */
|
||||
#define SECONDARY_IDE_ENABLE (1 << 4)
|
||||
|
||||
#endif /* SOUTHBRIDGE_AMD_CS5530_CS5530_H */
|
@@ -1,47 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2009 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <stdint.h>
|
||||
#include "cs5530.h"
|
||||
|
||||
static void cs5530_enable_rom(void)
|
||||
{
|
||||
uint8_t reg8;
|
||||
|
||||
/* So far all CS5530(A) ISA bridges we've seen are at 00:12.0. */
|
||||
device_t dev = PCI_DEV(0, 0x12, 0);
|
||||
|
||||
/*
|
||||
* Decode 0x000E0000-0x000FFFFF (128 KB), not just 64 KB, and
|
||||
* decode 0xFF000000-0xFFFFFFFF (16 MB), not just 256 KB.
|
||||
*
|
||||
* Make the ROM write-protected.
|
||||
*/
|
||||
reg8 = pci_read_config8(dev, ROM_AT_LOGIC_CONTROL_REG);
|
||||
reg8 |= LOWER_ROM_ADDRESS_RANGE;
|
||||
reg8 |= UPPER_ROM_ADDRESS_RANGE;
|
||||
reg8 &= ~ROM_WRITE_ENABLE;
|
||||
pci_write_config8(dev, ROM_AT_LOGIC_CONTROL_REG, reg8);
|
||||
|
||||
/* Set positive decode on ROM. */
|
||||
reg8 = pci_read_config8(dev, DECODE_CONTROL_REG2);
|
||||
reg8 |= BIOS_ROM_POSITIVE_DECODE;
|
||||
pci_write_config8(dev, DECODE_CONTROL_REG2, reg8);
|
||||
}
|
@@ -1,78 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include "cs5530.h"
|
||||
|
||||
/**
|
||||
* Initialize the IDE controller.
|
||||
*
|
||||
* Depending on the configuration variables 'ide0_enable' and 'ide1_enable'
|
||||
* enable or disable the primary and secondary IDE interface, respectively.
|
||||
*
|
||||
* @param dev The device to use.
|
||||
*/
|
||||
static void ide_init(struct device *dev)
|
||||
{
|
||||
uint8_t reg8;
|
||||
struct southbridge_amd_cs5530_config *conf = dev->chip_info;
|
||||
|
||||
reg8 = pci_read_config8(dev, DECODE_CONTROL_REG2);
|
||||
|
||||
/* Enable/disable the primary IDE interface. */
|
||||
if (conf->ide0_enable) {
|
||||
reg8 |= PRIMARY_IDE_ENABLE;
|
||||
} else {
|
||||
reg8 &= ~(PRIMARY_IDE_ENABLE);
|
||||
}
|
||||
|
||||
/* Enable/disable the secondary IDE interface. */
|
||||
if (conf->ide1_enable) {
|
||||
reg8 |= SECONDARY_IDE_ENABLE;
|
||||
} else {
|
||||
reg8 &= ~(SECONDARY_IDE_ENABLE);
|
||||
}
|
||||
|
||||
pci_write_config8(dev, DECODE_CONTROL_REG2, reg8);
|
||||
|
||||
printk(BIOS_INFO, "%s IDE interface %s\n", "Primary",
|
||||
conf->ide0_enable ? "enabled" : "disabled");
|
||||
printk(BIOS_INFO, "%s IDE interface %s\n", "Secondary",
|
||||
conf->ide1_enable ? "enabled" : "disabled");
|
||||
}
|
||||
|
||||
static struct device_operations ide_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = ide_init,
|
||||
.enable = 0,
|
||||
.scan_bus = scan_static_bus,
|
||||
.ops_pci = 0,
|
||||
};
|
||||
|
||||
static const struct pci_driver ide_driver __pci_driver = {
|
||||
.ops = &ide_ops,
|
||||
.vendor = PCI_VENDOR_ID_CYRIX,
|
||||
.device = PCI_DEVICE_ID_CYRIX_5530_IDE,
|
||||
};
|
@@ -1,64 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Uwe Hermann <uwe@hermann-uwe.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <console/console.h>
|
||||
#include <arch/io.h>
|
||||
#include <arch/ioapic.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include "cs5530.h"
|
||||
|
||||
static void cs5530_read_resources(device_t dev)
|
||||
{
|
||||
struct resource* res;
|
||||
|
||||
pci_dev_read_resources(dev);
|
||||
|
||||
res = new_resource(dev, 1);
|
||||
res->base = 0x0UL;
|
||||
res->size = 0x1000UL;
|
||||
res->limit = 0xffffUL;
|
||||
res->flags = IORESOURCE_IO | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
||||
|
||||
res = new_resource(dev, 3); /* IOAPIC */
|
||||
res->base = IO_APIC_ADDR;
|
||||
res->size = 0x00001000;
|
||||
res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
|
||||
}
|
||||
|
||||
static void isa_init(struct device *dev)
|
||||
{
|
||||
}
|
||||
|
||||
static struct device_operations isa_ops = {
|
||||
.read_resources = cs5530_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = isa_init,
|
||||
.enable = 0,
|
||||
.scan_bus = scan_static_bus,
|
||||
};
|
||||
|
||||
static const struct pci_driver isa_driver __pci_driver = {
|
||||
.ops = &isa_ops,
|
||||
.vendor = PCI_VENDOR_ID_CYRIX,
|
||||
.device = PCI_DEVICE_ID_CYRIX_5530_LEGACY,
|
||||
};
|
@@ -1,39 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Nikolay Petukhov <nikolay.petukhov@gmail.com>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; either version 2 of the License, or
|
||||
* (at your option) any later version.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
|
||||
*/
|
||||
|
||||
#include <arch/pirq_routing.h>
|
||||
#include <console/console.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ids.h>
|
||||
|
||||
#if (CONFIG_PIRQ_ROUTE==1 && CONFIG_GENERATE_PIRQ_TABLE==1)
|
||||
void pirq_assign_irqs(const unsigned char pIntAtoD[4])
|
||||
{
|
||||
device_t pdev;
|
||||
|
||||
pdev = dev_find_device(PCI_VENDOR_ID_CYRIX,
|
||||
PCI_DEVICE_ID_CYRIX_5530_LEGACY, 0);
|
||||
|
||||
if (pdev) {
|
||||
pci_write_config8(pdev, 0x5c, (pIntAtoD[1] << 4 | pIntAtoD[0]));
|
||||
pci_write_config8(pdev, 0x5d, (pIntAtoD[3] << 4 | pIntAtoD[2]));
|
||||
}
|
||||
}
|
||||
#endif
|
@@ -1,495 +0,0 @@
|
||||
/*
|
||||
* This file is part of the coreboot project.
|
||||
*
|
||||
* Copyright (C) 2007 Juergen Beisert <juergen@kreuzholzen.de>
|
||||
*
|
||||
* This program is free software; you can redistribute it and/or modify
|
||||
* it under the terms of the GNU General Public License as published by
|
||||
* the Free Software Foundation; version 2 of the License.
|
||||
*
|
||||
* This program is distributed in the hope that it will be useful,
|
||||
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||
* GNU General Public License for more details.
|
||||
*
|
||||
* You should have received a copy of the GNU General Public License
|
||||
* along with this program; if not, write to the Free Software
|
||||
* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA, 02110-1301 USA
|
||||
*/
|
||||
|
||||
/**
|
||||
* @brief Activate the VGA feature in a Geode GX1 based system with one
|
||||
* of five possible VESA modes: VGA, SVGA, XGA, 4:3 SXGA and 5:4 SXGA.
|
||||
* Also it is prepared to display a splash screen.
|
||||
*
|
||||
* In a Geode GX1 environment the companion CS5530 is the VGA
|
||||
* interface only. It contains a PLL for pixel clock generation,
|
||||
* DACs to generate the analogue RGB signals, drivers for HSYNC
|
||||
* and VSYNC and drivers for a digital flatpanel.
|
||||
* The graphic feature itself (framebuffer, acceleration unit)
|
||||
* is not part of this device. It is part of the CPU device.
|
||||
* But both depend on each other, we cannot divide them into
|
||||
* different drivers. So this driver is not only a CS5530 driver,
|
||||
* it is also a Geode GX1 chipset graphic driver.
|
||||
*/
|
||||
#include <arch/io.h>
|
||||
#include <device/device.h>
|
||||
#include <device/pci.h>
|
||||
#include <device/pci_ops.h>
|
||||
#include <device/pci_ids.h>
|
||||
#include <console/console.h>
|
||||
#include <cpu/amd/gx1def.h>
|
||||
#include <delay.h>
|
||||
|
||||
#if CONFIG_GX1_VIDEO
|
||||
/*
|
||||
* Some register descriptions that are no listed in cpu/amd/gx1def.h
|
||||
*/
|
||||
#define CS5530_DOT_CLK_CONFIG 0x0024
|
||||
#define CS5530_DISPLAY_CONFIG 0x0004
|
||||
|
||||
#define DC_FB_ST_OFFSET 0x8310 /* framebuffer start offset */
|
||||
#define DC_CB_ST_OFFSET 0x8314 /* compression start offset */
|
||||
#define DC_CURS_ST_OFFSET 0x8318 /* cursor start offset */
|
||||
#define DC_VID_ST_OFFSET 0x8320 /* video start offset */
|
||||
#define DC_LINE_DELTA 0x8324 /* fb and cb skip counts */
|
||||
#define DC_BUF_SIZE 0x8328 /* fb and cb line size */
|
||||
#define DC_H_TIMING_1 0x8330 /* horizontal timing... */
|
||||
#define DC_H_TIMING_2 0x8334
|
||||
#define DC_H_TIMING_3 0x8338
|
||||
#define DC_FP_H_TIMING 0x833C
|
||||
#define DC_V_TIMING_1 0x8340 /* vertical timing... */
|
||||
#define DC_V_TIMING_2 0x8344
|
||||
#define DC_V_TIMING_3 0x8348
|
||||
#define DC_FP_V_TIMING 0x834C
|
||||
#define DC_TIMING_CFG 0x8308
|
||||
#define DC_OUTPUT_CFG 0x830C
|
||||
|
||||
/**
|
||||
* what colour depth should be used as default (in bpp)
|
||||
* Note: Currently no other value than 16 is supported
|
||||
*/
|
||||
#define COLOUR_DEPTH 16
|
||||
|
||||
/**
|
||||
* Support for a few basic video modes
|
||||
* Note: all modes only for CRT. The flatpanel feature is
|
||||
* not supported here (due to the lack of hardware to test)
|
||||
*/
|
||||
struct video_mode {
|
||||
int pixel_clock; /*<< pixel clock in Hz */
|
||||
unsigned long pll_value; /*<< pll register value for this clock */
|
||||
|
||||
int visible_pixel; /*<< visible pixels in one line */
|
||||
int hsync_start; /*<< start of hsync behind visible pixels */
|
||||
int hsync_end; /*<< end of hsync behind its start */
|
||||
int line_length; /*<< whole line length */
|
||||
|
||||
int visible_lines; /*<< visible lines on screen */
|
||||
int vsync_start; /*<< vsync start behind last visible line */
|
||||
int vsync_end; /*<< end of vsync behind its start */
|
||||
int picture_length; /*<< whole screen length */
|
||||
|
||||
int sync_pol; /*<< 0: low, 1: high, bit 0 hsync, bit 1 vsync */
|
||||
};
|
||||
|
||||
/*
|
||||
* values for .sync_pol in struct video_mode
|
||||
*/
|
||||
#define HSYNC_HIGH_POL 0
|
||||
#define HSYNC_LOW_POL 1
|
||||
#define VSYNC_HIGH_POL 0
|
||||
#define VSYNC_LOW_POL 2
|
||||
|
||||
/**
|
||||
* 640x480 @ 72Hz hsync: 37.9kHz
|
||||
* VESA standard mode for classic 4:3 monitors
|
||||
* Copied from X11:
|
||||
* ModeLine "640x480" 31.5 640 664 704 832 480 489 491 520 -hsync -vsync
|
||||
*/
|
||||
static const struct video_mode mode_640x480 = {
|
||||
.pixel_clock = 31500000,
|
||||
.pll_value = 0x33915801,
|
||||
|
||||
.visible_pixel = 640,
|
||||
.hsync_start = 664,
|
||||
.hsync_end = 704, /* 1.27 us sync length */
|
||||
.line_length = 832, /* 26.39us */
|
||||
|
||||
.visible_lines = 480,
|
||||
.vsync_start = 489,
|
||||
.vsync_end = 491,
|
||||
.picture_length = 520, /* 13.89ms */
|
||||
|
||||
.sync_pol = HSYNC_LOW_POL | VSYNC_LOW_POL,
|
||||
};
|
||||
|
||||
/**
|
||||
* 800x600 @ 72Hz hsync: 48.1kHz
|
||||
* VESA standard mode for classic 4:3 monitors
|
||||
* Copied from X11:
|
||||
* ModeLine "800x600" 50.0 800 856 976 1040 600 637 643 666 +hsync +vsync
|
||||
*/
|
||||
static const struct video_mode mode_800x600 = {
|
||||
.pixel_clock = 50000000,
|
||||
.pll_value = 0x23088801,
|
||||
|
||||
.visible_pixel = 800,
|
||||
.hsync_start = 856,
|
||||
.hsync_end = 976,
|
||||
.line_length = 1040, /* 20.8us */
|
||||
|
||||
.visible_lines = 600,
|
||||
.vsync_start = 637,
|
||||
.vsync_end = 643,
|
||||
.picture_length = 666, /* 13.89ms */
|
||||
|
||||
.sync_pol = HSYNC_HIGH_POL | VSYNC_HIGH_POL,
|
||||
};
|
||||
|
||||
/**
|
||||
* 1024x768 @ 70Hz (VESA) hsync: 56.5kHz
|
||||
* Standard mode for classic 4:3 monitors
|
||||
* Copied from X11:
|
||||
* ModeLine "1024x768" 75.0 1024 1048 1184 1328 768 771 777 806 -hsync -vsync
|
||||
*/
|
||||
static const struct video_mode mode_1024x768 = {
|
||||
.pixel_clock = 75000000,
|
||||
.pll_value = 0x37E22801,
|
||||
|
||||
.visible_pixel = 1024,
|
||||
.hsync_start = 1048,
|
||||
.hsync_end = 1184,
|
||||
.line_length = 1328, /* 17.7us */
|
||||
|
||||
.visible_lines = 768,
|
||||
.vsync_start = 771,
|
||||
.vsync_end = 777,
|
||||
.picture_length = 806, /* 14.3us */
|
||||
|
||||
.sync_pol = HSYNC_LOW_POL | VSYNC_LOW_POL,
|
||||
};
|
||||
|
||||
/**
|
||||
* 1280x960 @ 60Hz (VESA) hsync: 60.0kHz
|
||||
* Mode for classic 4:3 monitors
|
||||
* Copied from X11:
|
||||
* ModeLine "1280x960" 108.0 1280 1376 1488 1800 960 961 964 1000 +hsync +vsync
|
||||
*/
|
||||
static const struct video_mode mode_1280x960 = {
|
||||
.pixel_clock = 108000000,
|
||||
.pll_value = 0x2710C805,
|
||||
|
||||
.visible_pixel = 1280,
|
||||
.hsync_start = 1376,
|
||||
.hsync_end = 1488,
|
||||
.line_length = 1800, /* 16.67us */
|
||||
|
||||
.visible_lines = 960,
|
||||
.vsync_start = 961,
|
||||
.vsync_end = 964,
|
||||
.picture_length = 1000, /* 16.67ms */
|
||||
|
||||
.sync_pol = HSYNC_HIGH_POL | VSYNC_HIGH_POL,
|
||||
};
|
||||
|
||||
/**
|
||||
* 1280x1024 @ 60Hz (VESA) hsync: 64.0kHz
|
||||
* Mode for modern 5:4 flat screens
|
||||
* Copied from X11:
|
||||
* ModeLine "1280x1024" 108.0 1280 1328 1440 1688 1024 1025 1028 1066 +hsync +vsync
|
||||
*/
|
||||
static const struct video_mode mode_1280x1024 = {
|
||||
.pixel_clock = 108000000,
|
||||
.pll_value = 0x2710C805,
|
||||
|
||||
.visible_pixel = 1280,
|
||||
.hsync_start = 1328,
|
||||
.hsync_end = 1440,
|
||||
.line_length = 1688, /* 15.6us */
|
||||
|
||||
.visible_lines = 1024,
|
||||
.vsync_start = 1025,
|
||||
.vsync_end = 1028,
|
||||
.picture_length = 1066,
|
||||
|
||||
.sync_pol = HSYNC_HIGH_POL | VSYNC_HIGH_POL,
|
||||
};
|
||||
|
||||
/**
|
||||
* List of supported common modes
|
||||
*/
|
||||
static const struct video_mode *modes[] = {
|
||||
&mode_640x480, /* CONFIG_GX1_VIDEOMODE = 0 */
|
||||
&mode_800x600, /* CONFIG_GX1_VIDEOMODE = 1 */
|
||||
&mode_1024x768, /* CONFIG_GX1_VIDEOMODE = 2 */
|
||||
&mode_1280x960, /* CONFIG_GX1_VIDEOMODE = 3 */
|
||||
&mode_1280x1024 /* CONFIG_GX1_VIDEOMODE = 4 */
|
||||
};
|
||||
|
||||
/* make a sanity check at buildtime */
|
||||
#if CONFIG_GX1_VIDEOMODE > 4
|
||||
# error Requested video mode is unknown!
|
||||
#endif
|
||||
|
||||
/**
|
||||
* Setup the pixel PLL in the companion chip
|
||||
* @param[in] base register's base address
|
||||
* @param[in] pll_val pll register value to be set
|
||||
*
|
||||
* The PLL to program here is located in the CS5530
|
||||
*/
|
||||
static void cs5530_set_clock_frequency(u32 io_base, unsigned long pll_val)
|
||||
{
|
||||
unsigned long reg;
|
||||
|
||||
/* disable the PLL first, reset and power it down */
|
||||
reg = read32(io_base+CS5530_DOT_CLK_CONFIG) & ~0x20;
|
||||
reg |= 0x80000100;
|
||||
write32(io_base+CS5530_DOT_CLK_CONFIG, reg);
|
||||
|
||||
/* write the new PLL setting */
|
||||
reg |= (pll_val & ~0x80000920);
|
||||
write32(io_base+CS5530_DOT_CLK_CONFIG, reg);
|
||||
|
||||
mdelay(1); /* wait for control voltage to be 0V */
|
||||
|
||||
/* enable the PLL */
|
||||
reg |= 0x00000800;
|
||||
write32(io_base+CS5530_DOT_CLK_CONFIG, reg);
|
||||
|
||||
/* clear reset */
|
||||
reg &= ~0x80000000;
|
||||
write32(io_base+CS5530_DOT_CLK_CONFIG, reg);
|
||||
|
||||
/* clear bypass */
|
||||
reg &= ~0x00000100;
|
||||
write32(io_base+CS5530_DOT_CLK_CONFIG, reg);
|
||||
}
|
||||
|
||||
/**
|
||||
* Setup memory layout
|
||||
* @param[in] gx_base GX register area
|
||||
* @param[in] mode Data about the video mode to setup
|
||||
*
|
||||
* Memory layout must be setup in Geode GX1's chipset.
|
||||
* Note: This routine assumes unlocked DC registers.
|
||||
* Note: Using compressed buffer is not supported yet!
|
||||
* (makes more sense later, but not while booting)
|
||||
*
|
||||
* At this point a check is missed if the requested video
|
||||
* mode is possible with the provided video memory.
|
||||
* Check if symbol CONFIG_VIDEO_MB is at least:
|
||||
* - 1 (=1MiB) for VGA and SVGA
|
||||
* - 2 (=2MiB) for XGA
|
||||
* - 4 (=4MiB) for SXGA
|
||||
*/
|
||||
static void dc_setup_layout(u32 gx_base, const struct video_mode *mode)
|
||||
{
|
||||
u32 base = 0x00000000;
|
||||
|
||||
write32(gx_base + DC_FB_ST_OFFSET, base);
|
||||
|
||||
base += (COLOUR_DEPTH>>3) * mode->visible_pixel * mode->visible_lines;
|
||||
|
||||
write32(gx_base + DC_CB_ST_OFFSET, base);
|
||||
write32(gx_base + DC_CURS_ST_OFFSET, base);
|
||||
write32(gx_base + DC_VID_ST_OFFSET, base);
|
||||
write32(gx_base + DC_LINE_DELTA, ((COLOUR_DEPTH>>3) * mode->visible_pixel) >> 2);
|
||||
write32(gx_base + DC_BUF_SIZE, ((COLOUR_DEPTH>>3) * mode->visible_pixel) >> 3);
|
||||
}
|
||||
|
||||
/**
|
||||
* Setup the HSYNC/VSYNC, active video timing
|
||||
* @param[in] gx_base GX register area
|
||||
* @param[in] mode Data about the video mode to setup
|
||||
*
|
||||
* Sync signal generation is done in Geode GX1's chipset.
|
||||
* Note: This routine assumes unlocked DC registers
|
||||
*
|
||||
* |<------------------------- htotal ----------------------------->|
|
||||
* |<------------ hactive -------------->| |
|
||||
* | hblankstart-->| |
|
||||
* | hblankend-->|
|
||||
* | hsyncstart-->| |
|
||||
* | hsyncend-->| |
|
||||
* |#####################################___________________________| RGB data
|
||||
* |______________________________________________---------_________| HSYNC
|
||||
*
|
||||
* |<------------------------- vtotal ----------------------------->|
|
||||
* |<------------ vactive -------------->| |
|
||||
* | vblankstart-->| |
|
||||
* | vblankend-->|
|
||||
* | vsyncstart-->| |
|
||||
* | vsyncend-->| |
|
||||
* |#####################################___________________________| line data
|
||||
* |______________________________________________---------_________| YSYNC
|
||||
*/
|
||||
static void dc_setup_timing(u32 gx_base, const struct video_mode *mode)
|
||||
{
|
||||
u32 hactive, hblankstart, hsyncstart, hsyncend, hblankend, htotal;
|
||||
u32 vactive, vblankstart, vsyncstart, vsyncend, vblankend, vtotal;
|
||||
|
||||
hactive = mode->visible_pixel & 0x7FF;
|
||||
hblankstart = hactive;
|
||||
hsyncstart = mode->hsync_start & 0x7FF;
|
||||
hsyncend = mode->hsync_end & 0x7FF;
|
||||
hblankend = mode->line_length & 0x7FF;
|
||||
htotal = hblankend;
|
||||
|
||||
vactive = mode->visible_lines & 0x7FF;
|
||||
vblankstart = vactive;
|
||||
vsyncstart = mode->vsync_start & 0x7FF;
|
||||
vsyncend = mode->vsync_end & 0x7FF;
|
||||
vblankend = mode->picture_length & 0x7FF;
|
||||
vtotal = vblankend;
|
||||
|
||||
/* row description */
|
||||
write32(gx_base + DC_H_TIMING_1, (hactive - 1) | ((htotal - 1) << 16));
|
||||
/* horizontal blank description */
|
||||
write32(gx_base + DC_H_TIMING_2, (hblankstart - 1) | ((hblankend - 1) << 16));
|
||||
/* horizontal sync description */
|
||||
write32(gx_base + DC_H_TIMING_3, (hsyncstart - 1) | ((hsyncend - 1) << 16));
|
||||
write32(gx_base + DC_FP_H_TIMING, (hsyncstart - 1) | ((hsyncend - 1) << 16));
|
||||
|
||||
/* line description */
|
||||
write32(gx_base + DC_V_TIMING_1, (vactive - 1) | ((vtotal - 1) << 16));
|
||||
/* vertical blank description */
|
||||
write32(gx_base + DC_V_TIMING_2, (vblankstart - 1) | ((vblankend - 1) << 16));
|
||||
/* vertical sync description */
|
||||
write32(gx_base + DC_V_TIMING_3, (vsyncstart - 1) | ((vsyncend - 1) << 16));
|
||||
write32(gx_base + DC_FP_V_TIMING, (vsyncstart - 2) | ((vsyncend - 2) << 16));
|
||||
}
|
||||
|
||||
/**
|
||||
* Setup required internals to bring the mode up and running
|
||||
* @param[in] gx_base GX register area
|
||||
* @param[in] mode Data about the video mode to setup
|
||||
*
|
||||
* Must be setup in Geode GX1's chipset.
|
||||
* Note: This routine assumes unlocked DC registers.
|
||||
*/
|
||||
static void cs5530_activate_mode(u32 gx_base, const struct video_mode *mode)
|
||||
{
|
||||
write32(gx_base + DC_GENERAL_CFG, 0x00000080);
|
||||
mdelay(1);
|
||||
dc_setup_layout(gx_base,mode);
|
||||
dc_setup_timing(gx_base,mode);
|
||||
|
||||
write32(gx_base + DC_GENERAL_CFG, 0x2000C581);
|
||||
write32(gx_base + DC_TIMING_CFG, 0x0000002F);
|
||||
write32(gx_base + DC_OUTPUT_CFG, 0x00003004);
|
||||
}
|
||||
|
||||
/**
|
||||
* Activate the current mode to be "visible" outside
|
||||
* @param[in] gx_base GX register area
|
||||
* @param[in] mode Data about the video mode to setup
|
||||
*
|
||||
* As we now activate the interface this must be done
|
||||
* in the CS5530
|
||||
*/
|
||||
static void cs5530_activate_video(u32 io_base, const struct video_mode *mode)
|
||||
{
|
||||
u32 val;
|
||||
|
||||
val = (u32)mode->sync_pol << 8;
|
||||
write32(io_base + CS5530_DISPLAY_CONFIG, val | 0x0020002F);
|
||||
}
|
||||
|
||||
#if CONFIG_SPLASH_GRAPHIC
|
||||
|
||||
/*
|
||||
* This bitmap file must provide:
|
||||
* int width: pixel count in one line
|
||||
* int height: line count
|
||||
* int colours: ount of used colour
|
||||
* unsigned long colour_map[]: RGB 565 colours to be used
|
||||
* unsigned char bitmap[]: index per pixel into colour_map[], width*height pixels
|
||||
*/
|
||||
#include "bitmap.c"
|
||||
|
||||
/*
|
||||
* show a boot splash screen in the right lower corner of the screen
|
||||
* swidth: screen width in pixel
|
||||
* sheight: screen height in lines
|
||||
* pitch: line pitch in bytes
|
||||
* base: screen base address
|
||||
*
|
||||
* This routine assumes we are using a 16 bit colour depth!
|
||||
*/
|
||||
static void show_boot_splash_16(u32 swidth, u32 sheight, u32 pitch,void *base)
|
||||
{
|
||||
int word_count,i;
|
||||
unsigned short *adr;
|
||||
u32 xstart,ystart,x,y;
|
||||
/*
|
||||
* fill the screen with the colour of the
|
||||
* left top pixel in the graphic
|
||||
*/
|
||||
word_count = pitch * sheight;
|
||||
adr = (unsigned short*)base;
|
||||
for (i = 0; i < word_count; i++, adr++)
|
||||
*adr = colour_map[bitmap[0]];
|
||||
|
||||
/*
|
||||
* paint the splash
|
||||
*/
|
||||
xstart = swidth-width;
|
||||
ystart = sheight-height;
|
||||
for (y = 0; y < height; y++) {
|
||||
adr=(unsigned short*)(base + pitch*(y+ystart) + 2 * xstart);
|
||||
for (x = 0; x < width; x++) {
|
||||
*adr=(unsigned short)colour_map[(int)bitmap[x + y * width]];
|
||||
adr++;
|
||||
}
|
||||
}
|
||||
}
|
||||
#else
|
||||
# define show_boot_splash_16(w, x, y , z)
|
||||
#endif
|
||||
|
||||
/**
|
||||
* coreboot management part
|
||||
* @param[in] dev Info about the PCI device to initialise
|
||||
*/
|
||||
static void cs5530_vga_init(device_t dev)
|
||||
{
|
||||
const struct video_mode *mode;
|
||||
u32 io_base, gx_base;
|
||||
|
||||
io_base = pci_read_config32(dev, 0x10);
|
||||
gx_base = GX_BASE;
|
||||
mode = modes[CONFIG_GX1_VIDEOMODE];
|
||||
|
||||
printk(BIOS_DEBUG, "Setting up video mode %dx%d with %d Hz clock\n",
|
||||
mode->visible_pixel, mode->visible_lines, mode->pixel_clock);
|
||||
|
||||
cs5530_set_clock_frequency(io_base, mode->pll_value);
|
||||
|
||||
write32(gx_base + DC_UNLOCK, DC_UNLOCK_MAGIC);
|
||||
|
||||
show_boot_splash_16(mode->visible_pixel, mode->visible_lines,
|
||||
mode->visible_pixel * (COLOUR_DEPTH>>3), (void*)(GX_BASE + 0x800000));
|
||||
|
||||
cs5530_activate_mode(gx_base, mode);
|
||||
|
||||
cs5530_activate_video(io_base, mode);
|
||||
write32(gx_base + DC_UNLOCK, 0x00000000);
|
||||
}
|
||||
|
||||
static struct device_operations vga_ops = {
|
||||
.read_resources = pci_dev_read_resources,
|
||||
.set_resources = pci_dev_set_resources,
|
||||
.enable_resources = pci_dev_enable_resources,
|
||||
.init = cs5530_vga_init,
|
||||
.enable = NULL, /* not required */
|
||||
};
|
||||
|
||||
static const struct pci_driver vga_pci_driver __pci_driver = {
|
||||
.ops = &vga_ops,
|
||||
.vendor = PCI_VENDOR_ID_CYRIX,
|
||||
.device = PCI_DEVICE_ID_CYRIX_5530_VIDEO,
|
||||
};
|
||||
|
||||
#endif /* #if CONFIG_GX1_VIDEO */
|
Reference in New Issue
Block a user