mb/google/nissa/var/glassway: Adjust touchscreen power sequencing
Adjust touchscreen power sequencing for eKTH5015M. The INX touch panel (eKTH5015M) contains a pull-up register which causes TCHSCR_REPORT_EN pull-up abnormally from Z1 power on.Because the t25 must be at least greater than 20ms, TCHSCR_REPORT_EN is initialized to GPO_L in the early stage (romstage) to meet the spec. BUG=b:328170008 BRANCH=firmware-nissa-15217.B TEST=Build and check I2C devices timing meet spec. [INFO ] input: Elan Touchscreen as /devices/pci0000:00/0000:00:15.1/i2c_designware.1/i2c-10/i2c-ELAN0001:00/input/in4 Change-Id: I50f9c21ddee2bc9c1d313f63049cb587b4ae047a Signed-off-by: Frank Chu <frank_chu@pegatron.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/81135 Reviewed-by: Matt DeVillier <matt.devillier@gmail.com> Reviewed-by: Eric Lai <ericllai@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -100,6 +100,8 @@ static const struct pad_config romstage_gpio_table[] = {
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PAD_CFG_GPO(GPP_C0, 1, DEEP),
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/* C1 : SMBDATA ==> USI_RST_L */
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PAD_CFG_GPO(GPP_C1, 0, DEEP),
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/* C6 : SML1CLK ==> TCHSCR_REPORT_EN */
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PAD_CFG_GPO(GPP_C6, 0, DEEP),
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/* H12 : UART0_RTS# ==> SD_PERST_L */
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PAD_CFG_GPO(GPP_H12, 1, DEEP),
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};
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@ -323,13 +323,13 @@ chip soc/intel/alderlake
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register "desc" = ""ELAN Touchscreen""
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register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_C7_IRQ)"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C1)"
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register "reset_delay_ms" = "25"
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register "reset_delay_ms" = "20"
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register "reset_off_delay_ms" = "4"
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register "stop_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C6)"
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register "stop_delay_ms" = "25"
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register "stop_off_delay_ms" = "2"
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register "stop_delay_ms" = "5"
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register "stop_off_delay_ms" = "25"
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_C0)"
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register "enable_delay_ms" = "7"
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register "enable_delay_ms" = "25"
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register "has_power_resource" = "1"
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device i2c 10 on
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probe TOUCHSCREEN_SOURCE TOUCHSCREEN_UNPROVISIONED
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