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Enable UART on lemp10

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Change-Id: If82418b9dfcb63dfb7fdd192107d3f6b3d77d3b9
This commit is contained in:
Jeremy Soller
2020-11-30 11:40:55 -07:00
parent fd8c25ab61
commit b69fba193b
3 changed files with 11 additions and 3 deletions
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2
src/mainboard/system76/galp5/devicetree.cb
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@@ -282,7 +282,7 @@ chip soc/intel/tigerlake
end end
device ref uart2 on device ref uart2 on
# Debug console # Debug console
register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoPci" register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"
end end
device ref pcie_rp5 on device ref pcie_rp5 on
# PCIe root port #5 x4, Clock 2 (NVIDIA GPU) # PCIe root port #5 x4, Clock 2 (NVIDIA GPU)

4
src/mainboard/system76/lemp10/devicetree.cb
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@@ -249,6 +249,10 @@ chip soc/intel/tigerlake
#TODO Disable ME and HECI #TODO Disable ME and HECI
register "HeciEnabled" = "1" register "HeciEnabled" = "1"
end end
device ref uart2 on
# Debug console
register "SerialIoUartMode[PchSerialIoIndexUART2]" = "PchSerialIoSkipInit"
end
device ref sata on device ref sata on
# SATA1 (SSD2) # SATA1 (SSD2)
register "SataPortsEnable[1]" = "1" register "SataPortsEnable[1]" = "1"

8
src/mainboard/system76/lemp10/gpio.h
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@@ -10,6 +10,10 @@
/* Pad configuration in romstage. */ /* Pad configuration in romstage. */
static const struct pad_config early_gpio_table[] = { static const struct pad_config early_gpio_table[] = {
// UART2_RXD
PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1),
// UART2_TXD
PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1),
}; };
/* Pad configuration in ramstage. */ /* Pad configuration in ramstage. */
@@ -175,9 +179,9 @@ static const struct pad_config gpio_table[] = {
// PCH_I2C_SCL // PCH_I2C_SCL
PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1),
// UART2_RXD // UART2_RXD
PAD_NC(GPP_C20, NONE), PAD_CFG_NF(GPP_C20, UP_20K, DEEP, NF1),
// UART2_TXD // UART2_TXD
PAD_NC(GPP_C21, NONE), PAD_CFG_NF(GPP_C21, UP_20K, DEEP, NF1),
// GPP_C12_RTD3 // GPP_C12_RTD3
PAD_CFG_TERM_GPO(GPP_C22, 1, NONE, PLTRST), PAD_CFG_TERM_GPO(GPP_C22, 1, NONE, PLTRST),
// PCH_GPP_C23 // PCH_GPP_C23