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soc/intel/broadwell: Fix 16-bit read/write PCI_COMMAND register

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Change-Id: I0fd1a758d8838b3eea5640b41eee6a6893360aa3
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/40850
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Elyes HAOUAS 2020-04-29 10:42:34 +02:00 committed by Patrick Georgi
parent 3e42ee05d8
commit b887adf7a5
8 changed files with 25 additions and 42 deletions
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4
src/soc/intel/broadwell/adsp.c
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@ -24,9 +24,7 @@ static void adsp_init(struct device *dev)
u32 tmp32; u32 tmp32;
/* Ensure memory and bus master are enabled */ /* Ensure memory and bus master are enabled */
tmp32 = pci_read_config32(dev, PCI_COMMAND); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
tmp32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config32(dev, PCI_COMMAND, tmp32);
/* Find BAR0 and BAR1 */ /* Find BAR0 and BAR1 */
bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); bar0 = find_resource(dev, PCI_BASE_ADDRESS_0);

12
src/soc/intel/broadwell/hda.c
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@ -84,7 +84,6 @@ static void hda_init(struct device *dev)
u8 *base; u8 *base;
struct resource *res; struct resource *res;
u32 codec_mask; u32 codec_mask;
u32 reg32;
/* Find base address */ /* Find base address */
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
@ -95,8 +94,7 @@ static void hda_init(struct device *dev)
printk(BIOS_DEBUG, "HDA: base = %p\n", base); printk(BIOS_DEBUG, "HDA: base = %p\n", base);
/* Set Bus Master */ /* Set Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
hda_pch_init(dev, base); hda_pch_init(dev, base);
@ -110,7 +108,7 @@ static void hda_init(struct device *dev)
static void hda_enable(struct device *dev) static void hda_enable(struct device *dev)
{ {
u32 reg32; u16 reg16;
u8 reg8; u8 reg8;
reg8 = pci_read_config8(dev, 0x43); reg8 = pci_read_config8(dev, 0x43);
@ -126,10 +124,10 @@ static void hda_enable(struct device *dev)
printk(BIOS_INFO, "HDA disabled, I/O buffers routed to ADSP\n"); printk(BIOS_INFO, "HDA disabled, I/O buffers routed to ADSP\n");
/* Ensure memory, io, and bus master are all disabled */ /* Ensure memory, io, and bus master are all disabled */
reg32 = pci_read_config32(dev, PCI_COMMAND); reg16 = pci_read_config16(dev, PCI_COMMAND);
reg32 &= ~(PCI_COMMAND_MASTER | reg16 &= ~(PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO); PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
pci_write_config32(dev, PCI_COMMAND, reg32); pci_write_config16(dev, PCI_COMMAND, reg16);
/* Disable this device */ /* Disable this device */
pch_disable_devfn(dev); pch_disable_devfn(dev);

13
src/soc/intel/broadwell/me.c
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@ -600,17 +600,17 @@ static int mkhi_hmrfpo_lock_noack(void)
static void intel_me_finalize(struct device *dev) static void intel_me_finalize(struct device *dev)
{ {
u32 reg32; u16 reg16;
/* S3 path will have hidden this device already */ /* S3 path will have hidden this device already */
if (!mei_base_address || mei_base_address == (u8 *) 0xfffffff0) if (!mei_base_address || mei_base_address == (u8 *) 0xfffffff0)
return; return;
/* Make sure IO is disabled */ /* Make sure IO is disabled */
reg32 = pci_read_config32(dev, PCI_COMMAND); reg16 = pci_read_config16(dev, PCI_COMMAND);
reg32 &= ~(PCI_COMMAND_MASTER | reg16 &= ~(PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO); PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
pci_write_config32(dev, PCI_COMMAND, reg32); pci_write_config16(dev, PCI_COMMAND, reg16);
/* Hide the PCI device */ /* Hide the PCI device */
RCBA32_OR(FD2, PCH_DISABLE_MEI1); RCBA32_OR(FD2, PCH_DISABLE_MEI1);
@ -712,7 +712,6 @@ static int intel_mei_setup(struct device *dev)
{ {
struct resource *res; struct resource *res;
struct mei_csr host; struct mei_csr host;
u32 reg32;
/* Find the MMIO base for the ME interface */ /* Find the MMIO base for the ME interface */
res = find_resource(dev, PCI_BASE_ADDRESS_0); res = find_resource(dev, PCI_BASE_ADDRESS_0);
@ -723,9 +722,7 @@ static int intel_mei_setup(struct device *dev)
mei_base_address = res2mmio(res, 0, 0); mei_base_address = res2mmio(res, 0, 0);
/* Ensure Memory and Bus Master bits are set */ /* Ensure Memory and Bus Master bits are set */
reg32 = pci_read_config32(dev, PCI_COMMAND); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config32(dev, PCI_COMMAND, reg32);
/* Clean up status for next message */ /* Clean up status for next message */
read_host_csr(&host); read_host_csr(&host);

3
src/soc/intel/broadwell/minihd.c
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@ -62,8 +62,7 @@ static void minihd_init(struct device *dev)
printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base); printk(BIOS_DEBUG, "Mini-HD: base = %p\n", base);
/* Set Bus Master */ /* Set Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
pci_write_config32(dev, PCI_COMMAND, reg32 | PCI_COMMAND_MASTER);
/* Mini-HD configuration */ /* Mini-HD configuration */
reg32 = read32(base + 0x100c); reg32 = read32(base + 0x100c);

12
src/soc/intel/broadwell/pch.c
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@ -171,7 +171,7 @@ void pch_disable_devfn(struct device *dev)
void broadwell_pch_enable_dev(struct device *dev) void broadwell_pch_enable_dev(struct device *dev)
{ {
u32 reg32; u16 reg16;
/* These devices need special enable/disable handling */ /* These devices need special enable/disable handling */
switch (PCI_SLOT(dev->path.pci.devfn)) { switch (PCI_SLOT(dev->path.pci.devfn)) {
@ -185,18 +185,16 @@ void broadwell_pch_enable_dev(struct device *dev)
printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev)); printk(BIOS_DEBUG, "%s: Disabling device\n", dev_path(dev));
/* Ensure memory, io, and bus master are all disabled */ /* Ensure memory, io, and bus master are all disabled */
reg32 = pci_read_config32(dev, PCI_COMMAND); reg16 = pci_read_config16(dev, PCI_COMMAND);
reg32 &= ~(PCI_COMMAND_MASTER | reg16 &= ~(PCI_COMMAND_MASTER |
PCI_COMMAND_MEMORY | PCI_COMMAND_IO); PCI_COMMAND_MEMORY | PCI_COMMAND_IO);
pci_write_config32(dev, PCI_COMMAND, reg32); pci_write_config16(dev, PCI_COMMAND, reg16);
/* Disable this device if possible */ /* Disable this device if possible */
pch_disable_devfn(dev); pch_disable_devfn(dev);
} else { } else {
/* Enable SERR */ /* Enable SERR */
reg32 = pci_read_config32(dev, PCI_COMMAND); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
reg32 |= PCI_COMMAND_SERR;
pci_write_config32(dev, PCI_COMMAND, reg32);
} }
} }

10
src/soc/intel/broadwell/pcie.c
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@ -574,19 +574,14 @@ static void pch_pcie_early(struct device *dev)
static void pch_pcie_init(struct device *dev) static void pch_pcie_init(struct device *dev)
{ {
u16 reg16; u16 reg16;
u32 reg32;
printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n"); printk(BIOS_DEBUG, "Initializing PCH PCIe bridge.\n");
/* Enable SERR */ /* Enable SERR */
reg32 = pci_read_config32(dev, PCI_COMMAND); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_SERR);
reg32 |= PCI_COMMAND_SERR;
pci_write_config32(dev, PCI_COMMAND, reg32);
/* Enable Bus Master */ /* Enable Bus Master */
reg32 = pci_read_config32(dev, PCI_COMMAND); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER);
reg32 |= PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32);
/* Set Cache Line Size to 0x10 */ /* Set Cache Line Size to 0x10 */
pci_write_config8(dev, 0x0c, 0x10); pci_write_config8(dev, 0x0c, 0x10);
@ -597,6 +592,7 @@ static void pch_pcie_init(struct device *dev)
pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16); pci_write_config16(dev, PCI_BRIDGE_CONTROL, reg16);
#ifdef EVEN_MORE_DEBUG #ifdef EVEN_MORE_DEBUG
u32 reg32;
reg32 = pci_read_config32(dev, 0x20); reg32 = pci_read_config32(dev, 0x20);
printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32); printk(BIOS_SPEW, " MBL = 0x%08x\n", reg32);
reg32 = pci_read_config32(dev, 0x24); reg32 = pci_read_config32(dev, 0x24);

5
src/soc/intel/broadwell/serialio.c
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@ -160,14 +160,11 @@ static void serialio_init(struct device *dev)
config_t *config = config_of(dev); config_t *config = config_of(dev);
struct resource *bar0, *bar1; struct resource *bar0, *bar1;
int sio_index = -1; int sio_index = -1;
u32 reg32;
printk(BIOS_DEBUG, "Initializing Serial IO device\n"); printk(BIOS_DEBUG, "Initializing Serial IO device\n");
/* Ensure memory and bus master are enabled */ /* Ensure memory and bus master are enabled */
reg32 = pci_read_config32(dev, PCI_COMMAND); pci_or_config16(dev, PCI_COMMAND, PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY);
reg32 |= PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config32(dev, PCI_COMMAND, reg32);
/* Find BAR0 and BAR1 */ /* Find BAR0 and BAR1 */
bar0 = find_resource(dev, PCI_BASE_ADDRESS_0); bar0 = find_resource(dev, PCI_BASE_ADDRESS_0);

8
src/soc/intel/broadwell/smihandler.c
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@ -69,7 +69,7 @@ static void busmaster_disable_on_bus(int bus)
for (slot = 0; slot < 0x20; slot++) { for (slot = 0; slot < 0x20; slot++) {
for (func = 0; func < 8; func++) { for (func = 0; func < 8; func++) {
u32 reg32; u16 reg16;
pci_devfn_t dev = PCI_DEV(bus, slot, func); pci_devfn_t dev = PCI_DEV(bus, slot, func);
val = pci_read_config32(dev, PCI_VENDOR_ID); val = pci_read_config32(dev, PCI_VENDOR_ID);
@ -79,9 +79,9 @@ static void busmaster_disable_on_bus(int bus)
continue; continue;
/* Disable Bus Mastering for this one device */ /* Disable Bus Mastering for this one device */
reg32 = pci_read_config32(dev, PCI_COMMAND); reg16 = pci_read_config16(dev, PCI_COMMAND);
reg32 &= ~PCI_COMMAND_MASTER; reg16 &= ~PCI_COMMAND_MASTER;
pci_write_config32(dev, PCI_COMMAND, reg32); pci_write_config16(dev, PCI_COMMAND, reg16);
/* If this is a bridge, then follow it. */ /* If this is a bridge, then follow it. */
hdr = pci_read_config8(dev, PCI_HEADER_TYPE); hdr = pci_read_config8(dev, PCI_HEADER_TYPE);