sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/brask/var/constitution: correct Type-A USB3 port0/1 tx_de_emp

Browse Source 
Set Type-A USB3 port0/1 tx_de_emp to 0x2B to fix the USB3 Gen2
RX signal integrity issue.

BUG=None
TEST=build FW and check Type-A USB3 port0/port1 RX pass

Change-Id: I9296ae5a8a9d7aa49b3c7529a9c1b2d2829b15d0
Signed-off-by: Morris Hsu <morris-hsu@quanta.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/74142
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
This commit is contained in:
Morris Hsu
2023-03-31 14:53:02 +08:00
committed by Felix Held
parent 0973c32c5d
commit b99cd85f74
1 changed files with 13 additions and 0 deletions
Download Patch File Download Diff File Expand all files Collapse all files

13
src/mainboard/google/brya/variants/constitution/overridetree.cb
View File

@ -22,6 +22,19 @@ chip soc/intel/alderlake
register "usb2_ports[5]" = "USB2_PORT_EMPTY" # Disable USB2 Port 5
register "usb2_ports[6]" = "USB2_PORT_EMPTY" # Disable USB2 Port 6
register "usb3_ports[0]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.tx_de_emp = 0x2B,
.tx_downscale_amp = 0x00,
}" # Type-A port A0
register "usb3_ports[1]" = "{
.enable = 1,
.ocpin = OC_SKIP,
.tx_de_emp = 0x2B,
.tx_downscale_amp = 0x00,
}" # Type-A port A1
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC_SKIP)" # HDMI-IN
register "usb3_ports[3]" = "USB3_PORT_EMPTY" # Disable Type-A port A3