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src/southbridge: Code formating

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Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16291
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Elyes HAOUAS
2016-08-31 19:22:16 +02:00
committed by Martin Roth
parent 2e4d80687d
commit ba28e8d73b
130 changed files with 1484 additions and 1589 deletions
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4
src/southbridge/amd/agesa/hudson/acpi/fch.asl
View File

@@ -183,9 +183,9 @@ Method(_INI, 0) {
Method(OSFL, 0){
if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
if (LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
if(CondRefOf(\_OSI))
if (CondRefOf(\_OSI))
{
Store(1, OSVR) /* Assume some form of XP */
if (\_OSI("Windows 2006")) /* Vista */

2
src/southbridge/amd/amd8111/acpi.c
View File

@@ -152,7 +152,7 @@ static void acpi_init(struct device *dev)
/* Throttle the CPU speed down for testing */
on = SLOW_CPU_OFF;
get_option(&on, "slow_cpu");
if(on) {
if (on) {
pm10_bar = (pci_read_config16(dev, 0x58)&0xff00);
outl(((on<<1)+0x10) ,(pm10_bar + 0x10));
inl(pm10_bar + 0x10);

12
src/southbridge/amd/amd8111/amd8111_smbus.h
View File

@@ -26,11 +26,11 @@ static int smbus_wait_until_ready(unsigned smbus_io_base)
if ((val & 0x800) == 0) {
break;
}
if(loops == (SMBUS_TIMEOUT / 2)) {
if (loops == (SMBUS_TIMEOUT / 2)) {
outw(inw(smbus_io_base + SMBGSTATUS),
smbus_io_base + SMBGSTATUS);
}
} while(--loops);
} while (--loops);
return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
}
@@ -46,7 +46,7 @@ static int smbus_wait_until_done(unsigned smbus_io_base)
if (((val & 0x8) == 0) | ((val & 0x0037) != 0)) {
break;
}
} while(--loops);
} while (--loops);
return loops?0:SMBUS_WAIT_UNTIL_DONE_TIMEOUT;
}
@@ -267,11 +267,11 @@ static int do_smbus_block_read(unsigned smbus_io_base, unsigned device, unsigned
}
/* read data block */
for(i=0; i<msglen && i<bytes; i++) {
for (i=0; i<msglen && i<bytes; i++) {
buf[i] = inw(smbus_io_base + SMBHSTFIFO) & 0xff;
}
/* empty fifo */
while(bytes++<msglen) {
while (bytes++<msglen) {
inw(smbus_io_base + SMBHSTFIFO);
}
@@ -305,7 +305,7 @@ static int do_smbus_block_write(unsigned smbus_io_base, unsigned device, unsigne
outw(bytes, smbus_io_base + SMBHSTDAT);
/* set the data block */
for(i=0; i<bytes; i++) {
for (i=0; i<bytes; i++) {
outw(buf[i], smbus_io_base + SMBHSTFIFO);
}

40
src/southbridge/amd/amd8111/early_ctrl.c
View File

@@ -4,16 +4,16 @@
/* by yhlu 2005.10 */
static unsigned get_sbdn(unsigned bus)
{
device_t dev;
device_t dev;
/* Find the device.
* There can only be one 8111 on a hypertransport chain/bus.
*/
dev = pci_locate_device_on_bus(
PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI),
bus);
/* Find the device.
* There can only be one 8111 on a hypertransport chain/bus.
*/
dev = pci_locate_device_on_bus(
PCI_ID(PCI_VENDOR_ID_AMD, PCI_DEVICE_ID_AMD_8111_PCI),
bus);
return (dev>>15) & 0x1f;
return (dev>>15) & 0x1f;
}
@@ -40,34 +40,34 @@ static void enable_cf9(void)
void hard_reset(void)
{
set_bios_reset();
/* reset */
enable_cf9();
outb(0x0e, 0x0cf9); // make sure cf9 is enabled
set_bios_reset();
/* reset */
enable_cf9();
outb(0x0e, 0x0cf9); // make sure cf9 is enabled
}
void enable_fid_change_on_sb(unsigned sbbusn, unsigned sbdn)
{
device_t dev;
device_t dev;
dev = PCI_DEV(sbbusn, sbdn+1, 3); // ACPI
pci_write_config8(dev, 0x74, 4);
pci_write_config8(dev, 0x74, 4);
/* set VFSMAF ( VID/FID System Management Action Field) to 2 */
pci_write_config32(dev, 0x70, 2<<12);
/* set VFSMAF ( VID/FID System Management Action Field) to 2 */
pci_write_config32(dev, 0x70, 2<<12);
}
static void soft_reset_x(unsigned sbbusn, unsigned sbdn)
{
device_t dev;
device_t dev;
dev = PCI_DEV(sbbusn, sbdn+1, 0); //ISA
/* Reset */
set_bios_reset();
pci_write_config8(dev, 0x47, 1);
/* Reset */
set_bios_reset();
pci_write_config8(dev, 0x47, 1);
}

4
src/southbridge/amd/amd8111/ide.c
View File

@@ -33,8 +33,8 @@ static void ide_init(struct device *dev)
pci_write_config16(dev, 0x40, word);
byte = 0x20 ; // Latency: 64-->32
pci_write_config8(dev, 0xd, byte);
byte = 0x20 ; // Latency: 64-->32
pci_write_config8(dev, 0xd, byte);
word = 0x0f;
pci_write_config16(dev, 0x42, word);

22
src/southbridge/amd/amd8111/reset.c
View File

@@ -12,26 +12,26 @@
static void pci_write_config8(pci_devfn_t dev, unsigned where, unsigned char value)
{
unsigned addr;
addr = (dev>>4) | where;
outl(0x80000000 | (addr & ~3), 0xCF8);
outb(value, 0xCFC + (addr & 3));
unsigned addr;
addr = (dev>>4) | where;
outl(0x80000000 | (addr & ~3), 0xCF8);
outb(value, 0xCFC + (addr & 3));
}
static void pci_write_config32(pci_devfn_t dev, unsigned where, unsigned value)
{
unsigned addr;
addr = (dev>>4) | where;
outl(0x80000000 | (addr & ~3), 0xCF8);
outl(value, 0xCFC);
addr = (dev>>4) | where;
outl(0x80000000 | (addr & ~3), 0xCF8);
outl(value, 0xCFC);
}
static unsigned pci_read_config32(pci_devfn_t dev, unsigned where)
{
unsigned addr;
addr = (dev>>4) | where;
outl(0x80000000 | (addr & ~3), 0xCF8);
return inl(0xCFC);
addr = (dev>>4) | where;
outl(0x80000000 | (addr & ~3), 0xCF8);
return inl(0xCFC);
}
#define PCI_DEV_INVALID (0xffffffffU)
@@ -40,7 +40,7 @@ static pci_devfn_t pci_locate_device_on_bus(unsigned pci_id, unsigned bus)
pci_devfn_t dev, last;
dev = PCI_DEV(bus, 0, 0);
last = PCI_DEV(bus, 31, 7);
for(; dev <= last; dev += PCI_DEV(0,0,1)) {
for (; dev <= last; dev += PCI_DEV(0,0,1)) {
unsigned int id;
id = pci_read_config32(dev, 0);
if (id == pci_id) {

65
src/southbridge/amd/amd8131/bridge.c
View File

@@ -19,8 +19,7 @@ static void amd8131_walk_children(struct bus *bus,
void (*visit)(device_t dev, void *ptr), void *ptr)
{
device_t child;
for(child = bus->children; child; child = child->sibling)
{
for (child = bus->children; child; child = child->sibling) {
if (child->path.type != DEVICE_PATH_PCI) {
continue;
}
@@ -72,7 +71,7 @@ static void amd8131_pcix_tune_dev(device_t dev, void *ptr)
sibs = info->master_devices - 1;
/* Count how many sibling functions this device has */
sib_funcs = 0;
for(sib = dev->bus->children; sib; sib = sib->sibling) {
for (sib = dev->bus->children; sib; sib = sib->sibling) {
if (sib == dev) {
continue;
}
@@ -258,7 +257,7 @@ static void amd8131_scan_bus(struct bus *bus,
/* Don't allow the 8131 or any of it's parent busses to
* implement relaxed ordering. Errata #58
*/
for(pbus = bus; !pbus->disable_relaxed_ordering; pbus = pbus->dev->bus) {
for (pbus = bus; !pbus->disable_relaxed_ordering; pbus = pbus->dev->bus) {
printk(BIOS_SPEW, "%s disabling relaxed ordering\n",
bus_path(pbus));
pbus->disable_relaxed_ordering = 1;
@@ -280,57 +279,57 @@ static void amd8131_pcix_init(device_t dev)
/* Enable memory write and invalidate ??? */
byte = pci_read_config8(dev, 0x04);
byte |= 0x10;
pci_write_config8(dev, 0x04, byte);
byte |= 0x10;
pci_write_config8(dev, 0x04, byte);
/* Set drive strength */
word = pci_read_config16(dev, 0xe0);
word = 0x0404;
pci_write_config16(dev, 0xe0, word);
word = 0x0404;
pci_write_config16(dev, 0xe0, word);
word = pci_read_config16(dev, 0xe4);
word = 0x0404;
pci_write_config16(dev, 0xe4, word);
word = 0x0404;
pci_write_config16(dev, 0xe4, word);
/* Set impedance */
word = pci_read_config16(dev, 0xe8);
word = 0x0404;
pci_write_config16(dev, 0xe8, word);
word = 0x0404;
pci_write_config16(dev, 0xe8, word);
/* Set discard unrequested prefetch data */
/* Errata #51 */
word = pci_read_config16(dev, 0x4c);
word |= 1;
pci_write_config16(dev, 0x4c, word);
word |= 1;
pci_write_config16(dev, 0x4c, word);
/* Set split transaction limits */
word = pci_read_config16(dev, 0xa8);
pci_write_config16(dev, 0xaa, word);
pci_write_config16(dev, 0xaa, word);
word = pci_read_config16(dev, 0xac);
pci_write_config16(dev, 0xae, word);
pci_write_config16(dev, 0xae, word);
/* Set up error reporting, enable all */
/* system error enable */
dword = pci_read_config32(dev, 0x04);
dword |= (1<<8);
pci_write_config32(dev, 0x04, dword);
dword |= (1<<8);
pci_write_config32(dev, 0x04, dword);
/* system and error parity enable */
dword = pci_read_config32(dev, 0x3c);
dword |= (3<<16);
pci_write_config32(dev, 0x3c, dword);
dword |= (3<<16);
pci_write_config32(dev, 0x3c, dword);
/* NMI enable */
nmi_option = NMI_OFF;
get_option(&nmi_option, "nmi");
if(nmi_option) {
if (nmi_option) {
dword = pci_read_config32(dev, 0x44);
dword |= (1<<0);
pci_write_config32(dev, 0x44, dword);
dword |= (1<<0);
pci_write_config32(dev, 0x44, dword);
}
/* Set up CRC flood enable */
dword = pci_read_config32(dev, 0xc0);
if(dword) { /* do device A only */
if (dword) { /* do device A only */
dword = pci_read_config32(dev, 0xc4);
dword |= (1<<1);
pci_write_config32(dev, 0xc4, dword);
@@ -377,22 +376,22 @@ static void bridge_set_resources(struct device *dev)
static struct device_operations pcix_ops = {
#if BRIDGE_40_BIT_SUPPORT
.read_resources = bridge_read_resources,
.set_resources = bridge_set_resources,
.read_resources = bridge_read_resources,
.set_resources = bridge_set_resources,
#else
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
#endif
.enable_resources = pci_bus_enable_resources,
.init = amd8131_pcix_init,
.scan_bus = amd8131_scan_bridge,
.init = amd8131_pcix_init,
.scan_bus = amd8131_scan_bridge,
.reset_bus = pci_bus_reset,
};
static const struct pci_driver pcix_driver __pci_driver = {
.ops = &pcix_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = 0x7450,
.ops = &pcix_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = 0x7450,
};

151
src/southbridge/amd/amd8132/bridge.c
View File

@@ -32,8 +32,7 @@ static void amd8132_walk_children(struct bus *bus,
void (*visit)(device_t dev, void *ptr), void *ptr)
{
device_t child;
for(child = bus->children; child; child = child->sibling)
{
for (child = bus->children; child; child = child->sibling) {
if (child->path.type != DEVICE_PATH_PCI) {
continue;
}
@@ -126,11 +125,11 @@ static void amd8132_pcix_tune_dev(device_t dev, void *ptr)
cmd |= max_tran << 4;
}
/* Don't attempt to handle PCI-X errors */
cmd &= ~PCI_X_CMD_DPERR_E;
if (orig_cmd != cmd) {
pci_write_config16(dev, cap + PCI_X_CMD, cmd);
}
/* Don't attempt to handle PCI-X errors */
cmd &= ~PCI_X_CMD_DPERR_E;
if (orig_cmd != cmd) {
pci_write_config16(dev, cap + PCI_X_CMD, cmd);
}
}
@@ -203,18 +202,18 @@ static void amd8132_pcix_init(device_t dev)
unsigned chip_rev;
/* Find the revision of the 8132 */
chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);
chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);
/* Enable memory write and invalidate ??? */
dword = pci_read_config32(dev, 0x04);
dword |= 0x10;
dword |= 0x10;
dword &= ~(1<<6); // PERSP Parity Error Response
pci_write_config32(dev, 0x04, dword);
pci_write_config32(dev, 0x04, dword);
if (chip_rev == 0x01) {
/* Errata #37 */
byte = pci_read_config8(dev, 0x0c);
if(byte == 0x08 )
if (byte == 0x08 )
pci_write_config8(dev, 0x0c, 0x10);
#if 0
@@ -229,58 +228,58 @@ static void amd8132_pcix_init(device_t dev)
/* Set up error reporting, enable all */
/* system error enable */
dword = pci_read_config32(dev, 0x04);
dword |= (1<<8);
pci_write_config32(dev, 0x04, dword);
dword |= (1<<8);
pci_write_config32(dev, 0x04, dword);
/* system and error parity enable */
dword = pci_read_config32(dev, 0x3c);
dword |= (3<<16);
pci_write_config32(dev, 0x3c, dword);
dword |= (3<<16);
pci_write_config32(dev, 0x3c, dword);
dword = pci_read_config32(dev, 0x40);
// dword &= ~(1<<31); /* WriteChainEnable */
dword = pci_read_config32(dev, 0x40);
// dword &= ~(1<<31); /* WriteChainEnable */
dword |= (1<<31);
dword |= (1<<7);// must set to 1
dword |= (3<<21); //PCIErrorSerrDisable
pci_write_config32(dev, 0x40, dword);
pci_write_config32(dev, 0x40, dword);
/* EXTARB = 1, COMPAT = 0 */
dword = pci_read_config32(dev, 0x48);
dword |= (1<<3);
/* EXTARB = 1, COMPAT = 0 */
dword = pci_read_config32(dev, 0x48);
dword |= (1<<3);
dword &= ~(1<<0);
dword |= (1<<15); //CLEARPCILOG_L
dword |= (1<<19); //PERR FATAL Enable
dword |= (1<<22); // SERR FATAL Enable
dword |= (1<<23); // LPMARBENABLE
dword |= (0x61<<24); //LPMARBCOUNT
pci_write_config32(dev, 0x48, dword);
pci_write_config32(dev, 0x48, dword);
dword = pci_read_config32(dev, 0x4c);
dword |= (1<<6); //Initial prefetch for memory read line request
dword = pci_read_config32(dev, 0x4c);
dword |= (1<<6); //Initial prefetch for memory read line request
dword |= (1<<9); //continuous prefetch Enable for memory read line request
pci_write_config32(dev, 0x4c, dword);
pci_write_config32(dev, 0x4c, dword);
/* Disable Single-Bit-Error Correction [30] = 0 */
dword = pci_read_config32(dev, 0x70);
dword &= ~(1<<30);
pci_write_config32(dev, 0x70, dword);
/* Disable Single-Bit-Error Correction [30] = 0 */
dword = pci_read_config32(dev, 0x70);
dword &= ~(1<<30);
pci_write_config32(dev, 0x70, dword);
//link
dword = pci_read_config32(dev, 0xd4);
dword |= (0x5c<<16);
pci_write_config32(dev, 0xd4, dword);
dword = pci_read_config32(dev, 0xd4);
dword |= (0x5c<<16);
pci_write_config32(dev, 0xd4, dword);
/* TxSlack0 [16:17] = 0, RxHwLookahdEn0 [18] = 1, TxSlack1 [24:25] = 0, RxHwLookahdEn1 [26] = 1 */
dword = pci_read_config32(dev, 0xdc);
/* TxSlack0 [16:17] = 0, RxHwLookahdEn0 [18] = 1, TxSlack1 [24:25] = 0, RxHwLookahdEn1 [26] = 1 */
dword = pci_read_config32(dev, 0xdc);
dword |= (1<<1) | (1<<4); // stream disable 1 to 0 , DBLINSRATE
dword |= (1<<18)|(1<<26);
dword &= ~((3<<16)|(3<<24));
pci_write_config32(dev, 0xdc, dword);
dword |= (1<<18)|(1<<26);
dword &= ~((3<<16)|(3<<24));
pci_write_config32(dev, 0xdc, dword);
/* Set up CRC flood enable */
dword = pci_read_config32(dev, 0xc0);
if(dword) { /* do device A only */
if (dword) { /* do device A only */
#if 0
dword = pci_read_config32(dev, 0xc4);
dword |= (1<<1);
@@ -290,12 +289,12 @@ static void amd8132_pcix_init(device_t dev)
pci_write_config32(dev, 0xc8, dword);
#endif
if (chip_rev == 0x11) {
/* [18] Clock Gate Enable = 1 */
dword = pci_read_config32(dev, 0xf0);
dword |= 0x00040008;
pci_write_config32(dev, 0xf0, dword);
}
if (chip_rev == 0x11) {
/* [18] Clock Gate Enable = 1 */
dword = pci_read_config32(dev, 0xf0);
dword |= 0x00040008;
pci_write_config32(dev, 0xf0, dword);
}
}
return;
@@ -337,22 +336,22 @@ static void bridge_set_resources(struct device *dev)
static struct device_operations pcix_ops = {
#if BRIDGE_40_BIT_SUPPORT
.read_resources = bridge_read_resources,
.set_resources = bridge_set_resources,
.read_resources = bridge_read_resources,
.set_resources = bridge_set_resources,
#else
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
#endif
.enable_resources = pci_bus_enable_resources,
.init = amd8132_pcix_init,
.scan_bus = amd8132_scan_bridge,
.init = amd8132_pcix_init,
.scan_bus = amd8132_scan_bridge,
.reset_bus = pci_bus_reset,
};
static const struct pci_driver pcix_driver __pci_driver = {
.ops = &pcix_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = 0x7458,
.ops = &pcix_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = 0x7458,
};
static void ioapic_enable(device_t dev)
@@ -369,39 +368,39 @@ static void ioapic_enable(device_t dev)
}
static void amd8132_ioapic_init(device_t dev)
{
uint32_t dword;
unsigned chip_rev;
uint32_t dword;
unsigned chip_rev;
/* Find the revision of the 8132 */
chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);
/* Find the revision of the 8132 */
chip_rev = pci_read_config8(dev, PCI_CLASS_REVISION);
if (chip_rev == 0x01) {
if (chip_rev == 0x01) {
#if 0
/* Errata #43 */
dword = pci_read_config32(dev, 0xc8);
/* Errata #43 */
dword = pci_read_config32(dev, 0xc8);
dword |= (0x3<<23);
pci_write_config32(dev, 0xc8, dword);
#endif
}
}
if ( (chip_rev == 0x11) ||(chip_rev == 0x12) ) {
//for b1 b2
/* Errata #73 */
dword = pci_read_config32(dev, 0x80);
dword |= (0x1f<<5);
pci_write_config32(dev, 0x80, dword);
dword = pci_read_config32(dev, 0x88);
dword |= (0x1f<<5);
pci_write_config32(dev, 0x88, dword);
if ( (chip_rev == 0x11) ||(chip_rev == 0x12) ) {
//for b1 b2
/* Errata #73 */
dword = pci_read_config32(dev, 0x80);
dword |= (0x1f<<5);
pci_write_config32(dev, 0x80, dword);
dword = pci_read_config32(dev, 0x88);
dword |= (0x1f<<5);
pci_write_config32(dev, 0x88, dword);
/* Errata #74 */
dword = pci_read_config32(dev, 0x7c);
dword &= ~(0x3<<30);
dword |= (0x01<<30);
pci_write_config32(dev, 0x7c, dword);
}
/* Errata #74 */
dword = pci_read_config32(dev, 0x7c);
dword &= ~(0x3<<30);
dword |= (0x01<<30);
pci_write_config32(dev, 0x7c, dword);
}
}

2
src/southbridge/amd/amd8151/agp3.c
View File

@@ -66,7 +66,7 @@ static void agp3dev_enable(device_t dev)
}
static struct pci_operations pci_ops_pci_dev = {
.set_subsystem = pci_dev_set_subsystem,
.set_subsystem = pci_dev_set_subsystem,
};
static struct device_operations agp3dev_ops = {

2
src/southbridge/amd/cimx/sb700/Platform.h
View File

@@ -62,7 +62,7 @@ void TraceCode ( UINT32 Level, UINT32 Code);
#if CONFIG_REDIRECT_SBCIMX_TRACE_TO_SERIAL
#define TRACE(Arguments) printk Arguments
#else
#define TRACE(Arguments) do {} while(0)
#define TRACE(Arguments) do {} while (0)
#endif
#define TRACECODE(Arguments)
#endif

2
src/southbridge/amd/cimx/sb700/reset.c
View File

@@ -32,7 +32,7 @@ static inline void set_bios_reset(void)
int i;
nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
for(i = 0; i < nodes; i++) {
for (i = 0; i < nodes; i++) {
dev = NODE_PCI(i, 0);
htic = pci_read_config32(dev, HT_INIT_CONTROL);
htic &= ~HTIC_BIOSR_Detect;

4
src/southbridge/amd/cimx/sb800/early.c
View File

@@ -66,6 +66,6 @@ void sb800_clk_output_48Mhz(void)
/* AcpiMMioDecodeEn */
RWPMIO(SB_PMIOA_REG24, AccWidthUint8, ~(BIT0 + BIT1), BIT0);
*(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
*(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */
*(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) &= ~((1 << 0) | (1 << 2)); /* 48Mhz */
*(volatile u32 *)(ACPI_MMIO_BASE + MISC_BASE + 0x40) |= 1 << 1; /* 48Mhz */
}

54
src/southbridge/amd/cimx/sb800/late.c
View File

@@ -151,21 +151,21 @@ unsigned long acpi_fill_mcfg(unsigned long current)
}
static struct device_operations lpc_ops = {
.read_resources = lpc_read_resources,
.set_resources = lpc_set_resources,
.enable_resources = pci_dev_enable_resources,
.read_resources = lpc_read_resources,
.set_resources = lpc_set_resources,
.enable_resources = pci_dev_enable_resources,
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
.write_acpi_tables = acpi_write_hpet,
#endif
.init = lpc_init,
.scan_bus = scan_lpc_bus,
.ops_pci = &lops_pci,
.init = lpc_init,
.scan_bus = scan_lpc_bus,
.ops_pci = &lops_pci,
};
static const struct pci_driver lpc_driver __pci_driver = {
.ops = &lpc_ops,
.vendor = PCI_VENDOR_ID_ATI,
.device = PCI_DEVICE_ID_ATI_SB800_LPC,
.ops = &lpc_ops,
.vendor = PCI_VENDOR_ID_ATI,
.device = PCI_DEVICE_ID_ATI_SB800_LPC,
};
static struct device_operations sata_ops = {
@@ -226,34 +226,34 @@ static const struct pci_driver usb_ohci4_driver __pci_driver = {
static struct device_operations azalia_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = 0,
.scan_bus = 0,
.ops_pci = &lops_pci,
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = 0,
.scan_bus = 0,
.ops_pci = &lops_pci,
};
static const struct pci_driver azalia_driver __pci_driver = {
.ops = &azalia_ops,
.vendor = PCI_VENDOR_ID_ATI,
.device = PCI_DEVICE_ID_ATI_SB800_HDA,
.ops = &azalia_ops,
.vendor = PCI_VENDOR_ID_ATI,
.device = PCI_DEVICE_ID_ATI_SB800_HDA,
};
static struct device_operations gec_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = 0,
.scan_bus = 0,
.ops_pci = &lops_pci,
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = 0,
.scan_bus = 0,
.ops_pci = &lops_pci,
};
static const struct pci_driver gec_driver __pci_driver = {
.ops = &gec_ops,
.vendor = PCI_VENDOR_ID_ATI,
.device = PCI_DEVICE_ID_ATI_SB800_GEC,
.ops = &gec_ops,
.vendor = PCI_VENDOR_ID_ATI,
.device = PCI_DEVICE_ID_ATI_SB800_GEC,
};
/**

2
src/southbridge/amd/cimx/sb800/reset.c
View File

@@ -32,7 +32,7 @@ static inline void set_bios_reset(void)
int i;
nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
for(i = 0; i < nodes; i++) {
for (i = 0; i < nodes; i++) {
dev = NODE_PCI(i, 0);
htic = pci_read_config32(dev, HT_INIT_CONTROL);
htic &= ~HTIC_BIOSR_Detect;

8
src/southbridge/amd/cimx/sb800/smbus.c
View File

@@ -63,7 +63,7 @@ int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - smbus not ready.\n");
printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_recv_byte - smbus not ready.\n");
return -2; /* not ready */
}
@@ -93,7 +93,7 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val)
u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - smbus not ready.\n");
printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_send_byte - smbus not ready.\n");
return -2; /* not ready */
}
@@ -123,7 +123,7 @@ int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address)
u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - smbus not ready.\n");
printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_read_byte - smbus not ready.\n");
return -2; /* not ready */
}
@@ -156,7 +156,7 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val)
u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - smbus not ready.\n");
printk(BIOS_DEBUG, "SB800 - Smbus.c - do_smbus_write_byte - smbus not ready.\n");
return -2; /* not ready */
}

4
src/southbridge/amd/cimx/sb900/cfg.c
View File

@@ -28,7 +28,7 @@
void sb900_cimx_config(AMDSBCFG *sb_config)
{
if (!sb_config) {
printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - No sb_config.\n");
printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - No sb_config.\n");
return;
}
printk(BIOS_INFO, "SB900 - Cfg.c - sb900_cimx_config - Start.\n");
@@ -257,7 +257,7 @@ void sb900_cimx_config(AMDSBCFG *sb_config)
void SbPowerOnInit_Config(AMDSBCFG *sb_config)
{
if (!sb_config) {
printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - No sb_config.\n");
printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - No sb_config.\n");
return;
}
printk(BIOS_INFO, "SB900 - Cfg.c - SbPowerOnInit_Config - Start.\n");

2
src/southbridge/amd/cimx/sb900/early.c
View File

@@ -60,7 +60,7 @@ void sb_poweron_init(void)
outb(0xEA, 0xCD6);
data = inb(0xCD7);
data &= !BIT0;
if(!CONFIG_PCIB_ENABLE) {
if (!CONFIG_PCIB_ENABLE) {
data |= BIT0;
}
outb(data, 0xCD7);

98
src/southbridge/amd/cimx/sb900/late.c
View File

@@ -121,21 +121,21 @@ unsigned long acpi_fill_mcfg(unsigned long current)
}
static struct device_operations lpc_ops = {
.read_resources = lpc_read_resources,
.set_resources = lpc_set_resources,
.enable_resources = lpc_enable_resources,
.init = lpc_init,
.read_resources = lpc_read_resources,
.set_resources = lpc_set_resources,
.enable_resources = lpc_enable_resources,
.init = lpc_init,
#if IS_ENABLED(CONFIG_HAVE_ACPI_TABLES)
.write_acpi_tables = acpi_write_hpet,
#endif
.scan_bus = scan_lpc_bus,
.ops_pci = &lops_pci,
.scan_bus = scan_lpc_bus,
.ops_pci = &lops_pci,
};
static const struct pci_driver lpc_driver __pci_driver = {
.ops = &lpc_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_ATI_SB900_LPC,
.ops = &lpc_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_ATI_SB900_LPC,
};
@@ -239,18 +239,18 @@ static void azalia_init(struct device *dev)
}
static struct device_operations azalia_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = azalia_init,
.scan_bus = 0,
.ops_pci = &lops_pci,
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = azalia_init,
.scan_bus = 0,
.ops_pci = &lops_pci,
};
static const struct pci_driver azalia_driver __pci_driver = {
.ops = &azalia_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_ATI_SB900_HDA,
.ops = &azalia_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_ATI_SB900_HDA,
};
@@ -263,18 +263,18 @@ static void gec_init(struct device *dev)
}
static struct device_operations gec_ops = {
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = gec_init,
.scan_bus = 0,
.ops_pci = &lops_pci,
.read_resources = pci_dev_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_dev_enable_resources,
.init = gec_init,
.scan_bus = 0,
.ops_pci = &lops_pci,
};
static const struct pci_driver gec_driver __pci_driver = {
.ops = &gec_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_ATI_SB900_GEC,
.ops = &gec_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_ATI_SB900_GEC,
};
@@ -286,19 +286,19 @@ static void pcie_init(device_t dev)
}
static struct device_operations pci_ops = {
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_bus_enable_resources,
.init = pcie_init,
.scan_bus = pci_scan_bridge,
.reset_bus = pci_bus_reset,
.ops_pci = &lops_pci,
.read_resources = pci_bus_read_resources,
.set_resources = pci_dev_set_resources,
.enable_resources = pci_bus_enable_resources,
.init = pcie_init,
.scan_bus = pci_scan_bridge,
.reset_bus = pci_bus_reset,
.ops_pci = &lops_pci,
};
static const struct pci_driver pci_driver __pci_driver = {
.ops = &pci_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_ATI_SB900_PCI,
.ops = &pci_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_ATI_SB900_PCI,
};
@@ -315,30 +315,30 @@ struct device_operations bridge_ops = {
/* 0:15:0 PCIe PortA */
static const struct pci_driver PORTA_driver __pci_driver = {
.ops = &bridge_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_ATI_SB900_PCIEA,
.ops = &bridge_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_ATI_SB900_PCIEA,
};
/* 0:15:1 PCIe PortB */
static const struct pci_driver PORTB_driver __pci_driver = {
.ops = &bridge_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_ATI_SB900_PCIEB,
.ops = &bridge_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_ATI_SB900_PCIEB,
};
/* 0:15:2 PCIe PortC */
static const struct pci_driver PORTC_driver __pci_driver = {
.ops = &bridge_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_ATI_SB900_PCIEC,
.ops = &bridge_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_ATI_SB900_PCIEC,
};
/* 0:15:3 PCIe PortD */
static const struct pci_driver PORTD_driver __pci_driver = {
.ops = &bridge_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_ATI_SB900_PCIED,
.ops = &bridge_ops,
.vendor = PCI_VENDOR_ID_AMD,
.device = PCI_DEVICE_ID_ATI_SB900_PCIED,
};

2
src/southbridge/amd/cimx/sb900/reset.c
View File

@@ -32,7 +32,7 @@ static inline void set_bios_reset(void)
int i;
nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
for(i = 0; i < nodes; i++) {
for (i = 0; i < nodes; i++) {
dev = NODE_PCI(i, 0);
htic = pci_read_config32(dev, HT_INIT_CONTROL);
htic &= ~HTIC_BIOSR_Detect;

8
src/southbridge/amd/cimx/sb900/smbus.c
View File

@@ -63,7 +63,7 @@ int do_smbus_recv_byte(u32 smbus_io_base, u32 device)
u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_recv_byte - smbus no ready.\n");
printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_recv_byte - smbus no ready.\n");
return -2; /* not ready */
}
@@ -93,7 +93,7 @@ int do_smbus_send_byte(u32 smbus_io_base, u32 device, u8 val)
u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_send_byte - smbus no ready.\n");
printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_send_byte - smbus no ready.\n");
return -2; /* not ready */
}
@@ -123,7 +123,7 @@ int do_smbus_read_byte(u32 smbus_io_base, u32 device, u32 address)
u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_read_byte - smbus no ready.\n");
printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_read_byte - smbus no ready.\n");
return -2; /* not ready */
}
@@ -156,7 +156,7 @@ int do_smbus_write_byte(u32 smbus_io_base, u32 device, u32 address, u8 val)
u8 byte;
if (smbus_wait_until_ready(smbus_io_base) < 0) {
printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_write_byte - smbus no ready.\n");
printk(BIOS_INFO, "SB900 - Smbus.c - do_smbus_write_byte - smbus no ready.\n");
return -2; /* not ready */
}

2
src/southbridge/amd/common/amd_pci_util.c
View File

@@ -58,7 +58,7 @@ void write_pci_int_table (void)
{
u8 byte;
if(picr_data_ptr == NULL || intr_data_ptr == NULL){
if (picr_data_ptr == NULL || intr_data_ptr == NULL){
printk(BIOS_ERR, "Warning: Can't write PCI_INTR 0xC00/0xC01 registers because\n"
"'mainboard_picr_data' or 'mainboard_intr_data' tables are NULL\n");
return;

4
src/southbridge/amd/cs5535/chipsetinit.c
View File

@@ -328,7 +328,7 @@ chipsetinit(void)
i = 0;
csi = &SB_MASTER_CONF_TABLE[i];
for(; csi->msrnum; csi++){
for (; csi->msrnum; csi++){
msr.lo = csi->msr.lo;
msr.hi = csi->msr.hi;
wrmsr(csi->msrnum, msr); // MSR - see table above
@@ -347,7 +347,7 @@ chipsetinit(void)
{
csi = CS5535_CLOCK_GATING_TABLE;
for(; csi->msrnum; csi++){
for (; csi->msrnum; csi++){
msr.lo = csi->msr.lo;
msr.hi = csi->msr.hi;
wrmsr(csi->msrnum, msr); // MSR - see table above

14
src/southbridge/amd/cs5535/cs5535.c
View File

@@ -56,9 +56,9 @@ static void dump_south(struct device *dev)
{
int i, j;
for(i=0; i<256; i+=16) {
for (i=0; i<256; i+=16) {
printk(BIOS_DEBUG, "0x%02x: ", i);
for(j=0; j<16; j++)
for (j=0; j<16; j++)
printk(BIOS_DEBUG, "%02x ", pci_read_config8(dev, i+j));
printk(BIOS_DEBUG, "\n");
}
@@ -103,9 +103,9 @@ static const struct pci_driver cs5535_pci_driver __pci_driver = {
};
struct chip_operations southbridge_amd_cs5535_ops = {
CHIP_NAME("AMD Geode CS5535 Southbridge")
/* This is only called when this device is listed in the
* static device tree.
*/
.enable_dev = southbridge_enable,
CHIP_NAME("AMD Geode CS5535 Southbridge")
/* This is only called when this device is listed in the
* static device tree.
*/
.enable_dev = southbridge_enable,
};

4
src/southbridge/amd/cs5535/early_setup.c
View File

@@ -34,7 +34,7 @@ static void cs5535_setup_idsel(void)
outl(0x1 << (CS5535_DEV_NUM + 10), 0);
}
static void cs5535_usb_swapsif(void)
static void cs5535_usb_swapsif (void)
{
msr_t msr;
@@ -133,7 +133,7 @@ static void cs5535_early_setup(void)
printk(BIOS_DEBUG, "Setup idsel\n");
cs5535_setup_idsel();
printk(BIOS_DEBUG, "Setup iobase\n");
cs5535_usb_swapsif();
cs5535_usb_swapsif ();
cs5535_setup_iobase();
printk(BIOS_DEBUG, "Setup gpio\n");
cs5535_setup_gpio();

4
src/southbridge/amd/cs5536/early_setup.c
View File

@@ -42,7 +42,7 @@ static void cs5536_setup_idsel(void)
outl(0x1 << (CS5536_DEV_NUM + 10), 0);
}
static void cs5536_usb_swapsif(void)
static void cs5536_usb_swapsif (void)
{
msr_t msr;
@@ -260,7 +260,7 @@ static void cs5536_early_setup(void)
//printk(BIOS_DEBUG, "Setup idsel\n");
cs5536_setup_idsel();
//printk(BIOS_DEBUG, "Setup iobase\n");
cs5536_usb_swapsif();
cs5536_usb_swapsif ();
cs5536_setup_iobase();
//printk(BIOS_DEBUG, "Setup gpio\n");
cs5536_setup_gpio();

4
src/southbridge/amd/pi/hudson/acpi/fch.asl
View File

@@ -165,9 +165,9 @@ Method(_INI, 0) {
Method(OSFL, 0){
if(LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
if (LNotEqual(OSVR, Ones)) {Return(OSVR)} /* OS version was already detected */
if(CondRefOf(\_OSI))
if (CondRefOf(\_OSI))
{
Store(1, OSVR) /* Assume some form of XP */
if (\_OSI("Windows 2006")) /* Vista */

62
src/southbridge/amd/rs690/gfx.c
View File

@@ -461,48 +461,48 @@ void rs690_gfx_init(device_t nb_dev, device_t dev, u32 port)
/* done by enable_pci_bar3() before */
/* step 6 SBIOS compile flags */
if (cfg->gfx_tmds) {
/* step 6.2.2 Clock-Muxing Control */
/* step 6.2.2.1 */
set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 16, 1 << 16);
if (cfg->gfx_tmds) {
/* step 6.2.2 Clock-Muxing Control */
/* step 6.2.2.1 */
set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 16, 1 << 16);
/* step 6.2.2.2 */
set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 8, 1 << 8);
set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 10, 1 << 10);
/* step 6.2.2.2 */
set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 8, 1 << 8);
set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 10, 1 << 10);
/* step 6.2.2.3 */
set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 26, 1 << 26);
/* step 6.2.2.3 */
set_nbmisc_enable_bits(nb_dev, 0x7, 1 << 26, 1 << 26);
/* step 6.2.3 Lane-Muxing Control */
/* step 6.2.3.1 */
set_nbmisc_enable_bits(nb_dev, 0x37, 0x3 << 8, 0x2 << 8);
/* step 6.2.3 Lane-Muxing Control */
/* step 6.2.3.1 */
set_nbmisc_enable_bits(nb_dev, 0x37, 0x3 << 8, 0x2 << 8);
/* step 6.2.4 Received Data Control */
/* step 6.2.4.1 */
set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 16, 0x2 << 16);
/* step 6.2.4 Received Data Control */
/* step 6.2.4.1 */
set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 16, 0x2 << 16);
/* step 6.2.4.2 */
set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 18, 0x3 << 18);
/* step 6.2.4.2 */
set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 18, 0x3 << 18);
/* step 6.2.4.3 */
set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 20, 0x0 << 20);
/* step 6.2.4.3 */
set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 20, 0x0 << 20);
/* step 6.2.4.4 */
set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 22, 0x1 << 22);
/* step 6.2.4.4 */
set_pcie_enable_bits(nb_dev, 0x40, 0x3 << 22, 0x1 << 22);
/* step 6.2.5 PLL Power Down Control */
/* step 6.2.5.1 */
set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 6, 0x0 << 6);
/* step 6.2.5 PLL Power Down Control */
/* step 6.2.5.1 */
set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 6, 0x0 << 6);
/* step 6.2.6 Driving Strength Control */
/* step 6.2.6.1 */
set_nbmisc_enable_bits(nb_dev, 0x34, 0x1 << 24, 0x0 << 24);
/* step 6.2.6 Driving Strength Control */
/* step 6.2.6.1 */
set_nbmisc_enable_bits(nb_dev, 0x34, 0x1 << 24, 0x0 << 24);
/* step 6.2.6.2 */
set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 2, 0x3 << 2);
}
/* step 6.2.6.2 */
set_nbmisc_enable_bits(nb_dev, 0x35, 0x3 << 2, 0x3 << 2);
}
printk(BIOS_INFO, "rs690_gfx_init step6.\n");
printk(BIOS_INFO, "rs690_gfx_init step6.\n");
/* step 7 compliance state, (only need if CMOS option is enabled) */
/* the compliance state is just for test. refer to 4.2.5.2 of PCIe specification */

8
src/southbridge/amd/rs690/ht.c
View File

@@ -52,12 +52,12 @@ static void ht_dev_set_resources(device_t dev)
printk(BIOS_DEBUG,"%s: %s[0x1C] base = %0llx limit = %0llx\n", __func__, dev_path(dev), rbase, rend);
k8_f1 = dev_find_slot(0,PCI_DEVFN(0x18,1));
// find a not assigned resource
for( reg = 0xb8; reg >= 0x80; reg -= 8 ) {
for ( reg = 0xb8; reg >= 0x80; reg -= 8 ) {
base = pci_read_config32(k8_f1,reg);
limit = pci_read_config32(k8_f1,reg+4);
if( !(base & 3) ) break; // found a not assigned resource
if ( !(base & 3) ) break; // found a not assigned resource
}
if( !(base & 3) ) {
if ( !(base & 3) ) {
u32 sblk;
device_t k8_f0 = dev_find_slot(0, PCI_DEVFN(0x18, 0));
/* Remember this resource has been stored. */
@@ -90,7 +90,7 @@ unsigned long acpi_fill_mcfg(unsigned long current)
device_t dev = dev_find_slot(0,PCI_DEVFN(0,0));
// we report mmconf base
res = probe_resource(dev, 0x1C);
if( res )
if ( res )
mmconf_base = res->base;
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, mmconf_base, 0x0, 0x0, 0x1f); // Fix me: should i reserve 255 busses ?

2
src/southbridge/amd/rs690/pcie.c
View File

@@ -84,7 +84,7 @@ static void PciePowerOffGppPorts(device_t nb_dev, device_t dev, u32 port)
PCIE_GFX_COMPLIANCE))) {
}
if (!cfg->gfx_tmds){
if (!cfg->gfx_tmds){
/* step 3 Power Down Control for Southbridge */
reg = nbpcie_p_read_index(dev, 0xa2);

4
src/southbridge/amd/rs780/early_setup.c
View File

@@ -335,7 +335,7 @@ static void k8_optimization(void)
wrmsr(0xC001001F, msr);
}
#else
#define k8_optimization() do{}while(0)
#define k8_optimization() do {} while (0)
#endif /* !CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */
#if CONFIG_NORTHBRIDGE_AMD_AMDFAM10
@@ -400,7 +400,7 @@ static void fam10_optimization(void)
}
}
#else
#define fam10_optimization() do{}while(0)
#define fam10_optimization() do {} while (0)
#endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 */
/*****************************************

121
src/southbridge/amd/rs780/gfx.c
View File

@@ -127,12 +127,10 @@ static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO)
{
int i;
MMIORANGE * TempRange;
for(i=0; i<8; i++)
{
if(pMMIO[i].Attribute != Attribute && Base >= pMMIO[i].Base && Limit <= pMMIO[i].Limit)
{
for (i=0; i<8; i++) {
if (pMMIO[i].Attribute != Attribute && Base >= pMMIO[i].Base && Limit <= pMMIO[i].Limit) {
TempRange = AllocMMIO(pMMIO);
if(TempRange == 0) return 0x80000000;
if (TempRange == 0) return 0x80000000;
TempRange->Base = Limit;
TempRange->Limit = pMMIO[i].Limit;
TempRange->Attribute = pMMIO[i].Attribute;
@@ -140,7 +138,7 @@ static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO)
}
}
TempRange = AllocMMIO(pMMIO);
if(TempRange == 0) return 0x80000000;
if (TempRange == 0) return 0x80000000;
TempRange->Base = Base;
TempRange->Limit = Limit;
TempRange->Attribute = Attribute;
@@ -150,32 +148,25 @@ static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO)
static u8 FinalizeMMIO(MMIORANGE *pMMIO)
{
int i, j, n = 0;
for(i=0; i<8; i++)
{
if (pMMIO[i].Base == pMMIO[i].Limit)
{
for (i=0; i<8; i++) {
if (pMMIO[i].Base == pMMIO[i].Limit) {
FreeMMIO(&pMMIO[i]);
continue;
}
for(j=0; j<i; j++)
{
if (i!=j && pMMIO[i].Attribute == pMMIO[j].Attribute)
{
if (pMMIO[i].Base == pMMIO[j].Limit)
{
for (j=0; j<i; j++) {
if (i!=j && pMMIO[i].Attribute == pMMIO[j].Attribute) {
if (pMMIO[i].Base == pMMIO[j].Limit) {
pMMIO[j].Limit = pMMIO[i].Limit;
FreeMMIO(&pMMIO[i]);
}
if (pMMIO[i].Limit == pMMIO[j].Base)
{
if (pMMIO[i].Limit == pMMIO[j].Base) {
pMMIO[j].Base = pMMIO[i].Base;
FreeMMIO(&pMMIO[i]);
}
}
}
}
for (i=0; i<8; i++)
{
for (i=0; i<8; i++) {
if (pMMIO[i].Limit != 0) n++;
}
return n;
@@ -191,29 +182,23 @@ static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
Value = pci_read_config32(dev0x14, 0x18);
BusStart = (Value >> 8) & 0xFF;
BusEnd = (Value >> 16) & 0xFF;
for(Bus = BusStart; Bus <= BusEnd; Bus++)
{
for(Dev = 0; Dev <= 0x1f; Dev++)
{
for (Bus = BusStart; Bus <= BusEnd; Bus++) {
for (Dev = 0; Dev <= 0x1f; Dev++) {
tempdev = dev_find_slot(Bus, Dev << 3);
Value = pci_read_config32(tempdev, 0);
printk(BIOS_DEBUG, "Dev ID %x\n", Value);
if((Value & 0xffff) == 0x1102)
{//Creative
if ((Value & 0xffff) == 0x1102) {//Creative
//Found Creative SB
u32 MMIOStart = 0xffffffff;
u32 MMIOLimit = 0;
for(Reg = 0x10; Reg < 0x20; Reg+=4)
{
for (Reg = 0x10; Reg < 0x20; Reg+=4) {
u32 BaseA, LimitA;
BaseA = pci_read_config32(tempdev, Reg);
Value = BaseA;
if(!(Value & 0x01))
{
if (!(Value & 0x01)) {
Value = Value & 0xffffff00;
if(Value != 0)
{
if(MMIOStart > Value)
if (Value != 0) {
if (MMIOStart > Value)
MMIOStart = Value;
LimitA = 0xffffffff;
//WritePCI(PciAddress,AccWidthUint32,&LimitA);
@@ -232,16 +217,14 @@ static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
if (MMIOStart < MMIOLimit)
{
Status = SetMMIO(MMIOStart>>8, MMIOLimit>>8, 0x80, pMMIO);
if(Status == CIM_ERROR) return Status;
if (Status == CIM_ERROR) return Status;
}
}
}
}
if(Status == CIM_SUCCESS)
{
if (Status == CIM_SUCCESS) {
//Lets optimize MMIO
if(FinalizeMMIO(pMMIO) > 4)
{
if (FinalizeMMIO(pMMIO) > 4) {
Status = CIM_ERROR;
}
}
@@ -256,23 +239,18 @@ static void ProgramMMIO(MMIORANGE *pMMIO, u8 LinkID, u8 Attribute)
k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
for(i = 0; i < 8; i++)
{
for (i = 0; i < 8; i++) {
int k = 0, MmioReg;
u32 Base = 0;
u32 Limit = 0;
for(j = 0; j < 8; j++)
{
if (Base < pMMIO[j].Base)
{
for (j = 0; j < 8; j++) {
if (Base < pMMIO[j].Base) {
Base = pMMIO[j].Base;
k = j;
}
}
if(pMMIO[k].Limit != 0)
{
if(Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0 )
{
if (pMMIO[k].Limit != 0) {
if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0 ) {
Base = 0;
}
else
@@ -366,8 +344,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
/* Clear vgainfo. */
bpointer = (unsigned char *) &vgainfo;
for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i++)
{
for (i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i++) {
*bpointer = 0;
bpointer++;
}
@@ -651,8 +628,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
/* Transfer the Table to VBIOS. */
pointer = (u32 *)&vgainfo;
for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4)
{
for (i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4) {
#if CONFIG_GFXUMA
*GpuF0MMReg = 0x80000000 + uma_memory_size - 512 + i;
#else
@@ -686,14 +662,12 @@ static void internal_gfx_pci_dev_init(struct device *dev)
/* clear MMIO and CreativeMMIO. */
bpointer = (unsigned char *)MMIO;
for(i=0; i<sizeof(MMIO); i++)
{
for (i=0; i<sizeof(MMIO); i++) {
*bpointer = 0;
bpointer++;
}
bpointer = (unsigned char *)CreativeMMIO;
for(i=0; i<sizeof(CreativeMMIO); i++)
{
for (i=0; i<sizeof(CreativeMMIO); i++) {
*bpointer = 0;
bpointer++;
}
@@ -708,20 +682,18 @@ static void internal_gfx_pci_dev_init(struct device *dev)
temp = pci_read_config32(dev0x14, 0x20);
Base32 = (temp & 0x0fff0) << 8;
Limit32 = ((temp & 0x0fff00000) + 0x100000) >> 8;
if(Base32 < Limit32)
{
if (Base32 < Limit32) {
Status = GetCreativeMMIO(&CreativeMMIO[0]);
if(Status != CIM_ERROR)
if (Status != CIM_ERROR)
SetMMIO(Base32, Limit32, 0x0, &MMIO[0]);
}
/* Set MMIO for prefetchable P2P. */
if(Status != CIM_ERROR)
{
if (Status != CIM_ERROR) {
temp = pci_read_config32(dev0x14, 0x24);
Base32 = (temp & 0x0fff0) <<8;
Limit32 = ((temp & 0x0fff00000) + 0x100000) >> 8;
if(Base32 < Limit32)
if (Base32 < Limit32)
SetMMIO(Base32, Limit32, 0x0, &MMIO[0]);
}
@@ -835,8 +807,7 @@ static void rs780_internal_gfx_enable(device_t dev)
device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
device_t k8_f4 = dev_find_slot(0, PCI_DEVFN(0x18, 4));
for (i = 0; i < 12; i++)
{
for (i = 0; i < 12; i++) {
l_dword = pci_read_config32(k8_f2, 0x40 + i * 4);
nbmc_write_index(nb_dev, 0x30 + i, l_dword);
}
@@ -848,10 +819,8 @@ static void rs780_internal_gfx_enable(device_t dev)
set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<< 8))<<17);
l_dword = pci_read_config32(k8_f2, 0x90);
set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<<10))<<18);
if (is_family10h())
{
for (i = 0; i < 12; i++)
{
if (is_family10h()) {
for (i = 0; i < 12; i++) {
l_dword = pci_read_config32(k8_f2, 0x140 + i * 4);
nbmc_write_index(nb_dev, 0x3d + i, l_dword);
}
@@ -974,13 +943,11 @@ static void rs780_internal_gfx_enable(device_t dev)
/* set_nbmc_enable_bits(nb_dev, 0xac, ~(0xfffffff0), 0x0b); */
/* Init PM timing. */
for(i=0; i<4; i++)
{
for (i=0; i<4; i++) {
l_dword = nbmc_read_index(nb_dev, 0xa0+i);
nbmc_write_index(nb_dev, 0xc8+i, l_dword);
}
for(i=0; i<4; i++)
{
for (i=0; i<4; i++) {
l_dword = nbmc_read_index(nb_dev, 0xa8+i);
nbmc_write_index(nb_dev, 0xcc+i, l_dword);
}
@@ -1538,7 +1505,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3);
if((dev->path.pci.devfn >> 3) == 2) {
if ((dev->path.pci.devfn >> 3) == 2) {
single_port_configuration(nb_dev, dev);
} else {
set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */
@@ -1565,7 +1532,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
break;
case 2:
if(is_dev3_present()){
if (is_dev3_present()) {
/* step 1, lane reversal (only need if CMOS option is enabled) */
if (cfg->gfx_lane_reversal) {
set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
@@ -1583,7 +1550,7 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
printk(BIOS_DEBUG, "device = %x\n", dev->path.pci.devfn >> 3);
dual_port_configuration(nb_dev, dev);
}else{
} else {
if (cfg->gfx_lane_reversal) {
set_nbmisc_enable_bits(nb_dev, 0x36, 1 << 31, 1 << 31);
set_nbmisc_enable_bits(nb_dev, 0x33, 1 << 2, 1 << 2);
@@ -1591,9 +1558,9 @@ void rs780_gfx_init(device_t nb_dev, device_t dev, u32 port)
}
printk(BIOS_DEBUG, "rs780_gfx_init step1.\n");
if((dev->path.pci.devfn >> 3) == 2)
if ((dev->path.pci.devfn >> 3) == 2)
single_port_configuration(nb_dev, dev);
else{
else {
set_nbmisc_enable_bits(nb_dev, 0xc, 0, 0x2 << 2); /* hide the GFX bridge. */
printk(BIOS_DEBUG, "If dev3.., single port. Do nothing.\n");
}

2
src/southbridge/amd/rs780/rs780.h
View File

@@ -101,7 +101,7 @@ typedef struct _ATOM_INTEGRATED_SYSTEM_INFO_V2
ULONG ulDockingPinCFGInfo;
ULONG ulCPUCapInfo;
USHORT usNumberOfCyclesInPeriod; //usNumberOfCyclesInPeriod[15] = 0 - invert waveform
// 1 - non inverted waveform
// 1 - non inverted waveform
USHORT usMaxNBVoltage;
USHORT usMinNBVoltage;
USHORT usBootUpNBVoltage;

2
src/southbridge/amd/sb600/early_setup.c
View File

@@ -137,7 +137,7 @@ static void enable_fid_change_on_sb(u32 sbbusn, u32 sbdn)
pmio_write(0x8b, 0x01);
pmio_write(0x8a, 0x90);
if(get_sb600_revision() > 0x13)
if (get_sb600_revision() > 0x13)
pmio_write(0x88, 0x10);
else
pmio_write(0x88, 0x06);

4
src/southbridge/amd/sb600/hda.c
View File

@@ -175,7 +175,7 @@ static int wait_for_ready(void *base)
int timeout = 50;
while(timeout--) {
while (timeout--) {
u32 dword=read32(base + HDA_ICII_REG);
if (!(dword & HDA_ICII_BUSY))
return 0;
@@ -196,7 +196,7 @@ static int wait_for_valid(void *base)
* same duration */
int timeout = 50;
while(timeout--) {
while (timeout--) {
u32 dword = read32(base + HDA_ICII_REG);
if ((dword & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)

2
src/southbridge/amd/sb600/sata.c
View File

@@ -182,7 +182,7 @@ static void sata_init(struct device *dev)
printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
byte &= 0xF;
if( byte == 0x1 ) {
if ( byte == 0x1 ) {
/* If the drive status is 0x1 then we see it but we aren't talking to it. */
/* Try to do something about it. */
printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n");

10
src/southbridge/amd/sb700/Kconfig
View File

@@ -25,16 +25,6 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy
select HAVE_HARD_RESET
select SMBUS_HAS_AUX_CHANNELS
config SOUTHBRIDGE_AMD_SB700_33MHZ_SPI
bool "Enable high speed SPI clock"
default n
help
When set, the SPI clock will run at 33MHz instead
of the compatibility mode 16.5MHz. Note that not
all ROMs are capable of 33MHz operation, so you
will need to verify this option is appropriate for
the ROM you are using.
# Set for southbridge SP5100 which also uses SB700 driver
config SOUTHBRIDGE_AMD_SUBTYPE_SP5100
bool

34
src/southbridge/amd/sb700/bootblock.c
View File

@@ -20,10 +20,6 @@
#define IO_MEM_PORT_DECODE_ENABLE_5 0x48
#define IO_MEM_PORT_DECODE_ENABLE_6 0x4a
#define SPI_BASE_ADDRESS 0xa0
#define SPI_CONTROL_1 0xc
#define TEMPORARY_SPI_BASE_ADDRESS 0xfec10000
/*
* Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
@@ -96,37 +92,7 @@ static void sb700_enable_rom(void)
pci_io_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_6, reg8);
}
static void sb700_configure_rom(void)
{
pci_devfn_t dev;
uint32_t dword;
dev = PCI_DEV(0, 0x14, 3);
if (IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_33MHZ_SPI)) {
uint32_t prev_spi_cfg;
volatile uint32_t *spi_mmio;
/* Temporarily set up SPI access to change SPI speed */
prev_spi_cfg = dword = pci_io_read_config32(dev, SPI_BASE_ADDRESS);
dword &= ~(0x7ffffff << 5); /* SPI_BaseAddr */
dword |= TEMPORARY_SPI_BASE_ADDRESS & (0x7ffffff << 5);
dword |= (0x1 << 1); /* SpiRomEnable = 1 */
pci_io_write_config32(dev, SPI_BASE_ADDRESS, dword);
spi_mmio = (void *)(TEMPORARY_SPI_BASE_ADDRESS + SPI_CONTROL_1);
dword = *spi_mmio;
dword &= ~(0x3 << 12); /* NormSpeed = 0x1 */
dword |= (0x1 << 12);
*spi_mmio = dword;
/* Restore previous SPI access */
pci_io_write_config32(dev, SPI_BASE_ADDRESS, prev_spi_cfg);
}
}
static void bootblock_southbridge_init(void)
{
sb700_enable_rom();
sb700_configure_rom();
}

4
src/southbridge/amd/sb700/hda.c
View File

@@ -97,7 +97,7 @@ static int wait_for_ready(void *base)
int timeout = 50;
while(timeout--) {
while (timeout--) {
u32 dword=read32(base + HDA_ICII_REG);
if (!(dword & HDA_ICII_BUSY))
return 0;
@@ -118,7 +118,7 @@ static int wait_for_valid(void *base)
* same duration */
int timeout = 50;
while(timeout--) {
while (timeout--) {
u32 dword = read32(base + HDA_ICII_REG);
if ((dword & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)

2
src/southbridge/amd/sb700/reset.c
View File

@@ -36,7 +36,7 @@ static void set_bios_reset(void)
int i;
nodes = ((pci_read_config32(PCI_DEV(CONFIG_CBB, CONFIG_CDB, 0), 0x60) >> 4) & 7) + 1;
for(i = 0; i < nodes; i++) {
for (i = 0; i < nodes; i++) {
dev = NODE_PCI(i, 0);
htic = pci_read_config32(dev, HT_INIT_CONTROL);
htic &= ~HTIC_BIOSR_Detect;

24
src/southbridge/amd/sb700/sm.c
View File

@@ -213,7 +213,7 @@ static void sm_init(device_t dev)
}
/*rpr v2.13 2.22 SMBUS PCI Config */
byte = pci_read_config8(dev, 0xE1);
byte = pci_read_config8(dev, 0xE1);
if ((REV_SB700_A11 == rev) || REV_SB700_A12 == rev) {
byte |= 1 << 0;
}
@@ -222,7 +222,7 @@ static void sm_init(device_t dev)
*/
//byte |= 1 << 2 | 1 << 3 | 1 << 4;
byte |= 1 << 3 | 1 << 4;
pci_write_config8(dev, 0xE1, byte);
pci_write_config8(dev, 0xE1, byte);
/* 2.5 Enabling Non-Posted Memory Write */
axindxc_reg(0x10, 1 << 9, 1 << 9);
@@ -278,7 +278,7 @@ static void sm_init(device_t dev)
u16 word;
/* rpr v2.13 4.18 Enabling Posted Pass Non-Posted Downstream */
axindxc_reg(0x02, 1 << 9, 1 << 9);
axindxc_reg(0x02, 1 << 9, 1 << 9);
abcfg_reg(0x9C, 0x00007CC0, 0x00007CC0);
abcfg_reg(0x1009C, 0x00000030, 0x00000030);
abcfg_reg(0x10090, 0x00001E00, 0x00001E00);
@@ -287,19 +287,19 @@ static void sm_init(device_t dev)
abcfg_reg(0x58, 0x0000F800, 0x0000E800);
/* rpr v2.13 4.20 64 bit Non-Posted Memory Write Support */
axindxc_reg(0x02, 1 << 10, 1 << 10);
axindxc_reg(0x02, 1 << 10, 1 << 10);
/* rpr v2.13 2.38 Unconditional Shutdown */
byte = pci_read_config8(dev, 0x43);
byte = pci_read_config8(dev, 0x43);
byte &= ~(1 << 3);
pci_write_config8(dev, 0x43, byte);
pci_write_config8(dev, 0x43, byte);
word = pci_read_config16(dev, 0x38);
word |= 1 << 12;
pci_write_config16(dev, 0x38, word);
pci_write_config16(dev, 0x38, word);
byte |= 1 << 3;
pci_write_config8(dev, 0x43, byte);
pci_write_config8(dev, 0x43, byte);
/* Enable southbridge MMIO decode */
dword = pci_read_config32(dev, SB_MMIO_CFG_REG);
@@ -308,12 +308,12 @@ static void sm_init(device_t dev)
dword |= 0x1;
pci_write_config32(dev, SB_MMIO_CFG_REG, dword);
}
byte = pci_read_config8(dev, 0xAE);
if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID))
byte |= 1 << 4;
byte = pci_read_config8(dev, 0xAE);
if (IS_ENABLED(CONFIG_ENABLE_APIC_EXT_ID))
byte |= 1 << 4;
byte |= 1 << 5; /* ACPI_DISABLE_TIMER_IRQ_ENHANCEMENT_FOR_8254_TIMER */
byte |= 1 << 6; /* Enable arbiter between APIC and PIC interrupts */
pci_write_config8(dev, 0xAE, byte);
pci_write_config8(dev, 0xAE, byte);
/* 4.11:Programming Cycle Delay for AB and BIF Clock Gating */
/* 4.12: Enabling AB and BIF Clock Gating */

4
src/southbridge/amd/sb800/hda.c
View File

@@ -99,7 +99,7 @@ static int wait_for_ready(void *base)
int timeout = 50;
while(timeout--) {
while (timeout--) {
u32 dword=read32(base + HDA_ICII_REG);
if (!(dword & HDA_ICII_BUSY))
return 0;
@@ -120,7 +120,7 @@ static int wait_for_valid(void *base)
* same duration */
int timeout = 50;
while(timeout--) {
while (timeout--) {
u32 dword = read32(base + HDA_ICII_REG);
if ((dword & (HDA_ICII_VALID | HDA_ICII_BUSY)) ==
HDA_ICII_VALID)

2
src/southbridge/amd/sb800/sata.c
View File

@@ -177,7 +177,7 @@ static void sata_init(struct device *dev)
byte = read8(sata_bar5 + 0x128 + 0x80 * i);
printk(BIOS_SPEW, "SATA port %i status = %x\n", i, byte);
byte &= 0xF;
if( byte == 0x1 ) {
if ( byte == 0x1 ) {
/* If the drive status is 0x1 then we see it but we aren't talking to it. */
/* Try to do something about it. */
printk(BIOS_SPEW, "SATA device detected but not talking. Trying lower speed.\n");

28
src/southbridge/amd/sr5650/early_setup.c
View File

@@ -30,22 +30,22 @@
*/
static void alink_ax_indx(u32 space, u32 axindc, u32 mask, u32 val)
{
u32 tmp;
u32 tmp;
/* read axindc to tmp */
outl(space << 30 | space << 3 | 0x30, AB_INDX);
outl(axindc, AB_DATA);
outl(space << 30 | space << 3 | 0x34, AB_INDX);
tmp = inl(AB_DATA);
/* read axindc to tmp */
outl(space << 30 | space << 3 | 0x30, AB_INDX);
outl(axindc, AB_DATA);
outl(space << 30 | space << 3 | 0x34, AB_INDX);
tmp = inl(AB_DATA);
tmp &= ~mask;
tmp |= val;
tmp &= ~mask;
tmp |= val;
/* write tmp */
outl(space << 30 | space << 3 | 0x30, AB_INDX);
outl(axindc, AB_DATA);
outl(space << 30 | space << 3 | 0x34, AB_INDX);
outl(tmp, AB_DATA);
/* write tmp */
outl(space << 30 | space << 3 | 0x30, AB_INDX);
outl(axindc, AB_DATA);
outl(space << 30 | space << 3 | 0x34, AB_INDX);
outl(tmp, AB_DATA);
}
@@ -327,7 +327,7 @@ void fam10_optimization(void)
/* rpr Table 5-11, 5-12 */
}
#else
#define fam10_optimization() do{}while(0)
#define fam10_optimization() do {} while (0)
#endif /* CONFIG_NORTHBRIDGE_AMD_AMDFAM10 || CONFIG_NORTHBRIDGE_AMD_AGESA_FAMILY10 */
/*****************************************

4
src/southbridge/amd/sr5650/sr5650.c
View File

@@ -817,8 +817,8 @@ unsigned long acpi_fill_mcfg(unsigned long current)
resource_t mmconf_base = EXT_CONF_BASE_ADDRESS;
if (IS_ENABLED(CONFIG_EXT_CONF_SUPPORT)) {
res = sr5650_retrieve_cpu_mmio_resource();
if (res)
res = sr5650_retrieve_cpu_mmio_resource();
if (res)
mmconf_base = res->base;
current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, mmconf_base, 0x0, 0x0, 0x1f);