sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

src/southbridge: Code formating

Browse Source 
Change-Id: Icfc35b73bacb60b1f21e71e70ad4418ec3e644f6
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16291
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
This commit is contained in:
Elyes HAOUAS
2016-08-31 19:22:16 +02:00
committed by Martin Roth
parent 2e4d80687d
commit ba28e8d73b
130 changed files with 1484 additions and 1589 deletions
Download Patch File Download Diff File Expand all files Collapse all files

3
src/southbridge/amd/amd8131/bridge.c
View File

@ -19,8 +19,7 @@ static void amd8131_walk_children(struct bus *bus,
void (*visit)(device_t dev, void *ptr), void *ptr)
{
device_t child;
for(child = bus->children; child; child = child->sibling)
{
for (child = bus->children; child; child = child->sibling) {
if (child->path.type != DEVICE_PATH_PCI) {
continue;
}

3
src/southbridge/amd/amd8132/bridge.c
View File

@ -32,8 +32,7 @@ static void amd8132_walk_children(struct bus *bus,
void (*visit)(device_t dev, void *ptr), void *ptr)
{
device_t child;
for(child = bus->children; child; child = child->sibling)
{
for (child = bus->children; child; child = child->sibling) {
if (child->path.type != DEVICE_PATH_PCI) {
continue;
}

99
src/southbridge/amd/rs780/gfx.c
View File

@ -127,10 +127,8 @@ static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO)
{
int i;
MMIORANGE * TempRange;
for(i=0; i<8; i++)
{
if(pMMIO[i].Attribute != Attribute && Base >= pMMIO[i].Base && Limit <= pMMIO[i].Limit)
{
for (i=0; i<8; i++) {
if (pMMIO[i].Attribute != Attribute && Base >= pMMIO[i].Base && Limit <= pMMIO[i].Limit) {
TempRange = AllocMMIO(pMMIO);
if (TempRange == 0) return 0x80000000;
TempRange->Base = Limit;
@ -150,32 +148,25 @@ static u32 SetMMIO(u32 Base, u32 Limit, u8 Attribute, MMIORANGE *pMMIO)
static u8 FinalizeMMIO(MMIORANGE *pMMIO)
{
int i, j, n = 0;
for(i=0; i<8; i++)
{
if (pMMIO[i].Base == pMMIO[i].Limit)
{
for (i=0; i<8; i++) {
if (pMMIO[i].Base == pMMIO[i].Limit) {
FreeMMIO(&pMMIO[i]);
continue;
}
for(j=0; j<i; j++)
{
if (i!=j && pMMIO[i].Attribute == pMMIO[j].Attribute)
{
if (pMMIO[i].Base == pMMIO[j].Limit)
{
for (j=0; j<i; j++) {
if (i!=j && pMMIO[i].Attribute == pMMIO[j].Attribute) {
if (pMMIO[i].Base == pMMIO[j].Limit) {
pMMIO[j].Limit = pMMIO[i].Limit;
FreeMMIO(&pMMIO[i]);
}
if (pMMIO[i].Limit == pMMIO[j].Base)
{
if (pMMIO[i].Limit == pMMIO[j].Base) {
pMMIO[j].Base = pMMIO[i].Base;
FreeMMIO(&pMMIO[i]);
}
}
}
}
for (i=0; i<8; i++)
{
for (i=0; i<8; i++) {
if (pMMIO[i].Limit != 0) n++;
}
return n;
@ -191,28 +182,22 @@ static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
Value = pci_read_config32(dev0x14, 0x18);
BusStart = (Value >> 8) & 0xFF;
BusEnd = (Value >> 16) & 0xFF;
for(Bus = BusStart; Bus <= BusEnd; Bus++)
{
for(Dev = 0; Dev <= 0x1f; Dev++)
{
for (Bus = BusStart; Bus <= BusEnd; Bus++) {
for (Dev = 0; Dev <= 0x1f; Dev++) {
tempdev = dev_find_slot(Bus, Dev << 3);
Value = pci_read_config32(tempdev, 0);
printk(BIOS_DEBUG, "Dev ID %x\n", Value);
if((Value & 0xffff) == 0x1102)
{//Creative
if ((Value & 0xffff) == 0x1102) {//Creative
//Found Creative SB
u32 MMIOStart = 0xffffffff;
u32 MMIOLimit = 0;
for(Reg = 0x10; Reg < 0x20; Reg+=4)
{
for (Reg = 0x10; Reg < 0x20; Reg+=4) {
u32 BaseA, LimitA;
BaseA = pci_read_config32(tempdev, Reg);
Value = BaseA;
if(!(Value & 0x01))
{
if (!(Value & 0x01)) {
Value = Value & 0xffffff00;
if(Value != 0)
{
if (Value != 0) {
if (MMIOStart > Value)
MMIOStart = Value;
LimitA = 0xffffffff;
@ -237,11 +222,9 @@ static CIM_STATUS GetCreativeMMIO(MMIORANGE *pMMIO)
}
}
}
if(Status == CIM_SUCCESS)
{
if (Status == CIM_SUCCESS) {
//Lets optimize MMIO
if(FinalizeMMIO(pMMIO) > 4)
{
if (FinalizeMMIO(pMMIO) > 4) {
Status = CIM_ERROR;
}
}
@ -256,23 +239,18 @@ static void ProgramMMIO(MMIORANGE *pMMIO, u8 LinkID, u8 Attribute)
k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
for(i = 0; i < 8; i++)
{
for (i = 0; i < 8; i++) {
int k = 0, MmioReg;
u32 Base = 0;
u32 Limit = 0;
for(j = 0; j < 8; j++)
{
if (Base < pMMIO[j].Base)
{
for (j = 0; j < 8; j++) {
if (Base < pMMIO[j].Base) {
Base = pMMIO[j].Base;
k = j;
}
}
if(pMMIO[k].Limit != 0)
{
if(Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0 )
{
if (pMMIO[k].Limit != 0) {
if (Attribute & MMIO_ATTRIB_NP_ONLY && pMMIO[k].Attribute == 0 ) {
Base = 0;
}
else
@ -366,8 +344,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
/* Clear vgainfo. */
bpointer = (unsigned char *) &vgainfo;
for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i++)
{
for (i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i++) {
*bpointer = 0;
bpointer++;
}
@ -651,8 +628,7 @@ static void internal_gfx_pci_dev_init(struct device *dev)
/* Transfer the Table to VBIOS. */
pointer = (u32 *)&vgainfo;
for(i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4)
{
for (i=0; i<sizeof(ATOM_INTEGRATED_SYSTEM_INFO_V2); i+=4) {
#if CONFIG_GFXUMA
*GpuF0MMReg = 0x80000000 + uma_memory_size - 512 + i;
#else
@ -686,14 +662,12 @@ static void internal_gfx_pci_dev_init(struct device *dev)
/* clear MMIO and CreativeMMIO. */
bpointer = (unsigned char *)MMIO;
for(i=0; i<sizeof(MMIO); i++)
{
for (i=0; i<sizeof(MMIO); i++) {
*bpointer = 0;
bpointer++;
}
bpointer = (unsigned char *)CreativeMMIO;
for(i=0; i<sizeof(CreativeMMIO); i++)
{
for (i=0; i<sizeof(CreativeMMIO); i++) {
*bpointer = 0;
bpointer++;
}
@ -708,15 +682,13 @@ static void internal_gfx_pci_dev_init(struct device *dev)
temp = pci_read_config32(dev0x14, 0x20);
Base32 = (temp & 0x0fff0) << 8;
Limit32 = ((temp & 0x0fff00000) + 0x100000) >> 8;
if(Base32 < Limit32)
{
if (Base32 < Limit32) {
Status = GetCreativeMMIO(&CreativeMMIO[0]);
if (Status != CIM_ERROR)
SetMMIO(Base32, Limit32, 0x0, &MMIO[0]);
}
/* Set MMIO for prefetchable P2P. */
if(Status != CIM_ERROR)
{
if (Status != CIM_ERROR) {
temp = pci_read_config32(dev0x14, 0x24);
Base32 = (temp & 0x0fff0) <<8;
@ -835,8 +807,7 @@ static void rs780_internal_gfx_enable(device_t dev)
device_t k8_f1 = dev_find_slot(0, PCI_DEVFN(0x18, 1));
device_t k8_f2 = dev_find_slot(0, PCI_DEVFN(0x18, 2));
device_t k8_f4 = dev_find_slot(0, PCI_DEVFN(0x18, 4));
for (i = 0; i < 12; i++)
{
for (i = 0; i < 12; i++) {
l_dword = pci_read_config32(k8_f2, 0x40 + i * 4);
nbmc_write_index(nb_dev, 0x30 + i, l_dword);
}
@ -848,10 +819,8 @@ static void rs780_internal_gfx_enable(device_t dev)
set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<< 8))<<17);
l_dword = pci_read_config32(k8_f2, 0x90);
set_nbmc_enable_bits(nb_dev, 0x3c, 0, !!(l_dword & (1<<10))<<18);
if (is_family10h())
{
for (i = 0; i < 12; i++)
{
if (is_family10h()) {
for (i = 0; i < 12; i++) {
l_dword = pci_read_config32(k8_f2, 0x140 + i * 4);
nbmc_write_index(nb_dev, 0x3d + i, l_dword);
}
@ -974,13 +943,11 @@ static void rs780_internal_gfx_enable(device_t dev)
/* set_nbmc_enable_bits(nb_dev, 0xac, ~(0xfffffff0), 0x0b); */
/* Init PM timing. */
for(i=0; i<4; i++)
{
for (i=0; i<4; i++) {
l_dword = nbmc_read_index(nb_dev, 0xa0+i);
nbmc_write_index(nb_dev, 0xc8+i, l_dword);
}
for(i=0; i<4; i++)
{
for (i=0; i<4; i++) {
l_dword = nbmc_read_index(nb_dev, 0xa8+i);
nbmc_write_index(nb_dev, 0xcc+i, l_dword);
}

10
src/southbridge/amd/sb700/Kconfig
View File

@ -25,16 +25,6 @@ config SOUTHBRIDGE_SPECIFIC_OPTIONS # dummy
select HAVE_HARD_RESET
select SMBUS_HAS_AUX_CHANNELS
config SOUTHBRIDGE_AMD_SB700_33MHZ_SPI
bool "Enable high speed SPI clock"
default n
help
When set, the SPI clock will run at 33MHz instead
of the compatibility mode 16.5MHz. Note that not
all ROMs are capable of 33MHz operation, so you
will need to verify this option is appropriate for
the ROM you are using.
# Set for southbridge SP5100 which also uses SB700 driver
config SOUTHBRIDGE_AMD_SUBTYPE_SP5100
bool

34
src/southbridge/amd/sb700/bootblock.c
View File

@ -20,10 +20,6 @@
#define IO_MEM_PORT_DECODE_ENABLE_5 0x48
#define IO_MEM_PORT_DECODE_ENABLE_6 0x4a
#define SPI_BASE_ADDRESS 0xa0
#define SPI_CONTROL_1 0xc
#define TEMPORARY_SPI_BASE_ADDRESS 0xfec10000
/*
* Enable 4MB (LPC) ROM access at 0xFFC00000 - 0xFFFFFFFF.
@ -96,37 +92,7 @@ static void sb700_enable_rom(void)
pci_io_write_config8(dev, IO_MEM_PORT_DECODE_ENABLE_6, reg8);
}
static void sb700_configure_rom(void)
{
pci_devfn_t dev;
uint32_t dword;
dev = PCI_DEV(0, 0x14, 3);
if (IS_ENABLED(CONFIG_SOUTHBRIDGE_AMD_SB700_33MHZ_SPI)) {
uint32_t prev_spi_cfg;
volatile uint32_t *spi_mmio;
/* Temporarily set up SPI access to change SPI speed */
prev_spi_cfg = dword = pci_io_read_config32(dev, SPI_BASE_ADDRESS);
dword &= ~(0x7ffffff << 5); /* SPI_BaseAddr */
dword |= TEMPORARY_SPI_BASE_ADDRESS & (0x7ffffff << 5);
dword |= (0x1 << 1); /* SpiRomEnable = 1 */
pci_io_write_config32(dev, SPI_BASE_ADDRESS, dword);
spi_mmio = (void *)(TEMPORARY_SPI_BASE_ADDRESS + SPI_CONTROL_1);
dword = *spi_mmio;
dword &= ~(0x3 << 12); /* NormSpeed = 0x1 */
dword |= (0x1 << 12);
*spi_mmio = dword;
/* Restore previous SPI access */
pci_io_write_config32(dev, SPI_BASE_ADDRESS, prev_spi_cfg);
}
}
static void bootblock_southbridge_init(void)
{
sb700_enable_rom();
sb700_configure_rom();
}

3
src/southbridge/intel/fsp_bd82x6x/me_8.x.c
View File

@ -385,8 +385,7 @@ static int mkhi_get_fwcaps(mefwcaps_sku *cap)
};
/* Send request and wait for response */
if (mei_sendrecv(&mei, &mkhi, &rule_id, &cap_msg, sizeof(cap_msg))
< 0) {
if (mei_sendrecv(&mei, &mkhi, &rule_id, &cap_msg, sizeof(cap_msg)) < 0) {
printk(BIOS_ERR, "ME: GET FWCAPS message failed\n");
return -1;
}

1
src/southbridge/intel/i82870/ioapic.c
View File

@ -14,7 +14,6 @@ static void p64h2_ioapic_enable(device_t dev)
/* We have to enable MEM and Bus Master for IOAPIC */
uint16_t command = PCI_COMMAND_SERR | PCI_COMMAND_PARITY | PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
pci_write_config16(dev, PCI_COMMAND, command);
}

53
src/southbridge/sis/sis966/early_smbus.c
View File

@ -135,10 +135,9 @@ static inline int do_smbus_read_byte(unsigned smbus_io_base, unsigned device, un
smbus_delay();
int i, j;
for(i = 0;i < 0x1000; i++)
{
if (inb(smbus_io_base + 0x00) != 0x08)
{ smbus_delay();
for (i = 0;i < 0x1000; i++) {
if (inb(smbus_io_base + 0x00) != 0x08) {
smbus_delay();
for (j=0;j<0xFFFF;j++);
}
}
@ -502,11 +501,12 @@ static const uint8_t SiS_SiS1183_init[44][3]={
};
/* In => Share Memory size
=> 00h : 0MBytes
=> 02h : 32MBytes
=> 03h : 64MBytes
=> 04h : 128MBytes
=> Others: Reserved
* => 00h : 0MBytes
* => 02h : 32MBytes
* => 03h : 64MBytes
* => 03h : 64MBytes
* => 04h : 128MBytes
* => Others: Reserved
*/
static void Init_Share_Memory(uint8_t ShareSize)
{
@ -517,12 +517,12 @@ static void Init_Share_Memory(uint8_t ShareSize)
}
/* In: => Aperture size
=> 00h : 32MBytes
=> 01h : 64MBytes
=> 02h : 128MBytes
=> 03h : 256MBytes
=> 04h : 512MBytes
=> Others: Reserved
* => 00h : 32MBytes
* => 01h : 64MBytes
* => 02h : 128MBytes
* => 03h : 256MBytes
* => 04h : 512MBytes
* => Others: Reserved
*/
static void Init_Aper_Size(uint8_t AperSize)
{
@ -547,8 +547,8 @@ static void sis_init_stage1(void)
// ========================== NB =============================
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761), 0);
i=0;
while(SiS_NB_init[i][0] != 0)
{ temp8 = pci_read_config8(dev, SiS_NB_init[i][0]);
while (SiS_NB_init[i][0] != 0) {
temp8 = pci_read_config8(dev, SiS_NB_init[i][0]);
temp8 &= SiS_NB_init[i][1];
temp8 |= SiS_NB_init[i][2];
pci_write_config8(dev, SiS_NB_init[i][0], temp8);
@ -558,8 +558,8 @@ static void sis_init_stage1(void)
// ========================== LPC =============================
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS966_LPC), 0);
i=0;
while(SiS_LPC_init[i][0] != 0)
{ temp8 = pci_read_config8(dev, SiS_LPC_init[i][0]);
while (SiS_LPC_init[i][0] != 0) {
temp8 = pci_read_config8(dev, SiS_LPC_init[i][0]);
temp8 &= SiS_LPC_init[i][1];
temp8 |= SiS_LPC_init[i][2];
pci_write_config8(dev, SiS_LPC_init[i][0], temp8);
@ -567,8 +567,8 @@ static void sis_init_stage1(void)
};
// ========================== ACPI =============================
i=0;
while(SiS_ACPI_init[i][0] != 0)
{ temp8 = inb(0x800 + SiS_ACPI_init[i][0]);
while (SiS_ACPI_init[i][0] != 0) {
temp8 = inb(0x800 + SiS_ACPI_init[i][0]);
temp8 &= SiS_ACPI_init[i][1];
temp8 |= SiS_ACPI_init[i][2];
outb(temp8, 0x800 + SiS_ACPI_init[i][0]);
@ -582,8 +582,8 @@ static void sis_init_stage1(void)
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_SIS761_PCIE), 0);
i=0;
while(SiS_NBPCIE_init[i][0] != 0)
{ temp8 = pci_read_config8(dev, SiS_NBPCIE_init[i][0]);
while (SiS_NBPCIE_init[i][0] != 0) {
temp8 = pci_read_config8(dev, SiS_NBPCIE_init[i][0]);
temp8 &= SiS_NBPCIE_init[i][1];
temp8 |= SiS_NBPCIE_init[i][2];
pci_write_config8(dev, SiS_NBPCIE_init[i][0], temp8);
@ -614,8 +614,7 @@ static void sis_init_stage2(void)
dev = pci_locate_device(PCI_ID(PCI_VENDOR_ID_SIS, PCI_DEVICE_ID_SIS_AGP), 0);
i=0;
while(SiS_NBAGP_init[i][0] != 0)
{
while (SiS_NBAGP_init[i][0] != 0) {
temp8 = pci_read_config8(dev, SiS_NBAGP_init[i][0]);
temp8 &= SiS_NBAGP_init[i][1];
temp8 |= SiS_NBAGP_init[i][2];
@ -662,8 +661,8 @@ static void sis_init_stage2(void)
// ========================== ACPI =============================
i=0;
printk(BIOS_DEBUG, "Init ACPI -------->\n");
do
{ temp8 = inb(0x800 + SiS_ACPI_2_init[i][0]);
do {
temp8 = inb(0x800 + SiS_ACPI_2_init[i][0]);
temp8 &= SiS_ACPI_2_init[i][1];
temp8 |= SiS_ACPI_2_init[i][2];
outb(temp8, 0x800 + SiS_ACPI_2_init[i][0]);

3
src/southbridge/sis/sis966/ide.c
View File

@ -103,8 +103,7 @@ printk(BIOS_DEBUG, "IDE_INIT:---------->\n");
{
uint8_t temp8;
int i=0;
while(SiS_SiS5513_init[i][0] != 0)
{
while (SiS_SiS5513_init[i][0] != 0) {
temp8 = pci_read_config8(dev, SiS_SiS5513_init[i][0]);
temp8 &= SiS_SiS5513_init[i][1];
temp8 |= SiS_SiS5513_init[i][2];

40
src/southbridge/sis/sis966/nic.c
View File

@ -73,8 +73,7 @@ static void readApcMacAddr(void)
outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data
printk(BIOS_DEBUG, "MAC addr in APC = ");
for (i = 0x9 ; i <=0xe ; i++)
{
for (i = 0x9 ; i <=0xe ; i++) {
printk(BIOS_DEBUG, "%2.2x",readApcByte(i));
}
printk(BIOS_DEBUG, "\n");
@ -98,8 +97,7 @@ static void set_apc(struct device *dev)
outl(0x80001048,0xcf8);
outl((inl(0xcfc) & 0xfffffffd),0xcfc ); // enable IO78/79h for APC Index/Data
for (i = 0 ; i <3; i++)
{
for (i = 0 ; i <3; i++) {
addr=0x9+2*i;
writeApcByte(addr,(u8)(MacAddr[i]&0xFF));
writeApcByte(addr+1L,(u8)((MacAddr[i]>>8)&0xFF));
@ -135,15 +133,13 @@ static unsigned long ReadEEprom( struct device *dev, u8 *base, u32 Reg)
u32 i;
u32 ulValue;
ulValue = (0x80 | (0x2 << 8) | (Reg << 10)); //BIT_7
write32(base + 0x3c, ulValue);
mdelay(10);
for (i=0 ; i <= LoopNum; i++)
{
for (i=0 ; i <= LoopNum; i++) {
ulValue=read32(base + 0x3c);
if (!(ulValue & 0x0080)) //BIT_7
@ -169,8 +165,6 @@ static int phy_read(u8 *base, unsigned phy_addr, unsigned phy_reg)
u32 Read_Cmd;
u16 usData;
Read_Cmd = ((phy_reg << 11) |
(phy_addr << 6) |
SMI_READ |
@ -180,8 +174,7 @@ static int phy_read(u8 *base, unsigned phy_addr, unsigned phy_reg)
write32(base + 0x44, Read_Cmd);
// Polling SMI_REQ bit to be deasserted indicated read command completed
do
{
do {
// Wait 20 usec before checking status
mdelay(20);
ulValue = read32(base + 0x44);
@ -189,10 +182,7 @@ static int phy_read(u8 *base, unsigned phy_addr, unsigned phy_reg)
//printk(BIOS_DEBUG, "base %x cmd %lx ret val %lx\n", tmp,Read_Cmd,ulValue);
usData=(ulValue>>16);
return usData;
}
// Detect a valid PHY
@ -205,22 +195,18 @@ static int phy_detect(u8 *base,u16 *PhyAddr) //BOOL PHY_Detect()
// Scan all PHY address(0 ~ 31) to find a valid PHY
for (PhyAddress = 0; PhyAddress < 32; PhyAddress++)
{
for (PhyAddress = 0; PhyAddress < 32; PhyAddress++) {
usData=phy_read(base,PhyAddress,StatusReg); // Status register is a PHY's register(offset 01h)
// Found a valid PHY
if ((usData != 0x0) && (usData != 0xffff))
{
if ((usData != 0x0) && (usData != 0xffff)) {
bFoundPhy = TRUE;
break;
}
}
if (!bFoundPhy)
{
if (!bFoundPhy) {
printk(BIOS_DEBUG, "PHY not found !!!!\n");
}
@ -243,8 +229,7 @@ static void nic_init(struct device *dev)
{
u8 temp8;
int i=0;
while(SiS_SiS191_init[i][0] != 0)
{
while (SiS_SiS191_init[i][0] != 0) {
temp8 = pci_read_config8(dev, SiS_SiS191_init[i][0]);
temp8 &= SiS_SiS191_init[i][1];
temp8 |= SiS_SiS191_init[i][2];
@ -260,24 +245,21 @@ static void nic_init(struct device *dev)
res = find_resource(dev, 0x10);
if (!res)
{
if (!res) {
printk(BIOS_DEBUG, "NIC Cannot find resource..\n");
return;
}
base = res2mmio(res, 0, 0);
printk(BIOS_DEBUG, "NIC base address %p\n",base);
if (!(val=phy_detect(base,&PhyAddr)))
{
if (!(val=phy_detect(base,&PhyAddr))) {
printk(BIOS_DEBUG, "PHY detect fail !!!!\n");
return;
}
ulValue=read32(base + 0x38L); // check EEPROM existing
if ((ulValue & 0x0002))
{
if ((ulValue & 0x0002)) {
// read MAC address from EEPROM at first

5
src/southbridge/sis/sis966/sata.c
View File

@ -109,8 +109,6 @@ static void sata_init(struct device *dev)
{
struct southbridge_sis_sis966_config *conf;
conf = dev->chip_info;
printk(BIOS_DEBUG, "SATA_INIT:---------->\n");
@ -118,8 +116,7 @@ static void sata_init(struct device *dev)
{
uint8_t temp8;
int i=0;
while(SiS_SiS1183_init[i][0] != 0)
{
while (SiS_SiS1183_init[i][0] != 0) {
temp8 = pci_read_config8(dev, SiS_SiS1183_init[i][0]);
temp8 &= SiS_SiS1183_init[i][1];
temp8 |= SiS_SiS1183_init[i][2];

4
src/southbridge/sis/sis966/usb.c
View File

@ -58,8 +58,8 @@ static void usb_init(struct device *dev)
uint8_t temp8;
int i=0;
while(SiS_SiS7001_init[i][0] != 0)
{ temp8 = pci_read_config8(dev, SiS_SiS7001_init[i][0]);
while (SiS_SiS7001_init[i][0] != 0) {
temp8 = pci_read_config8(dev, SiS_SiS7001_init[i][0]);
temp8 &= SiS_SiS7001_init[i][1];
temp8 |= SiS_SiS7001_init[i][2];
pci_write_config8(dev, SiS_SiS7001_init[i][0], temp8);

3
src/southbridge/sis/sis966/usb2.c
View File

@ -72,8 +72,7 @@ static void usb2_init(struct device *dev)
//-------------- enable USB2.0 (SiS7002) ----------------------
i = 0;
while (SiS_SiS7002_init[i][0] != 0)
{
while (SiS_SiS7002_init[i][0] != 0) {
temp8 = pci_read_config8(dev, SiS_SiS7002_init[i][0]);
temp8 &= SiS_SiS7002_init[i][1];
temp8 |= SiS_SiS7002_init[i][2];