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soc/intel/common: Calculate and configure SF Mask 1

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MSR IA_SF_QOS_INFO (0xc87) has been introduced since TGL and is used
to find out the NUM_SNOOP_FILTER_WAYS. Bit[5:0] of MSR 0xc87 indicates
the maximum number of bits that may be set in any of the SF MASK
register. Hence, this patch calculates SF way count using below logic:

Calculate SF masks 1:

1. Calculate SFWayCnt = (MSR 0xC87) & 0x3f

2. if CONFIG_SF_MASK_2WAYS_PER_BIT:
	a. SFWayCnt = SFWayCnt / 2

3. Set SF_MASK_1 = ((1 << SFWayCnt) - 1) - SF_MASK_2

Change-Id: Ifd0b7e1a90cad4a4837adf6067fe8301dcd0a941
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51374
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
This commit is contained in:
Subrata Banik
2021-07-30 17:24:38 +05:30
parent 16ab9bdcd5
commit baf922c798
1 changed files with 19 additions and 11 deletions
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30
src/soc/intel/common/block/cpu/car/cache_as_ram.S
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@@ -538,25 +538,33 @@ set_eviction_mask:
shl %cl, %eax
subl $0x01, %eax
program_sf2:
mov %eax, %ebx /* back up IA32_CR_SF_QOS_MASK_2 in ebx */
xorl %edx, %edx
mov $IA32_CR_SF_QOS_MASK_2, %ecx
wrmsr
/*
* SF mask is programmed with the double number of bits than
* the number of ways
* Calculate the SF Mask 1:
* 1. Calcuate SFWayCnt = IA32_SF_QOS_INFO & Bit [5:0]
* 2. if CONFIG_SF_MASK_2WAYS_PER_BIT: SFWayCnt = SFWayCnt / 2
* 3. Set SF_MASK_1 = ((1 << SFWayCnt) - 1) - IA32_CR_SF_QOS_MASK_2
*/
mov $0x01, %eax
mov %edi, %ecx
mov $IA32_SF_QOS_INFO, %ecx
rdmsr
and $IA32_SF_WAY_COUNT_MASK, %eax /* Step 1 */
#if CONFIG(SF_MASK_2WAYS_PER_BIT)
/* Assumption: skip checking SFWayCnt = 1 i.e. 1 way LLC (which is not practical) */
movl $0x01, %ecx /* Step 2 */
shr %cl, %eax
#endif
/* Step 3 */
mov %eax, %ecx
movl $0x01, %eax
shl %cl, %eax
shl %cl, %eax
subl $0x01, %eax /* contains SF mask */
/*
* Program MSR 0x1891 IA32_CR_SF_QOS_MASK_1 with
* total number of LLC ways
*/
movl $IA32_CR_SF_QOS_MASK_1, %ecx
subl $0x01, %eax
sub %ebx, %eax
xorl %edx, %edx
movl $IA32_CR_SF_QOS_MASK_1, %ecx
wrmsr
#endif
/*