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soc/intel/xeon_sp: Drop RMRR entry for USB

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Drop RMRR entry for XHCI controller since it's not under BIOS control.
There's no USB-PS/2 emulation done in SMM, hence it's not needed.

TEST=intel/archercity CRB

Change-Id: I5afd68371d71a00988fe0f8a6045ec5ce2adc6a1
Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81297
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Shuo Liu <shuo.liu@intel.com>
This commit is contained in:
Patrick Rudolph
2024-03-17 11:12:12 +01:00
parent 43d260745a
commit bb50190bec
3 changed files with 1 additions and 33 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/commonlib/bsd/include/commonlib/bsd/cbmem_id.h
View File

@@ -61,7 +61,7 @@
#define CBMEM_ID_STAGEx_META 0x57a9e000
#define CBMEM_ID_STAGEx_CACHE 0x57a9e100
#define CBMEM_ID_STAGEx_RAW 0x57a9e200
#define CBMEM_ID_STORAGE_DATA 0x53746f72
#define CBMEM_ID_STORAGE_DATA 0x53746f72 /* deprecated */
#define CBMEM_ID_TPM_CB_LOG 0x54435041 /* TPM log in coreboot-specific format */
#define CBMEM_ID_TCPA_TCG_LOG 0x54445041 /* TPM log per TPM 1.2 specification */
#define CBMEM_ID_TIMESTAMP 0x54494d45

5
src/soc/intel/xeon_sp/include/soc/acpi.h
View File

@@ -16,11 +16,6 @@ enum acpi_cstate_mode {
CSTATES_C1C6
};
#define MEM_BLK_COUNT 0x140
typedef struct {
uint8_t buf[32];
} MEM_BLK;
unsigned long northbridge_write_acpi_tables(const struct device *device,
unsigned long current, struct acpi_rsdp *rsdp);
unsigned long xeonsp_acpi_create_madt_lapics(unsigned long current);

27
src/soc/intel/xeon_sp/uncore_acpi.c
View File

@@ -439,33 +439,6 @@ static unsigned long acpi_create_atsr(unsigned long current)
static unsigned long acpi_create_rmrr(unsigned long current)
{
uint32_t size = ALIGN_UP(MEM_BLK_COUNT * sizeof(MEM_BLK), 0x1000);
uint32_t *ptr;
// reserve memory
ptr = cbmem_find(CBMEM_ID_STORAGE_DATA);
if (!ptr) {
ptr = cbmem_add(CBMEM_ID_STORAGE_DATA, size);
assert(ptr);
memset(ptr, 0, size);
}
unsigned long tmp = current;
printk(BIOS_DEBUG, "[Reserved Memory Region] PCI Segment Number: 0x%x, Base Address: 0x%x, "
"End Address (limit): 0x%x\n",
0, (uint32_t)ptr, (uint32_t)((uint32_t)ptr + size - 1));
current += acpi_create_dmar_rmrr(current, 0, (uint32_t)ptr,
(uint32_t)((uint32_t)ptr + size - 1));
printk(BIOS_DEBUG, " [PCI Endpoint Device] PCI Bus Number: 0x%x, "
"PCI Path: 0x%x, 0x%x\n",
XHCI_BUS_NUMBER, PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM);
current += acpi_create_dmar_ds_pci(current, XHCI_BUS_NUMBER,
PCH_DEV_SLOT_XHCI, XHCI_FUNC_NUM);
acpi_dmar_rmrr_fixup(tmp, current);
return current;
}