arch/x86/riscv: Use 'all' target to include files in all stages
This adds a few new files to romstage, that will be needed in follow-up patches. Change-Id: I2ba84e0becee883b5becf12e51f40734cad83d7d Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/68839 Reviewed-by: Martin L Roth <gaumless@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Maximilian Brune <maximilian.brune@9elements.com>
This commit is contained in:
committed by
Felix Held
parent
773c7ce90b
commit
bf0b06d9bd
@@ -47,31 +47,34 @@ COMPILER_RT_romstage = $(shell $(GCC_romstage) $(simple_riscv_flags) -print-li
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COMPILER_RT_ramstage = $(shell $(GCC_ramstage) $(simple_riscv_flags) -print-libgcc-file-name)
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## All stages
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all-y += trap_util.S
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all-y += trap_handler.c
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all-y += fp_asm.S
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all-y += misaligned.c
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all-y += sbi.c
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all-y += mcall.c
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all-y += virtual_memory.c
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all-y += boot.c
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all-y += smp.c
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all-y += misc.c
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all-$(ARCH_RISCV_PMP) += pmp.c
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all-y += \
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$(top)/src/lib/memchr.c \
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$(top)/src/lib/memcmp.c \
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$(top)/src/lib/memcpy.c \
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$(top)/src/lib/memmove.c \
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$(top)/src/lib/memset.c
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all-$(CONFIG_RISCV_USE_ARCH_TIMER) += arch_timer.c
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################################################################################
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## bootblock
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################################################################################
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ifeq ($(CONFIG_ARCH_BOOTBLOCK_RISCV),y)
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bootblock-y = bootblock.S
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bootblock-y += trap_util.S
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bootblock-y += trap_handler.c
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bootblock-y += fp_asm.S
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bootblock-y += misaligned.c
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bootblock-y += sbi.c
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bootblock-y += mcall.c
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bootblock-y += virtual_memory.c
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bootblock-y += boot.c
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bootblock-y += smp.c
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bootblock-y += misc.c
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bootblock-$(ARCH_RISCV_PMP) += pmp.c
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bootblock-y += \
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$(top)/src/lib/memchr.c \
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$(top)/src/lib/memcmp.c \
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$(top)/src/lib/memcpy.c \
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$(top)/src/lib/memmove.c \
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$(top)/src/lib/memset.c
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bootblock-$(CONFIG_RISCV_USE_ARCH_TIMER) += arch_timer.c
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$(objcbfs)/bootblock.debug: $$(bootblock-objs)
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@printf " LINK $(subst $(obj)/,,$(@))\n"
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@@ -93,19 +96,7 @@ endif #CONFIG_ARCH_BOOTBLOCK_RISCV
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################################################################################
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ifeq ($(CONFIG_ARCH_ROMSTAGE_RISCV),y)
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romstage-y += boot.c
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romstage-y += romstage.c
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romstage-y += misc.c
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romstage-$(ARCH_RISCV_PMP) += pmp.c
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romstage-y += smp.c
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romstage-y += \
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$(top)/src/lib/memchr.c \
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$(top)/src/lib/memcmp.c \
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$(top)/src/lib/memcpy.c \
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$(top)/src/lib/memmove.c \
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$(top)/src/lib/memset.c
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romstage-$(CONFIG_RISCV_USE_ARCH_TIMER) += arch_timer.c
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# Build the romstage
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@@ -129,28 +120,9 @@ ifeq ($(CONFIG_ARCH_RAMSTAGE_RISCV),y)
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ramstage-y =
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ramstage-y += ramstage.S
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ramstage-y += mcall.c
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ramstage-y += trap_util.S
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ramstage-y += trap_handler.c
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ramstage-y += fp_asm.S
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ramstage-y += misaligned.c
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ramstage-y += sbi.c
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ramstage-y += virtual_memory.c
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ramstage-y += misc.c
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ramstage-y += smp.c
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ramstage-y += boot.c
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ramstage-y += tables.c
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ramstage-y += payload.c
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ramstage-$(ARCH_RISCV_PMP) += pmp.c
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ramstage-y += fit_payload.c
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ramstage-y += \
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$(top)/src/lib/memchr.c \
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$(top)/src/lib/memcmp.c \
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$(top)/src/lib/memcpy.c \
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$(top)/src/lib/memmove.c \
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$(top)/src/lib/memset.c
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ramstage-$(CONFIG_RISCV_USE_ARCH_TIMER) += arch_timer.c
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$(eval $(call create_class_compiler,rmodules,riscv))
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