soc/intel: Remove blank lines before '}' and after '{'

Change-Id: I79b93b0ca446411e2a1feb65d00045e3be85ee8a
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/81489
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>

src/soc/intel/alderlake/chip.h

@@ -323,7 +323,6 @@ enum slew_rate {
 };
 
 struct soc_intel_alderlake_config {
-
 	/* Common struct containing soc config data required by common code */
 	struct soc_intel_common_config common_soc_config;
 

src/soc/intel/apollolake/chip.c

@@ -846,7 +846,6 @@ static void disable_xhci_lfps_pm(void)
 void platform_fsp_notify_status(enum fsp_notify_phase phase)
 {
 	if (phase == END_OF_FIRMWARE) {
-
 		/*
 		 * Before hiding P2SB device and dropping privilege level,
 		 * dump CSE status and disable HECI1 interface.

src/soc/intel/apollolake/chip.h

@@ -33,7 +33,6 @@ enum sata_speed_limit {
 };
 
 struct soc_intel_apollolake_config {
-
 	/* Common structure containing soc config data required by common code*/
 	struct soc_intel_common_config common_soc_config;
 

src/soc/intel/apollolake/cpu.c

@@ -164,7 +164,6 @@ static void pre_mp_init(void)
 	}
 	x86_setup_mtrrs_with_detect();
 	x86_mtrr_check();
-
 }
 
 #if !CONFIG(SOC_INTEL_COMMON_BLOCK_CPU_MPINIT)

src/soc/intel/apollolake/elog.c

@@ -82,7 +82,6 @@ static void pch_log_power_and_resets(const struct chipset_power_state *ps)
 	/* Power Button Override */
 	if (ps->pm1_sts & PRBTNOR_STS)
 		elog_add_event(ELOG_TYPE_POWER_BUTTON_OVERRIDE);
-
 }
 
 void pch_log_state(void)

src/soc/intel/apollolake/romstage.c

@@ -323,7 +323,6 @@ void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)
 	assert(CONFIG(BOOT_DEVICE_MEMORY_MAPPED));
 
 	fsp_version = version;
-
 }
 
 __weak

src/soc/intel/baytrail/acpi.c

@@ -229,7 +229,6 @@ static void generate_p_state_entries(int core)
 	/* Generate the remaining entries */
 	for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
 	     ratio >= ratio_min; ratio -= ratio_step) {
-
 		/* Calculate VID for this ratio */
 		vid = ((ratio - ratio_min) * vid_range_2) / ratio_range_2 + vid_min;
 

src/soc/intel/baytrail/fadt.c

@@ -29,5 +29,4 @@ void acpi_fill_fadt(acpi_fadt_t *fadt)
 			ACPI_FADT_SLEEP_BUTTON |
 			ACPI_FADT_SEALED_CASE | ACPI_FADT_S4_RTC_WAKE |
 			ACPI_FADT_PLATFORM_CLOCK;
-
 }

src/soc/intel/baytrail/smm.c

@@ -70,7 +70,6 @@ static void smm_southcluster_route_gpios(void)
 
 static void smm_southbridge_enable(uint16_t pm1_events)
 {
-
 	printk(BIOS_DEBUG, "Enabling SMIs.\n");
 	if (!smm_save_params[SMM_SAVE_PARAM_PCIE_WAKE_ENABLE])
 		pm1_events |= PCIEXPWAK_DIS;

src/soc/intel/braswell/acpi.c

@@ -257,7 +257,6 @@ static void generate_p_state_entries(int core)
 	/* Generate the remaining entries */
 	for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
 	     ratio >= ratio_min; ratio -= ratio_step) {
-
 		/* Calculate VID for this ratio */
 		vid = ((ratio - ratio_min) * vid_range_2) / ratio_range_2 + vid_min;
 

src/soc/intel/braswell/gpio.c

@@ -89,7 +89,6 @@ static void setup_gpio_route(const struct soc_gpio_map *sw_gpios,
 
 	for (sw_config = sw_gpios, n_config = n_gpios;
 		(!north_done || !south_done); sw_config++, n_config++, gpio++) {
-
 		/* When north config is done */
 		if ((gpio > GP_NORTH_COUNT) || (n_config->pad_conf0 == GPIO_LIST_END))
 			north_done = 1;
@@ -228,7 +227,6 @@ static void setup_gpios(const struct soc_gpio_map *gpios, const struct gpio_bank
 void setup_soc_gpios(struct soc_gpio_config *config, u8 enable_xdp_tap)
 {
 	if (config) {
-
 		/*
 		 * Write the default value 0xffffff to the SW write_access_policy_interrupt_reg
 		 * to allow the SW interrupt mask register to be set

src/soc/intel/braswell/smm.c

@@ -69,7 +69,6 @@ static void smm_southcluster_route_gpios(void)
 
 static void smm_southbridge_enable(uint16_t pm1_events)
 {
-
 	printk(BIOS_DEBUG, "Enabling SMIs.\n");
 	if (!smm_save_params[SMM_SAVE_PARAM_PCIE_WAKE_ENABLE])
 		pm1_events |= PCIEXPWAK_DIS;

src/soc/intel/braswell/southcluster.c

@@ -111,7 +111,6 @@ static void write_pci_config_irqs(void)
 	 */
 	printk(BIOS_DEBUG, "PCI_CFG IRQ: Write PIRQ assignments\n");
 	for (irq_dev = all_devices; irq_dev; irq_dev = irq_dev->next) {
-
 		if ((irq_dev->path.type != DEVICE_PATH_PCI) ||
 			(!irq_dev->enabled))
 			continue;
@@ -288,7 +287,6 @@ static void sc_init(struct device *dev)
 	setup_i8254();
 
 	sc_set_serial_irqs_mode(dev, config->serirq_mode);
-
 }
 
 /*

src/soc/intel/broadwell/gma.c

@@ -253,7 +253,6 @@ u32 gtt_read(u32 reg)
 	u32 val;
 	val = read32(res2mmio(gtt_res, reg, 0));
 	return val;
-
 }
 
 void gtt_write(u32 reg, u32 data)

src/soc/intel/broadwell/pch/lpc.c

@@ -368,7 +368,6 @@ static void pch_pm_init(struct device *dev)
 	/* Set RCBA 0x2b1c[29]=1 if DSP disabled */
 	if (RCBA32(FD) & PCH_DISABLE_ADSPD)
 		RCBA32_OR(0x2b1c, (1 << 29));
-
 }
 
 static void pch_cg_init(struct device *dev)

src/soc/intel/cannonlake/chip.h

@@ -37,7 +37,6 @@ enum chip_pl2_4_cfg {
 };
 
 struct soc_intel_cannonlake_config {
-
 	/* Common struct containing soc config data required by common code */
 	struct soc_intel_common_config common_soc_config;
 

src/soc/intel/cannonlake/finalize.c

@@ -79,7 +79,6 @@ static void pch_finalize(void)
 	 */
 	if (!CONFIG(USE_INTEL_FSP_MP_INIT))
 		cpu_lt_lock_memory();
-
 }
 
 static void soc_finalize(void *unused)

src/soc/intel/cannonlake/include/soc/vr_config.h

@@ -8,7 +8,6 @@
 #include <fsp/api.h>
 
 struct vr_config {
-
 	/* The below settings will take effect when this is set to 1
 	 * for that domain. */
 	uint8_t vr_config_enable;

src/soc/intel/common/block/acpi/acpi.c

@@ -273,7 +273,6 @@ void generate_p_state_entries(int core, int cores_per_package)
 	/* Generate the remaining entries */
 	for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
 	     ratio >= ratio_min; ratio -= ratio_step) {
-
 		/* Calculate power at this ratio */
 		power = common_calculate_power_ratio(power_max, ratio_max, ratio);
 		clock = (ratio * cpu_get_bus_clock()) / KHz;

src/soc/intel/common/block/acpi/acpi_bert.c

@@ -54,7 +54,6 @@ static enum cb_err record_crashlog_into_bert(void **region, size_t *length)
 	bool multi_entry = false;
 	cl_node_t *cl_node = cl_list_head.next;
 	while (cl_node) {
-
 		if ((cl_node->size <= 0) || (!(cl_node->data))) {
 			cl_node = cl_node->next;
 			continue;

src/soc/intel/common/block/cpu/cpulib.c

@@ -154,7 +154,6 @@ void cpu_set_p_state_to_min_clock_ratio(void)
  */
 int cpu_get_burst_mode_state(void)
 {
-
 	msr_t msr;
 	unsigned int eax;
 	int burst_en, burst_cap, burst_state = BURST_MODE_UNKNOWN;

src/soc/intel/common/block/crashlog/crashlog.c

@@ -200,7 +200,6 @@ bool __weak cpu_cl_discovery(void)
 
 int cl_pmc_re_arm_after_reset(void)
 {
-
 	const struct pmc_ipc_buffer req = { 0 };
 	struct pmc_ipc_buffer res;
 	uint32_t cmd_reg;
@@ -400,7 +399,6 @@ void __weak cl_get_pmc_sram_data(cl_node_t *head)
 
 	if (discovery_buf.bits.discov_mechanism == 1) {
 		for (int i = 0; i < descriptor_table.numb_regions; i++) {
-
 			cl_node_t *cl_node = malloc_cl_node(descriptor_table.regions[i].bits.size);
 			if (!cl_node) {
 				printk(BIOS_DEBUG, "failed to allocate cl_node [region = %d]\n", i);
@@ -425,7 +423,6 @@ void __weak cl_get_pmc_sram_data(cl_node_t *head)
 			}
 		}
 	} else {
-
 		cl_node_t *cl_node = malloc_cl_node(discovery_buf.bits.size);
 		if (!cl_node) {
 			printk(BIOS_DEBUG, "failed to allocate cl_node\n");
@@ -458,7 +455,6 @@ pmc_send_re_arm_after_reset:
 
 	/* Clear the SSRAM region after copying the error log */
 	cl_pmc_clear();
-
 }
 
 void cl_get_cpu_sram_data(cl_node_t *head)
@@ -481,7 +477,6 @@ void cl_get_cpu_sram_data(cl_node_t *head)
 	}
 
 	for (int i = 0 ; i < cpu_cl_disc_tab.header.fields.count ; i++) {
-
 		u32 cpu_bar_addr = cl_get_cpu_bar_addr();
 		bool pmc_sram = false;
 

src/soc/intel/common/block/cse/cse.c

@@ -1258,7 +1258,6 @@ static void me_reset_with_count(void)
 			 */
 			printk(BIOS_ERR, "Failed to change ME state in %u attempts!\n",
 									 ME_DISABLE_ATTEMPTS);
-
 		}
 	} else {
 		printk(BIOS_DEBUG, "ME: Resetting");
@@ -1268,7 +1267,6 @@ static void me_reset_with_count(void)
 
 static void cse_set_state(struct device *dev)
 {
-
 	/* (CS)ME Disable Command */
 	struct me_disable_command {
 		struct mkhi_hdr hdr;

src/soc/intel/common/block/cse/cse_lite.c

@@ -83,7 +83,6 @@ enum bp_status {
  * The flags are returned in response to MKHI_BUP_COMMON_GET_BOOT_PARTITION_INFO cmd.
  */
 enum bp_info_flags {
-
 	/* Redundancy Enabled: It indicates CSE supports RO(BP1) and RW(BP2) regions */
 	BP_INFO_REDUNDANCY_EN = 1 << 0,
 
@@ -715,7 +714,6 @@ static void cse_get_bp_entry_range(enum boot_partition_id bp, uint32_t *start_of
 
 	if (end_offset)
 		*end_offset = cse_bp->end_offset;
-
 }
 
 static bool cse_is_rw_bp_status_valid(void)

src/soc/intel/common/block/cse/telemetry.c

@@ -28,7 +28,6 @@ static void process_cse_telemetry_data(void)
 	current_time = timestamp_get();
 
 	for (unsigned int i = 0; i < NUM_CSE_BOOT_PERF_DATA; i++) {
-
 		if (cse_perf_data.timestamp[i] == 0xffffffff) {
 			printk(BIOS_ERR, "%s: CSME timestamps invalid\n", __func__);
 			return;
@@ -48,7 +47,6 @@ static void process_cse_telemetry_data(void)
 
 	/* Normalize TS values to zero-point */
 	for (unsigned int i = zero_point_idx + 1; i < NUM_CSE_BOOT_PERF_DATA; i++) {
-
 		if (ts[i] && ts[i] < ts[zero_point_idx]) {
 			printk(BIOS_ERR, "%s: CSME timestamps invalid,"
 					" wraparound detected\n", __func__);

src/soc/intel/common/block/fast_spi/mmap_boot.c

@@ -170,7 +170,6 @@ uint32_t spi_flash_get_mmap_windows(struct flash_mmap_window *table)
 	bios_mmap_init();
 
 	for (i = 0; i < TOTAL_DECODE_WINDOWS; i++) {
-
 		if (region_sz(&real_dev_windows[i].sub_region) == 0)
 			continue;
 

src/soc/intel/common/block/gpio/gpio.c

@@ -810,7 +810,6 @@ void gpi_clear_get_smi_status(struct gpi_status *sts)
 
 	if (CONFIG(DEBUG_SMI))
 		print_gpi_status(sts);
-
 }
 
 int gpi_status_get(const struct gpi_status *sts, gpio_t pad)

src/soc/intel/common/block/sgx/sgx.c

@@ -163,7 +163,6 @@ static int is_prmrr_approved(void)
  */
 void sgx_configure(void *unused)
 {
-
 	if (!is_sgx_supported() || !is_prmrr_set()) {
 		printk(BIOS_ERR, "SGX: not supported or pre-conditions not met\n");
 		return;

src/soc/intel/common/block/tcss/tcss.c

@@ -41,7 +41,6 @@ static uint32_t tcss_make_alt_mode_cmd_buf_0(int u, int u3, int m)
 	return TCSS_ALT_FIELD(USAGE, u) |
 		TCSS_ALT_FIELD(USB3, u3) |
 		TCSS_ALT_FIELD(MODE, m);
-
 }
 
 static uint32_t tcss_make_alt_mode_cmd_buf_1(int p, int c, int ufp, int dp)
@@ -65,7 +64,6 @@ static uint32_t tcss_make_hpd_mode_cmd(int u, int u3, int hpd_lvl, int hpd_irq)
 		TCSS_HPD_FIELD(USB3, u3) |
 		TCSS_HPD_FIELD(LVL, hpd_lvl) |
 		TCSS_HPD_FIELD(IRQ, hpd_irq);
-
 }
 
 static int send_pmc_req(int cmd_type, const struct pmc_ipc_buffer *req,

src/soc/intel/denverton_ns/bootblock/bootblock.c

@@ -80,7 +80,6 @@ static void sanity_check_pci_mmconf(void)
 
 void bootblock_soc_early_init(void)
 {
-
 #if (CONFIG(CONSOLE_SERIAL))
 	early_uart_init();
 #endif

src/soc/intel/denverton_ns/gpio_dnv.c

@@ -159,7 +159,6 @@ void gpio_configure_dnv_pads(const struct dnv_pad_config *gpio, size_t num)
 	NumberOfGroups = V_PCH_GPIO_GROUP_MAX;
 
 	for (Index = 0; Index < (uint32_t)num; Index++) {
-
 		Dw0RegMask = 0;
 		Dw0Reg = 0;
 		Dw1RegMask = 0;

src/soc/intel/denverton_ns/romstage.c

@@ -146,7 +146,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg)
 
 	/* if ME HECI communication is disabled, apply default one*/
 	if (mupd->FspmConfig.PcdMeHeciCommunication == 0) {
-
 		/* Configure FIA MUX PCD */
 		/* Assume the validating silicon has max lanes. */
 		supported_hsio_lanes = BL_ME_FIA_MUX_LANE_NUM_MAX;

src/soc/intel/denverton_ns/smm.c

@@ -32,7 +32,6 @@ void smm_southbridge_clear_state(void)
 
 static void smm_southbridge_enable(uint16_t pm1_events)
 {
-
 	printk(BIOS_DEBUG, "Enabling SMIs.\n");
 	/* Configure events Disable PCIe wake. */
 	enable_pm1(pm1_events | PCIEXPWAK_DIS);

src/soc/intel/denverton_ns/uart.c

@@ -32,7 +32,6 @@ static void dnv_ns_uart_read_resources(struct device *dev)
 	if (res != NULL)
 		res->flags = 0;
 	compact_resources(dev);
-
 }
 
 static struct device_operations uart_ops = {

src/soc/intel/elkhartlake/chip.h

@@ -109,7 +109,6 @@ enum sata_speed_limit {
 };
 
 struct soc_intel_elkhartlake_config {
-
 	/* Common struct containing soc config data required by common code */
 	struct soc_intel_common_config common_soc_config;
 

src/soc/intel/elkhartlake/include/soc/meminit.h

@@ -52,7 +52,6 @@ struct spd_info {
 
 /* Board-specific memory dq mapping information */
 struct mb_cfg {
-
 	/*
 	 * For each channel, there are 6 sets of DQ byte mappings,
 	 * where each set has a package 0 and a package 1 value (package 0

src/soc/intel/elkhartlake/meminit.c

@@ -88,7 +88,6 @@ static void meminit_channels(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_c
 void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg,
 			const struct spd_info *spd_info, bool half_populated)
 {
-
 	if (spd_info->read_type == READ_SMBUS) {
 		for (int i = 0; i < NUM_DIMM_SLOT; i++)
 			mem_cfg->SpdAddressTable[i] = spd_info->spd_spec.spd_smbus_address[i];

src/soc/intel/elkhartlake/systemagent.c

@@ -60,5 +60,4 @@ void soc_systemagent_init(struct device *dev)
 	config = config_of_soc();
 	soc_config = &config->power_limits_config;
 	set_power_limits(MOBILE_SKU_PL1_TIME_SEC, soc_config);
-
 }

src/soc/intel/jasperlake/chip.h

@@ -58,7 +58,6 @@ static const struct {
 };
 
 struct soc_intel_jasperlake_config {
-
 	/* Common struct containing soc config data required by common code */
 	struct soc_intel_common_config common_soc_config;
 

src/soc/intel/jasperlake/gpio.c

@@ -32,7 +32,6 @@ static const struct reset_mapping rst_map_com0[] = {
  * linux/drivers/pinctrl/intel/pinctrl-jasperlake.c
  */
 static const struct pad_group jsl_community0_groups[] = {
-
 	INTEL_GPP_BASE(GPP_F0, GPP_F0, GPP_F19, 320),		/* GPP_F */
 	INTEL_GPP(GPP_F0, GPIO_SPI0_IO_2, GPIO_SPI0_CLK_LOOPBK),/* SPI0 */
 	INTEL_GPP_BASE(GPP_F0, GPP_B0, GPIO_GSPI1_CLK_LOOPBK, 32),/* GPP_B */

src/soc/intel/jasperlake/include/soc/meminit.h

@@ -52,7 +52,6 @@ struct spd_info {
 
 /* Board-specific memory dq mapping information */
 struct mb_cfg {
-
 	/*
 	 * For each channel, there are 6 sets of DQ byte mappings,
 	 * where each set has a package 0 and a package 1 value (package 0

src/soc/intel/jasperlake/meminit.c

@@ -88,7 +88,6 @@ static void meminit_channels(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_c
 void memcfg_init(FSP_M_CONFIG *mem_cfg, const struct mb_cfg *board_cfg,
 			const struct spd_info *spd_info, bool half_populated)
 {
-
 	if (spd_info->read_type == READ_SMBUS) {
 		for (int i = 0; i < NUM_DIMM_SLOT; i++)
 			mem_cfg->SpdAddressTable[i] = spd_info->spd_spec.spd_smbus_address[i];

src/soc/intel/jasperlake/romstage/romstage.c

@@ -139,7 +139,6 @@ void mainboard_romstage_entry(void)
 	fsp_memory_init(s3wake);
 	pmc_set_disb();
 	if (!s3wake) {
-
 		/*
 		 * cse_fw_sync() must be called after DRAM initialization as
 		 * HMRFPO_ENABLE HECI command (which is used by cse_fw_sync())

src/soc/intel/meteorlake/chip.h

@@ -146,7 +146,6 @@ enum slew_rate {
 };
 
 struct soc_intel_meteorlake_config {
-
 	/* Common struct containing soc config data required by common code */
 	struct soc_intel_common_config common_soc_config;
 

src/soc/intel/meteorlake/crashlog.c

@@ -110,7 +110,6 @@ void cl_get_pmc_sram_data(cl_node_t *head)
 
 	/* process crashlog records */
 	for (int i = 0; i < descriptor_table.numb_regions + 1; i++) {
-
 		u32 sram_base = 0;
 		bool pmc_sram = true;
 		printk(BIOS_DEBUG, "Region[0x%x].Tag=0x%x offset=0x%x, size=0x%x\n",

src/soc/intel/meteorlake/finalize.c

@@ -27,7 +27,6 @@
 
 static void pch_handle_sideband(config_t *config)
 {
-
 }
 
 static void pch_finalize(void)

src/soc/intel/skylake/chip.h

@@ -31,7 +31,6 @@ enum skylake_i2c_voltage {
 };
 
 struct soc_intel_skylake_config {
-
 	/* Common struct containing soc config data required by common code */
 	struct soc_intel_common_config common_soc_config;
 

src/soc/intel/skylake/fadt.c

@@ -25,5 +25,4 @@ void soc_fill_fadt(acpi_fadt_t *fadt)
 	if (config->s0ix_enable)
 		fadt->flags |= ACPI_FADT_LOW_PWR_IDLE_S0;
 
-
 }

src/soc/intel/skylake/gpio.c

@@ -181,5 +181,4 @@ uint32_t soc_gpio_pad_config_fixup(const struct pad_config *cfg,
 	if (cfg->pad >= GPP_F4 && cfg->pad <= GPP_F11 && dw_reg == 1)
 		reg_val = reg_val & ~(PAD_CFG1_TOL_1V8);
 	return reg_val;
-
 }

src/soc/intel/skylake/include/soc/vr_config.h

@@ -8,7 +8,6 @@
 #include <fsp/api.h>
 
 struct vr_config {
-
 	/*
 	 * The below settings will take effect when this is set to 1
 	 * for that domain.

src/soc/intel/tigerlake/chip.h

@@ -116,7 +116,6 @@ enum ddi_port_config {
 };
 
 struct soc_intel_tigerlake_config {
-
 	/* Common struct containing soc config data required by common code */
 	struct soc_intel_common_config common_soc_config;
 

src/soc/intel/tigerlake/crashlog_lib.c

@@ -116,7 +116,6 @@ u32 cl_get_cpu_tmp_bar(void)
 
 bool  cl_pmc_sram_has_mmio_access(void)
 {
-
 	if (pci_read_config16(PCH_DEV_SRAM, PCI_VENDOR_ID) == 0xFFFF) {
 		printk(BIOS_ERR, "PMC SSRAM PCI device is disabled.\n");
 		return false;

src/soc/intel/tigerlake/fsp_params.c

@@ -563,7 +563,6 @@ void platform_fsp_silicon_init_params_cb(FSPS_UPD *supd)
 
 		params->PchFivrExtV1p05RailIccMaximum =
 			config->ext_fivr_settings.v1p05_icc_max_ma;
-
 	}
 
 	/* Apply minimum assertion width settings if non-zero */

src/soc/intel/tigerlake/meminit.c

@@ -176,5 +176,4 @@ void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg,
 	default:
 		die("Unsupported memory type(%d)\n", mb_cfg->type);
 	}
-
 }

src/soc/intel/tigerlake/romstage/fsp_params.c

@@ -221,7 +221,6 @@ static void soc_memory_init_params(FSP_M_CONFIG *m_cfg,
 				       config->ibecc.region_mask);
 		}
 	}
-
 }
 
 void platform_fsp_memory_init_params_cb(FSPM_UPD *mupd, uint32_t version)

src/soc/intel/tigerlake/romstage/romstage.c

@@ -150,5 +150,4 @@ void mainboard_romstage_entry(void)
 
 		save_dimm_info();
 	}
-
 }

src/soc/intel/xeon_sp/chip_common.c

@@ -433,7 +433,6 @@ bool is_ubox_domain(struct device *dev)
 
 	return (strstr(dev->name, DOMAIN_TYPE_UBX0) ||
 		strstr(dev->name, DOMAIN_TYPE_UBX1));
-
 }
 
 bool is_cxl_domain(struct device *dev)

src/soc/intel/xeon_sp/cpx/soc_acpi.c

@@ -130,7 +130,6 @@ void soc_power_states_generation(int core, int cores_per_package)
 	/* Generate the remaining entries */
 	for (ratio = ratio_min + ((num_entries - 1) * ratio_step);
 	     ratio >= ratio_min; ratio -= ratio_step) {
-
 		/* Calculate power at this ratio */
 		power = common_calculate_power_ratio(power_max, ratio_max, ratio);
 		clock = ratio * CONFIG_CPU_BCLK_MHZ;

src/soc/intel/xeon_sp/finalize.c

@@ -82,7 +82,6 @@ static void bios_done_finalize(void *unused)
 	/* bios_done_msr() only defined for some Xeon-SP, such as SPR-SP */
 	if (mp_run_on_all_cpus(&bios_done_msr, NULL) != CB_SUCCESS)
 		printk(BIOS_ERR, "Fail to set BIOS_DONE MSR\n");
-
 }
 
 BOOT_STATE_INIT_ENTRY(BS_PAYLOAD_LOAD, BS_ON_ENTRY, soc_finalize, NULL);

src/soc/intel/xeon_sp/romstage.c

@@ -36,7 +36,6 @@ __weak void mainboard_memory_init_params(FSPM_UPD *mupd)
 
 __weak void mainboard_rtc_failed(void)
 {
-
 }
 __weak void save_dimm_info(void) { }
 __weak void mainboard_ewl_check(void) { }

src/soc/intel/xeon_sp/smihandler.c

@@ -83,7 +83,6 @@ void smihandler_soc_at_finalize(void)
  */
 void cpu_smi_handler(void)
 {
-
 }
 
 /* This is needed by common SMM code */

src/soc/intel/xeon_sp/spr/chip.c

@@ -29,7 +29,6 @@
 
 __weak void mainboard_silicon_init_params(FSPS_UPD *params)
 {
-
 }
 
 /* UPD parameters to be initialized before SiliconInit */

src/soc/intel/xeon_sp/spr/romstage.c

@@ -149,7 +149,6 @@ void soc_config_iio(FSPM_UPD *mupd, const UPD_IIO_PCIE_PORT_CONFIG_ENTRY
 	mupd->FspmConfig.IioPcieConfigTableNumber = CONFIG_MAX_SOCKET; /* Set by mainboard */
 
 	for (socket = 0; socket < CONFIG_MAX_SOCKET; socket++) {
-
 		/* Configures DMI, IOU0 ~ IOU4 */
 		for (port = 0; port < IIO_PORT_SETTINGS; port++) {
 			const UPD_IIO_PCIE_PORT_CONFIG_ENTRY *port_cfg =

src/soc/intel/xeon_sp/spr/soc_acpi.c

@@ -140,7 +140,6 @@ void soc_power_states_generation(int core, int cores_per_package)
 	/* Generate the remaining entries */
 	for (ratio = ratio_min + ((num_entries - 1) * ratio_step); ratio >= ratio_min;
 	     ratio -= ratio_step) {
-
 		/* Calculate power at this ratio */
 		power = common_calculate_power_ratio(power_max, ratio_max, ratio);
 		clock = ratio * CONFIG_CPU_BCLK_MHZ;

src/soc/intel/xeon_sp/spr/soc_util.c

@@ -165,7 +165,6 @@ void soc_set_mrc_cold_boot_flag(bool cold_boot_required)
 	printk(BIOS_SPEW, "MRC status: 0x%02x want 0x%02x\n", mrc_status, new_mrc_status);
 	if (new_mrc_status != mrc_status)
 		cmos_write(new_mrc_status, CMOS_OFFSET_MRC_STATUS);
-
 }
 
 bool is_memtype_reserved(uint16_t mem_type)

src/soc/intel/xeon_sp/uncore.c

@@ -253,7 +253,6 @@ static void mc_add_dram_resources(struct device *dev, int *res_count)
 		res = reserved_ram_from_to(dev, index++, (dpr.top - dpr.size) * MiB,
 					   dpr.top * MiB);
 		LOG_RESOURCE("dpr", dev, res);
-
 	}
 
 	/* Mark TSEG/SMM region as reserved */