sravan/system76-coreboot
1
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

soc/intel: Decouple HECI disabling interface from HECI disable Kconfig

Browse Source 
This patch decouples HECI disabling interface a.k.a SMM or PCR or PMC
IPC etc. from DISABLE_HECI1_AT_PRE_BOOT kconfig as Intel ME BWG
recommends to disable the CSE PCI device while CSE is in
software temporary disable state.

BUG=b:228789015
TEST=Able to build google/redrix.

Signed-off-by: Subrata Banik <subratabanik@google.com>
Change-Id: I66abc04d5e195515165a77b0166d004f17d029e7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/63823
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Kangheui Won <khwon@chromium.org>
This commit is contained in:
Subrata Banik
2022-04-25 16:59:35 +05:30
committed by Felix Held
parent 09106f75f1
commit c176fc2dfb
5 changed files with 7 additions and 7 deletions
Download Patch File Download Diff File Expand all files Collapse all files

2
src/soc/intel/alderlake/Kconfig
View File

@@ -88,7 +88,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
select SOC_INTEL_COMMON_BLOCK_SCS if SOC_INTEL_ALDERLAKE_PCH_N
select SOC_INTEL_COMMON_BLOCK_HDA
select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT
select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC
select SOC_INTEL_COMMON_BLOCK_IPU
select SOC_INTEL_COMMON_BLOCK_IRQ
select SOC_INTEL_COMMON_BLOCK_MEMINIT

2
src/soc/intel/apollolake/Kconfig
View File

@@ -82,7 +82,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_GPIO_ITSS_POL_CFG
select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY
select SOC_INTEL_COMMON_BLOCK_GRAPHICS
select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR if DISABLE_HECI1_AT_PRE_BOOT
select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR
select SOC_INTEL_COMMON_BLOCK_ITSS
select SOC_INTEL_COMMON_BLOCK_I2C
select SOC_INTEL_COMMON_BLOCK_LPC

6
src/soc/intel/cannonlake/Kconfig
View File

@@ -7,7 +7,7 @@ config SOC_INTEL_COFFEELAKE
select FSP_USES_CB_STACK
select HAVE_EXP_X86_64_SUPPORT
select HAVE_INTEL_FSP_REPO
select HECI_DISABLE_USING_SMM if DISABLE_HECI1_AT_PRE_BOOT
select HECI_DISABLE_USING_SMM
select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
config SOC_INTEL_WHISKEYLAKE
@@ -15,7 +15,7 @@ config SOC_INTEL_WHISKEYLAKE
select SOC_INTEL_CANNONLAKE_BASE
select FSP_USES_CB_STACK
select HAVE_INTEL_FSP_REPO
select HECI_DISABLE_USING_SMM if DISABLE_HECI1_AT_PRE_BOOT
select HECI_DISABLE_USING_SMM
select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
config SOC_INTEL_COMETLAKE
@@ -25,7 +25,7 @@ config SOC_INTEL_COMETLAKE
select HAVE_INTEL_FSP_REPO
select PMC_IPC_ACPI_INTERFACE if DISABLE_HECI1_AT_PRE_BOOT
select SOC_INTEL_CONFIGURE_DDI_A_4_LANES
select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT
select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC
select SOC_INTEL_COMMON_BASECODE if SOC_INTEL_CSE_LITE_SKU
config SOC_INTEL_COMETLAKE_1

2
src/soc/intel/skylake/Kconfig
View File

@@ -63,7 +63,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_GPIO_PADCFG_PADTOL
select SOC_INTEL_COMMON_BLOCK_GSPI
select SOC_INTEL_COMMON_BLOCK_HDA
select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR if DISABLE_HECI1_AT_PRE_BOOT
select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PCR
select SOC_INTEL_COMMON_BLOCK_PMC_DISCOVERABLE
select SOC_INTEL_COMMON_BLOCK_SA
select SOC_INTEL_COMMON_BLOCK_SCS

2
src/soc/intel/tigerlake/Kconfig
View File

@@ -61,7 +61,7 @@ config CPU_SPECIFIC_OPTIONS
select SOC_INTEL_COMMON_BLOCK_GPIO_IOSTANDBY
select SOC_INTEL_COMMON_BLOCK_GSPI_VERSION_2
select SOC_INTEL_COMMON_BLOCK_HDA
select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC if DISABLE_HECI1_AT_PRE_BOOT
select SOC_INTEL_COMMON_BLOCK_HECI1_DISABLE_USING_PMC_IPC
select SOC_INTEL_COMMON_BLOCK_IRQ
select SOC_INTEL_COMMON_BLOCK_MEMINIT
select SOC_INTEL_COMMON_BLOCK_PCIE_RTD3