mb/google/brya/var/ghost: Update memory DQ map

Follow latest schematic 6/27 to update the DQ map.

BUG=b:240006200
BRANCH=firmware-brya-14505.B
TEST=build passed.

Signed-off-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Change-Id: I8d0de04a001cab53a245185707ebc9da7a501ec4
Reviewed-on: https://review.coreboot.org/c/coreboot/+/66122
Reviewed-by: Derek Huang <derekhuang@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Jack Rosenthal <jrosenth@chromium.org>
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
This commit is contained in:
Eric Lai 2022-07-25 16:00:04 +08:00 committed by Paul Fagerburg
parent 93928194c4
commit c1b01ea9f5

View File

@ -17,36 +17,36 @@ static const struct mb_cfg baseboard_memcfg = {
*/
.lpx_dq_map = {
.ddr0 = {
.dq0 = { 5, 0, 4, 1, 2, 6, 7, 3, },
.dq1 = { 9, 12, 8, 13, 15, 10, 14, 11, },
.dq0 = { 5, 0, 4, 1, 2, 6, 7, 3 },
.dq1 = { 11, 15, 13, 12, 10, 14, 8, 9 },
},
.ddr1 = {
.dq0 = { 9, 10, 11, 8, 13, 15, 14, 12, },
.dq1 = { 0, 3, 1, 2, 7, 5, 6, 4, },
.dq0 = { 9, 10, 11, 8, 13, 14, 12, 15 },
.dq1 = { 0, 2, 1, 3, 7, 5, 6, 4 },
},
.ddr2 = {
.dq0 = { 9, 13, 8, 12, 15, 10, 14, 11, },
.dq1 = { 7, 6, 4, 5, 0, 3, 1, 2, },
.dq0 = { 3, 7, 2, 6, 4, 1, 5, 0 },
.dq1 = { 12, 14, 15, 13, 11, 10, 8, 9 },
},
.ddr3 = {
.dq0 = { 3, 7, 2, 6, 4, 1, 5, 0, },
.dq1 = { 12, 14, 15, 13, 11, 10, 8, 9, },
.dq0 = { 15, 14, 12, 13, 10, 9, 11, 8 },
.dq1 = { 7, 6, 4, 5, 0, 3, 1, 2 },
},
.ddr4 = {
.dq0 = { 15, 14, 12, 13, 10, 9, 8, 11, },
.dq1 = { 7, 5, 4, 6, 2, 0, 1, 3, },
.dq0 = { 15, 14, 12, 13, 10, 9, 8, 11 },
.dq1 = { 1, 3, 0, 2, 5, 6, 7, 4 },
},
.ddr5 = {
.dq0 = { 9, 10, 11, 8, 12, 15, 13, 14, },
.dq1 = { 3, 7, 2, 6, 0, 4, 5, 1, },
.dq0 = { 9, 10, 11, 8, 12, 15, 13, 14 },
.dq1 = { 3, 7, 2, 6, 0, 4, 5, 1 },
},
.ddr6 = {
.dq0 = { 3, 2, 1, 0, 7, 5, 6, 4, },
.dq1 = { 12, 13, 10, 9, 14, 11, 8, 15, },
.dq0 = { 11, 8, 10, 9, 12, 14, 13, 15 },
.dq1 = { 0, 7, 1, 2, 6, 4, 3, 5 },
},
.ddr7 = {
.dq0 = { 11, 8, 10, 9, 12, 14, 13, 15, },
.dq1 = { 1, 7, 0, 2, 5, 3, 4, 6, },
.dq0 = { 1, 2, 3, 0, 7, 5, 6, 4 },
.dq1 = { 15, 14, 11, 13, 8, 9, 12, 10 },
},
},
@ -59,12 +59,12 @@ static const struct mb_cfg baseboard_memcfg = {
*/
.lpx_dqs_map = {
.ddr0 = { .dqs0 = 0, .dqs1 = 1 },
.ddr1 = { .dqs0 = 0, .dqs1 = 1 },
.ddr1 = { .dqs0 = 1, .dqs1 = 0 },
.ddr2 = { .dqs0 = 0, .dqs1 = 1 },
.ddr3 = { .dqs0 = 0, .dqs1 = 1 },
.ddr4 = { .dqs0 = 0, .dqs1 = 1 },
.ddr5 = { .dqs0 = 0, .dqs1 = 1 },
.ddr6 = { .dqs0 = 0, .dqs1 = 1 },
.ddr3 = { .dqs0 = 1, .dqs1 = 0 },
.ddr4 = { .dqs0 = 1, .dqs1 = 0 },
.ddr5 = { .dqs0 = 1, .dqs1 = 0 },
.ddr6 = { .dqs0 = 1, .dqs1 = 0 },
.ddr7 = { .dqs0 = 0, .dqs1 = 1 },
},