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AGESA,binaryPI boards: Drop unused variables in ASL

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Change-Id: I1d1323ab8bb8565c05fd50697e29c61f9932a2c7
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50646
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki
2021-02-14 00:06:39 +02:00
parent c8d7c4834a
commit c308f021d2
29 changed files with 0 additions and 208 deletions
Download Patch File Download Diff File Expand all files Collapse all files

6
src/mainboard/amd/gardenia/acpi/mainboard.asl
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@ -1,10 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */

8
src/mainboard/amd/inagua/acpi/mainboard.asl
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@ -1,14 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* Data to be patched by the BIOS during POST */
/* FIXME the patching is not done yet! */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Scope(\_SI) { Scope(\_SI) {
Method(_SST, 1) { Method(_SST, 1) {

6
src/mainboard/amd/olivehill/acpi/mainboard.asl
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@ -1,13 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
/* AcpiGpe0Blk */ /* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)

6
src/mainboard/amd/padmelon/acpi/mainboard.asl
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@ -1,10 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */

8
src/mainboard/amd/parmer/acpi/mainboard.asl
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@ -1,15 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* Data to be patched by the BIOS during POST */
/* FIXME the patching is not done yet! */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
/* AcpiGpe0Blk */ /* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)

8
src/mainboard/amd/persimmon/acpi/mainboard.asl
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@ -1,14 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* Data to be patched by the BIOS during POST */
/* FIXME the patching is not done yet! */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Scope(\_SI) { Scope(\_SI) {
Method(_SST, 1) { Method(_SST, 1) {

8
src/mainboard/amd/south_station/acpi/mainboard.asl
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@ -1,14 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* Data to be patched by the BIOS during POST */
/* FIXME the patching is not done yet! */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Scope(\_SI) { Scope(\_SI) {
Method(_SST, 1) { Method(_SST, 1) {

8
src/mainboard/amd/thatcher/acpi/mainboard.asl
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@ -1,15 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* Data to be patched by the BIOS during POST */
/* FIXME the patching is not done yet! */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
/* AcpiGpe0Blk */ /* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)

8
src/mainboard/amd/union_station/acpi/mainboard.asl
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@ -1,14 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* Data to be patched by the BIOS during POST */
/* FIXME the patching is not done yet! */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Scope(\_SI) { Scope(\_SI) {
Method(_SST, 1) { Method(_SST, 1) {

8
src/mainboard/asrock/e350m1/acpi/mainboard.asl
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@ -1,14 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* Data to be patched by the BIOS during POST */
/* FIXME the patching is not done yet! */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Scope(\_SI) { Scope(\_SI) {
Method(_SST, 1) { Method(_SST, 1) {

6
src/mainboard/asrock/imb-a180/acpi/mainboard.asl
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@ -1,13 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
/* AcpiGpe0Blk */ /* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)

8
src/mainboard/asus/a88xm-e/acpi/mainboard.asl
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@ -1,15 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* Data to be patched by the BIOS during POST */
/* FIXME the patching is not done yet! */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */
/* Base address of PCIe config space */ /* Base address of PCIe config space */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS)
/* Length of PCIe config space, 1MB each bus */ /* Length of PCIe config space, 1MB each bus */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER))
/* Base address of HPET table */ /* Base address of HPET table */
Name(HPBA, 0xFED00000)

6
src/mainboard/asus/am1i-a/acpi/mainboard.asl
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@ -1,13 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
/* AcpiGpe0Blk */ /* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)

8
src/mainboard/asus/f2a85-m/acpi/mainboard.asl
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@ -1,12 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* Data to be patched by the BIOS during POST */
/* FIXME the patching is not done yet! */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */

6
src/mainboard/bap/ode_e20XX/acpi/mainboard.asl
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@ -1,13 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
/* AcpiGpe0Blk */ /* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)

6
src/mainboard/biostar/a68n_5200/acpi/mainboard.asl
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@ -1,13 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
/* AcpiGpe0Blk */ /* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)

6
src/mainboard/biostar/am1ml/acpi/mainboard.asl
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@ -1,13 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
/* AcpiGpe0Blk */ /* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)

8
src/mainboard/elmex/pcm205400/acpi/mainboard.asl
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@ -1,14 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* Data to be patched by the BIOS during POST */
/* FIXME the patching is not done yet! */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Scope(\_SI) { Scope(\_SI) {
Method(_SST, 1) { Method(_SST, 1) {

8
src/mainboard/gizmosphere/gizmo/acpi/mainboard.asl
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@ -1,14 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* Data to be patched by the BIOS during POST */
/* FIXME the patching is not done yet! */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Scope(\_SI) { Scope(\_SI) {
Method(_SST, 1) { Method(_SST, 1) {

6
src/mainboard/gizmosphere/gizmo2/acpi/mainboard.asl
View File

@ -1,13 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
/* AcpiGpe0Blk */ /* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)

6
src/mainboard/google/kahlee/variants/baseboard/include/baseboard/acpi/mainboard.asl
View File

@ -1,10 +1,5 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* Memory related values */
Name (LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
Name (PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name (PBLN, 0x0) /* Length of BIOS area */
/* Base address of PCIe config space */ /* Base address of PCIe config space */
Name (PCBA, CONFIG_MMCONF_BASE_ADDRESS) Name (PCBA, CONFIG_MMCONF_BASE_ADDRESS)
@ -12,4 +7,3 @@ Name (PCBA, CONFIG_MMCONF_BASE_ADDRESS)
Name (PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) Name (PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER))
/* Base address of HPET table */ /* Base address of HPET table */
Name (HPBA, 0xFED00000)

6
src/mainboard/hp/abm/acpi/mainboard.asl
View File

@ -1,13 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
/* AcpiGpe0Blk */ /* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)

8
src/mainboard/hp/pavilion_m6_1035dx/acpi/mainboard.asl
View File

@ -1,15 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* Data to be patched by the BIOS during POST */
/* FIXME the patching is not done yet! */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
/* AcpiGpe0Blk */ /* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)

8
src/mainboard/jetway/nf81-t56n-lf/acpi/mainboard.asl
View File

@ -1,14 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* Data to be patched by the BIOS during POST */
/* FIXME the patching is not done yet! */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Scope(\_SI) { Scope(\_SI) {
Method(_SST, 1) { Method(_SST, 1) {

8
src/mainboard/lenovo/g505s/acpi/mainboard.asl
View File

@ -1,15 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* Data to be patched by the BIOS during POST */
/* FIXME the patching is not done yet! */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
/* AcpiGpe0Blk */ /* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)

8
src/mainboard/lippert/frontrunner-af/dsdt.asl
View File

@ -13,15 +13,7 @@ DefinitionBlock (
{ /* Start of ASL file */ { /* Start of ASL file */
#include <acpi/dsdt_top.asl> #include <acpi/dsdt_top.asl>
/* Data to be patched by the BIOS during POST */
/* FIXME the patching is not done yet! */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
/* USB overcurrent mapping pins. */ /* USB overcurrent mapping pins. */
Name(UOM0, 0) Name(UOM0, 0)

8
src/mainboard/msi/ms7721/acpi/mainboard.asl
View File

@ -1,12 +1,4 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* Data to be patched by the BIOS during POST */
/* FIXME the patching is not done yet! */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */

8
src/mainboard/pcengines/apu1/acpi/mainboard.asl
View File

@ -1,14 +1,6 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* Data to be patched by the BIOS during POST */
/* FIXME the patching is not done yet! */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
Scope(\_SI) { Scope(\_SI) {
Method(_SST, 1) { Method(_SST, 1) {

6
src/mainboard/pcengines/apu2/acpi/mainboard.asl
View File

@ -1,13 +1,7 @@
/* SPDX-License-Identifier: GPL-2.0-only */ /* SPDX-License-Identifier: GPL-2.0-only */
/* Memory related values */
Name(LOMH, 0x0) /* Start of unused memory in C0000-E0000 range */
Name(PBAD, 0x0) /* Address of BIOS area (If TOM2 != 0, Addr >> 16) */
Name(PBLN, 0x0) /* Length of BIOS area */
Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */ Name(PCBA, CONFIG_MMCONF_BASE_ADDRESS) /* Base address of PCIe config space */
Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */ Name(PCLN, Multiply(0x100000, CONFIG_MMCONF_BUS_NUMBER)) /* Length of PCIe config space, 1MB each bus */
Name(HPBA, 0xFED00000) /* Base address of HPET table */
/* AcpiGpe0Blk */ /* AcpiGpe0Blk */
OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04) OperationRegion(GP0B, SystemMemory, 0xfed80814, 0x04)