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Trivial. Spell checking.

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Signed-off-by: Zheng Bao <zheng.bao@amd.com>
Acked-by: Zheng Bao <zheng.bao@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5923 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Zheng Bao 2010-10-08 05:08:47 +00:00 committed by Zheng Bao
parent 3d682fe888
commit c3af12fb8a
4 changed files with 18 additions and 18 deletions
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16
src/northbridge/amd/amdmct/mct/mct_d.c
View File

@ -655,7 +655,7 @@ static void MCTMemClr_D(struct MCTStatStruc *pMCTstat,
{ {
/* Initiates a memory clear operation for all node. The mem clr /* Initiates a memory clear operation for all node. The mem clr
* is done in paralel. After the memclr is complete, all processors * is done in parallel. After the memclr is complete, all processors
* status are checked to ensure that memclr has completed. * status are checked to ensure that memclr has completed.
*/ */
u8 Node; u8 Node;
@ -856,7 +856,7 @@ static void StartupDCT_D(struct MCTStatStruc *pMCTstat,
* HW memory clear process that the chip is capable of. The sooner * HW memory clear process that the chip is capable of. The sooner
* that dram init is set for all nodes, the faster the memory system * that dram init is set for all nodes, the faster the memory system
* initialization can complete. Thus, the init loop is unrolled into * initialization can complete. Thus, the init loop is unrolled into
* two loops so as to start the processeses for non BSP nodes sooner. * two loops so as to start the processes for non BSP nodes sooner.
* This procedure will not wait for the process to finish. * This procedure will not wait for the process to finish.
* Synchronization is handled elsewhere. * Synchronization is handled elsewhere.
*/ */
@ -878,7 +878,7 @@ static void StartupDCT_D(struct MCTStatStruc *pMCTstat,
reg = 0x78 + reg_off; reg = 0x78 + reg_off;
val = Get_NB32(dev, reg); val = Get_NB32(dev, reg);
/* Setting this bit forces a 1T window with hard left /* Setting this bit forces a 1T window with hard left
* pass/fail edge and a probabalistic right pass/fail * pass/fail edge and a probabilistic right pass/fail
* edge. LEFT edge is referenced for final * edge. LEFT edge is referenced for final
* receiver enable position.*/ * receiver enable position.*/
val |= 1 << DqsRcvEnTrain; val |= 1 << DqsRcvEnTrain;
@ -1038,7 +1038,7 @@ static u8 AutoCycTiming_D(struct MCTStatStruc *pMCTstat,
} else { } else {
byte = mctRead_SPD(smbaddr, SPD_TRCRFC); byte = mctRead_SPD(smbaddr, SPD_TRCRFC);
if (byte & 0xF0) { if (byte & 0xF0) {
val++; /* round up in case fractional extention is non-zero.*/ val++; /* round up in case fractional extension is non-zero.*/
} }
} }
if (Trc < val) if (Trc < val)
@ -1496,7 +1496,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
DramConfigMisc = 0; DramConfigMisc = 0;
DramConfigMisc2 = 0; DramConfigMisc2 = 0;
/* set bank addessing and Masks, plus CS pops */ /* set bank addressing and Masks, plus CS pops */
SPDSetBanks_D(pMCTstat, pDCTstat, dct); SPDSetBanks_D(pMCTstat, pDCTstat, dct);
if (pDCTstat->ErrCode == SC_StopError) if (pDCTstat->ErrCode == SC_StopError)
goto AutoConfig_exit; goto AutoConfig_exit;
@ -1582,7 +1582,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
} }
if (!(Status & (1 << SB_Registered))) if (!(Status & (1 << SB_Registered)))
DramConfigLo |= 1 << UnBuffDimm; /* Unbufferd DIMMs */ DramConfigLo |= 1 << UnBuffDimm; /* Unbuffered DIMMs */
if (mctGet_NVbits(NV_ECC_CAP)) if (mctGet_NVbits(NV_ECC_CAP))
if (Status & (1 << SB_ECCDIMMs)) if (Status & (1 << SB_ECCDIMMs))
@ -3405,7 +3405,7 @@ static void SetODTTriState(struct MCTStatStruc *pMCTstat,
if (pDCTstat->CSPresent & (1 << cs)) { if (pDCTstat->CSPresent & (1 << cs)) {
odt &= ~(1 << (cs / 2)); odt &= ~(1 << (cs / 2));
/* if quad-rank capable platform clear adtitional pins */ /* if quad-rank capable platform clear additional pins */
if (max_dimms != MAX_CS_SUPPORTED) { if (max_dimms != MAX_CS_SUPPORTED) {
if (pDCTstat->CSPresent & (1 << (cs + 1))) if (pDCTstat->CSPresent & (1 << (cs + 1)))
odt &= ~(4 << (cs / 2)); odt &= ~(4 << (cs / 2));
@ -3768,7 +3768,7 @@ static void mct_BeforeDQSTrain_D(struct MCTStatStruc *pMCTstat,
* Silicon Status: Fixed In Rev B0 * Silicon Status: Fixed In Rev B0
* *
* Bug#15880: Determine validity of reset settings for DDR PHY timing. * Bug#15880: Determine validity of reset settings for DDR PHY timing.
* Solutiuon: At least, set WrDqs fine delay to be 0 for DDR2 training. * Solution: At least, set WrDqs fine delay to be 0 for DDR2 training.
*/ */
for (Node = 0; Node < 8; Node++) { for (Node = 0; Node < 8; Node++) {

12
src/northbridge/amd/amdmct/mct_ddr3/mct_d.c
View File

@ -656,7 +656,7 @@ static void MCTMemClr_D(struct MCTStatStruc *pMCTstat,
{ {
/* Initiates a memory clear operation for all node. The mem clr /* Initiates a memory clear operation for all node. The mem clr
* is done in paralel. After the memclr is complete, all processors * is done in parallel. After the memclr is complete, all processors
* status are checked to ensure that memclr has completed. * status are checked to ensure that memclr has completed.
*/ */
u8 Node; u8 Node;
@ -868,7 +868,7 @@ static void StartupDCT_D(struct MCTStatStruc *pMCTstat,
* HW memory clear process that the chip is capable of. The sooner * HW memory clear process that the chip is capable of. The sooner
* that dram init is set for all nodes, the faster the memory system * that dram init is set for all nodes, the faster the memory system
* initialization can complete. Thus, the init loop is unrolled into * initialization can complete. Thus, the init loop is unrolled into
* two loops so as to start the processeses for non BSP nodes sooner. * two loops so as to start the processes for non BSP nodes sooner.
* This procedure will not wait for the process to finish. * This procedure will not wait for the process to finish.
* Synchronization is handled elsewhere. * Synchronization is handled elsewhere.
*/ */
@ -1520,7 +1520,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
DramConfigMisc = 0; DramConfigMisc = 0;
DramConfigMisc2 = 0; DramConfigMisc2 = 0;
/* set bank addessing and Masks, plus CS pops */ /* set bank addressing and Masks, plus CS pops */
SPDSetBanks_D(pMCTstat, pDCTstat, dct); SPDSetBanks_D(pMCTstat, pDCTstat, dct);
if (pDCTstat->ErrCode == SC_StopError) if (pDCTstat->ErrCode == SC_StopError)
goto AutoConfig_exit; goto AutoConfig_exit;
@ -1547,7 +1547,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
else else
val = 6; val = 6;
DramControl &= ~0xFF; DramControl &= ~0xFF;
DramControl |= val; /* RdPrtInit = 6 for Cx CPU */ DramControl |= val; /* RdPtrInit = 6 for Cx CPU */
if (mctGet_NVbits(NV_CLKHZAltVidC3)) if (mctGet_NVbits(NV_CLKHZAltVidC3))
DramControl |= 1<<16; /* check */ DramControl |= 1<<16; /* check */
@ -1570,7 +1570,7 @@ static u8 AutoConfig_D(struct MCTStatStruc *pMCTstat,
} }
if (!(Status & (1 << SB_Registered))) if (!(Status & (1 << SB_Registered)))
DramConfigLo |= 1 << UnBuffDimm; /* Unbufferd DIMMs */ DramConfigLo |= 1 << UnBuffDimm; /* Unbuffered DIMMs */
if (mctGet_NVbits(NV_ECC_CAP)) if (mctGet_NVbits(NV_ECC_CAP))
if (Status & (1 << SB_ECCDIMMs)) if (Status & (1 << SB_ECCDIMMs))
@ -3511,7 +3511,7 @@ static void mct_BeforeDQSTrain_D(struct MCTStatStruc *pMCTstat,
* Silicon Status: Fixed In Rev B0 * Silicon Status: Fixed In Rev B0
* *
* Bug#15880: Determine validity of reset settings for DDR PHY timing. * Bug#15880: Determine validity of reset settings for DDR PHY timing.
* Solutiuon: At least, set WrDqs fine delay to be 0 for DDR3 training. * Solution: At least, set WrDqs fine delay to be 0 for DDR3 training.
*/ */
for (Node = 0; Node < 8; Node++) { for (Node = 0; Node < 8; Node++) {
pDCTstat = pDCTstatA + Node; pDCTstat = pDCTstatA + Node;