soc/amd: Create AMD common reset code

This allows us to use the same file for PCO, CZN, MDN, PHX, & Glinda.
PCO supports the warm reset, and future chips can support it by setting
the SOC_AMD_SUPPORTS_WARM_RESET option.

Signed-off-by: Martin Roth <gaumless@gmail.com>
Change-Id: Ib6459e7ab82aacbe57b4c2fc5bbb3759dc5266f7
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72658
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Martin Roth
2023-02-01 11:55:28 -07:00
committed by Felix Held
parent 9f5a5eefc3
commit c46c15b592
4 changed files with 56 additions and 1 deletions

View File

@@ -3,9 +3,11 @@
#ifndef AMD_BLOCK_RESET_H
#define AMD_BLOCK_RESET_H
#include <console/console.h>
#include <amdblocks/acpimmio.h>
#include <arch/cache.h>
#include <console/console.h>
#include <halt.h>
#include <soc/southbridge.h>
void do_warm_reset(void);
void do_cold_reset(void);
@@ -28,4 +30,10 @@ static inline __noreturn void cold_reset(void)
halt();
}
static inline void set_resets_to_cold(void)
{
/* De-assert and then assert all PwrGood signals on CF9 reset. */
pm_write16(PWR_RESET_CFG, pm_read16(PWR_RESET_CFG) | TOGGLE_ALL_PWR_GOOD);
}
#endif /* AMD_BLOCK_RESET_H */

View File

@@ -15,3 +15,14 @@ config SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE
platforms that use FSP for hardware initialization.
endif # SOC_AMD_COMMON_BLOCK_PM
config SOC_AMD_COMMON_BLOCK_RESET
bool
help
Select this option to use AMD common reset driver support.
config SOC_AMD_SUPPORTS_WARM_RESET
bool
depends on SOC_AMD_COMMON_BLOCK_RESET
help
Select this option if the chip supports warm reset.

View File

@@ -1,5 +1,13 @@
## SPDX-License-Identifier: GPL-2.0-only
bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_PM) += pmlib.c
bootblock-$(CONFIG_SOC_AMD_COMMON_BLOCK_RESET) += reset.c
verstage_x86-$(CONFIG_SOC_AMD_COMMON_BLOCK_RESET) += reset.c
romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE) += chipset_state.c
romstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_RESET) += reset.c
ramstage-$(CONFIG_SOC_AMD_COMMON_BLOCK_RESET) += reset.c
smm-$(CONFIG_SOC_AMD_COMMON_BLOCK_PM_CHIPSET_STATE_SAVE) += chipset_state.c

View File

@@ -0,0 +1,28 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <arch/io.h>
#include <cf9_reset.h>
#include <reset.h>
#include <soc/southbridge.h>
#include <amdblocks/acpimmio.h>
#include <amdblocks/reset.h>
void do_cold_reset(void)
{
set_resets_to_cold();
outb(RST_CPU | SYS_RST, RST_CNT);
}
void do_warm_reset(void)
{
/* If warm resets are not supported, executed a cold reset */
if (!CONFIG(SOC_AMD_SUPPORTS_WARM_RESET))
do_cold_reset(); /* Does not return */
outb(RST_CPU | SYS_RST, RST_CNT);
}
void do_board_reset(void)
{
do_cold_reset();
}