mb/system76/adl-p: oryp9: Enable dGPU

Change-Id: If78241c197a552a5d93e4bfdadcb175d68194e3d
Signed-off-by: Tim Crawford <tcrawford@system76.com>
This commit is contained in:
Tim Crawford
2022-07-24 15:31:13 -06:00
parent 0ec21e466e
commit c6a45cdef5
6 changed files with 43 additions and 1 deletions

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@@ -3,6 +3,7 @@ if BOARD_SYSTEM76_DARP8 || BOARD_SYSTEM76_LEMP11 || BOARD_SYSTEM76_ORYP9
config BOARD_SPECIFIC_OPTIONS
def_bool y
select BOARD_ROMSIZE_KB_32768
select DRIVERS_GFX_NVIDIA if BOARD_SYSTEM76_ORYP9
select DRIVERS_I2C_HID
select DRIVERS_INTEL_PMC
select DRIVERS_INTEL_USB4_RETIMER

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@@ -1,4 +1,5 @@
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/include
CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/$(VARIANT_DIR)/include
bootblock-y += bootblock.c
bootblock-y += variants/$(VARIANT_DIR)/gpio_early.c

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@@ -1,5 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#if CONFIG(DRIVERS_GFX_NVIDIA)
#include <variant/gpio.h>
#endif
#define EC_GPE_SCI 0x6E
#define EC_GPE_SWI 0x6B
#include <ec/system76/ec/acpi/ec.asl>
@@ -8,5 +12,11 @@ Scope (\_SB) {
#include "sleep.asl"
Scope (PCI0) {
#include "backlight.asl"
#if CONFIG(DRIVERS_GFX_NVIDIA)
Scope (PEG2) {
#include <drivers/gfx/nvidia/acpi/tigerlake.asl>
}
#endif
}
}

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@@ -0,0 +1,13 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#ifndef VARIANT_GPIO_H
#define VARIANT_GPIO_H
#include <soc/gpio.h>
#define DGPU_RST_N GPP_B2
#define DGPU_PWR_EN GPP_A14
#define DGPU_GC6 GPP_A7
#define DGPU_SSID 0x65f51558
#endif

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@@ -18,13 +18,17 @@ chip soc/intel/alderlake
device domain 0 on
subsystemid 0x1558 0x65f5 inherit
device ref pcie5 off
device ref pcie5 on
# CPU PCIe RP#2 x8, Clock 3 (DGPU)
register "cpu_pcie_rp[CPU_RP(2)]" = "{
.clk_src = 3,
.clk_req = 3,
.flags = PCIE_RP_LTR,
}"
chip drivers/gfx/nvidia
device pci 00.0 on end # VGA controller
device pci 00.1 on end # Audio device
end
end
device ref igpu on
register "ddi_portA_config" = "1"

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@@ -1,7 +1,9 @@
/* SPDX-License-Identifier: GPL-2.0-only */
#include <drivers/gfx/nvidia/gpu.h>
#include <soc/meminit.h>
#include <soc/romstage.h>
#include <variant/gpio.h>
void mainboard_memory_init_params(FSPM_UPD *mupd)
{
@@ -18,6 +20,17 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
};
const bool half_populated = false;
const struct nvidia_gpu_config config = {
.power_gpio = DGPU_PWR_EN,
.reset_gpio = DGPU_RST_N,
.enable = true,
};
// Enable dGPU power
nvidia_set_power(&config);
// Set primary display to internal graphics
mupd->FspmConfig.PrimaryDisplay = 0;
mupd->FspmConfig.PchHdaAudioLinkHdaEnable = 1;
mupd->FspmConfig.DmiMaxLinkSpeed = 4;
mupd->FspmConfig.GpioOverride = 0;